z8kgen: temp file to generate z8k-opc.h from
z8k-dis.c: fixed various bugs
This commit is contained in:
Steve Chamberlain
parent
5e9d510ea6
commit
c38f5470c2
519
opcodes/z8k-dis.c
Normal file
519
opcodes/z8k-dis.c
Normal file
@ -0,0 +1,519 @@
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#include <stdio.h>
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#define DEFINE_TABLE
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#include "z8k-opc.h"
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static void fetch_data();
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static void fetch_instr();
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static unsigned long get_val();
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static int is_segmented();
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static int lookup_instr();
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static void output_instr();
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static void unpack_instr();
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static void unparse_instr();
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typedef struct {
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unsigned char instr_buf[24];
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unsigned long bytes_fetched;
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unsigned long tabl_index;
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unsigned char instr_asmsrc[80];
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unsigned long arg_reg[0x0f];
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unsigned long immediate;
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unsigned long displacement;
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unsigned long address;
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unsigned long cond_code;
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unsigned long ctrl_code;
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unsigned long flags;
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unsigned long interrupts;
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} instr_data_s;
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static char *codes[16] =
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{
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"f",
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"lt",
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"le",
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"ule",
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"ov/pe",
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"mi",
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"eq",
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"c/ult",
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"t",
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"ge",
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"gt",
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"ugt",
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"nov/po",
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"pl",
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"ne",
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"nc/uge"
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};
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int print_insn_z8k(addr, in_buf, stream)
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unsigned long addr;
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unsigned char *in_buf;
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FILE *stream;
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{
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instr_data_s instr_data;
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fetch_instr( &in_buf, &instr_data );
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if ( lookup_instr( &instr_data ))
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{
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fetch_data( &in_buf, &instr_data );
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unpack_instr( &instr_data );
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unparse_instr( &instr_data );
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output_instr( &instr_data, addr, stream );
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return instr_data.bytes_fetched;
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}
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else {
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fprintf(stream,".word %02x%02x", in_buf[0], in_buf[1]);
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return 2;
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}
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}
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static void fetch_data( in_buf, instr_data )
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unsigned char **in_buf;
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instr_data_s *instr_data;
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{
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int bytes_2fetch;
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bytes_2fetch = z8k_table[instr_data->tabl_index].length -
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instr_data->bytes_fetched;
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while( bytes_2fetch-- )
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instr_data->instr_buf[instr_data->bytes_fetched++] = *(*in_buf)++;
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}
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static void fetch_instr( in_buf, instr_data )
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unsigned char **in_buf;
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instr_data_s *instr_data;
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{
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unsigned int loop = 2;
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instr_data->bytes_fetched = 0;
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while( loop-- )
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instr_data->instr_buf[instr_data->bytes_fetched++] = *(*in_buf)++;
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}
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static unsigned long get_val( instr_buf, start_nibl, nibls_long )
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unsigned char (*instr_buf)[];
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unsigned int start_nibl, nibls_long;
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{
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unsigned long ret_val;
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unsigned char byte_val, nibl_val;
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unsigned int nibl_index, nibl_lim;
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unsigned int byte_index;
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unsigned int which_nibl;
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ret_val = 0;
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nibl_lim = start_nibl + nibls_long;
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for( nibl_index = start_nibl; nibl_index < nibl_lim; nibl_index++ )
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{
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byte_index = nibl_index / 2;
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which_nibl = nibl_index % 2;
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switch( which_nibl )
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{
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case 0:
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byte_val = (*instr_buf)[byte_index];
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nibl_val = (byte_val >> 4) & 0x0f;
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break;
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case 1:
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nibl_val = byte_val & 0x0f;
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break;
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}
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ret_val = (ret_val << 4) | nibl_val;
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}
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return ret_val;
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}
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static int is_segmented()
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{
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return 1;
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}
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static
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int lookup_instr( instr_data )
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instr_data_s *instr_data;
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{
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int nibl_index, tabl_index;
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int tablent_found, nibl_matched;
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unsigned short instr_nibl;
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unsigned short tabl_datum, datum_class, datum_value;
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nibl_matched = 0;
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tabl_index = 0;
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while( ! nibl_matched && z8k_table[tabl_index].name)
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{
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nibl_matched = 1;
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for( nibl_index = 0; nibl_index < 4 && nibl_matched; nibl_index++ )
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{
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instr_nibl = get_val( instr_data->instr_buf, nibl_index, 1 );
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tabl_datum = z8k_table[tabl_index].byte_info[nibl_index];
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datum_class = tabl_datum & CLASS_MASK;
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datum_value = ~CLASS_MASK & tabl_datum;
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switch( datum_class )
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{
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case CLASS_BIT:
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if( datum_value != instr_nibl ) nibl_matched = 0;
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break;
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case CLASS_00II:
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if( ! ((~instr_nibl) & 0x4) ) nibl_matched = 0;
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break;
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case CLASS_01II:
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if( ! (instr_nibl & 0x4) ) nibl_matched = 0;
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break;
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case CLASS_0CCC:
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if( ! ((~instr_nibl) & 0x8) ) nibl_matched = 0;
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break;
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case CLASS_1CCC:
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if( ! (instr_nibl & 0x8) ) nibl_matched = 0;
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break;
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case CLASS_0DISP7:
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if( ! ((~instr_nibl) & 0x8) ) nibl_matched = 0;
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nibl_index += 1;
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break;
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case CLASS_1DISP7:
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if( ! (instr_nibl & 0x8) ) nibl_matched = 0;
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nibl_index += 1;
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break;
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case CLASS_REGN0:
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if( instr_nibl == 0 ) nibl_matched = 0;
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break;
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default:
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break;
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}
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}
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tabl_index++;
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}
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instr_data->tabl_index = tabl_index;
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return nibl_matched;
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}
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static void output_instr( instr_data, addr, stream )
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instr_data_s *instr_data;
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unsigned long addr;
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FILE *stream;
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{
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int loop, loop_limit;
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unsigned long word_val;
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char tmp_str[20];
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char out_str[100];
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strcpy( out_str, "" );
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loop_limit = z8k_table[instr_data->tabl_index].length / 2;
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for( loop = 0; loop < loop_limit; loop++ )
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{
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word_val = get_val( instr_data->instr_buf, loop * 4, 4 );
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sprintf( tmp_str, "%04x ", word_val );
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strcat( out_str, tmp_str );
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}
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while( loop++ < 5 )
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{
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strcat( out_str, " " );
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}
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strcat( out_str, instr_data->instr_asmsrc );
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fprintf( stream, "%s", out_str );
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}
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static void unpack_instr( instr_data )
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instr_data_s *instr_data;
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{
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int nibl_index, word_index;
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int nibl_count, loop;
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unsigned short instr_nibl, instr_byte, instr_word, instr_long;
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unsigned short tabl_datum, datum_class, datum_value;
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nibl_count = 0;
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loop = 0;
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while( z8k_table[instr_data->tabl_index].byte_info[loop] != 0 )
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{
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word_index = (int) nibl_count / 4;
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nibl_index = (int) nibl_count % 4;
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switch( nibl_index )
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{
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case 0:
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instr_nibl = get_val( instr_data->instr_buf, nibl_count, 1 );
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instr_byte = get_val( instr_data->instr_buf, nibl_count, 2 );
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instr_word = get_val( instr_data->instr_buf, nibl_count, 4 );
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instr_long = get_val( instr_data->instr_buf, nibl_count, 8 );
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break;
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case 1:
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instr_nibl = get_val( instr_data->instr_buf, nibl_count, 1 );
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break;
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case 2:
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instr_nibl = get_val( instr_data->instr_buf, nibl_count, 1 );
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instr_byte = get_val( instr_data->instr_buf, nibl_count, 2 );
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break;
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case 3:
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instr_nibl = get_val( instr_data->instr_buf, nibl_count, 1 );
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break;
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default:
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break;
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}
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tabl_datum = z8k_table[instr_data->tabl_index].byte_info[loop];
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datum_class = tabl_datum & CLASS_MASK;
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datum_value = tabl_datum & ~CLASS_MASK;
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switch( datum_class )
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{
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case CLASS_X:
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instr_data->address = instr_nibl;
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break;
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case CLASS_BA:
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instr_data->displacement = instr_nibl;
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break;
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case CLASS_BX:
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instr_data->arg_reg[datum_value] = instr_nibl;
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break;
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case CLASS_DISP:
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switch( datum_value )
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{
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case ARG_DISP16:
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instr_data->displacement = instr_word;
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nibl_count += 3;
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break;
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case ARG_DISP12:
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instr_data->displacement = instr_word & 0x0fff;
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nibl_count += 2;
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break;
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default:
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break;
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}
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break;
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case CLASS_IMM:
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switch( datum_value )
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{
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case ARG_IMM4:
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instr_data->immediate = instr_nibl;
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break;
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case ARG_IMM8:
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instr_data->immediate = instr_byte;
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nibl_count += 1;
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break;
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case ARG_IMM16:
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instr_data->immediate = instr_word;
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nibl_count += 3;
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break;
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case ARG_IMM32:
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instr_data->immediate = instr_long;
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nibl_count += 7;
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break;
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case ARG_IMMN:
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instr_data->immediate = instr_nibl -1;
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break;
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/* ????? */
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/* missing ARG_IMMNMINUS1 */
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case ARG_IMM_1:
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instr_data->immediate = 1;
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break;
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case ARG_IMM_2:
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instr_data->immediate = 2;
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break;
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case ARG_NIM16:
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instr_data->immediate = (- instr_word);
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nibl_count += 3;
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break;
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case ARG_IMM2:
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instr_data->immediate = instr_nibl & 0x3;
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break;
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default:
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break;
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}
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break;
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case CLASS_CC:
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instr_data->cond_code = instr_nibl;
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break;
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case CLASS_CTRL:
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instr_data->ctrl_code = instr_nibl;
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break;
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case CLASS_DA:
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case CLASS_ADDRESS:
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if( is_segmented() )
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{
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if( instr_nibl & 0x8 )
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{
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instr_data->address = ((instr_word & 0x7f00) << 8) +
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(instr_long & 0xffff);
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nibl_count += 7;
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}
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else
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{
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instr_data->address = ((instr_word & 0x7f00) << 8) +
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(instr_word & 0x00ff);
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nibl_count += 3;
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}
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}
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else
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{
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instr_data->address = instr_word;
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nibl_count += 3;
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}
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break;
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case CLASS_0CCC:
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instr_data->cond_code = instr_nibl & 0x7;
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break;
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case CLASS_1CCC:
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instr_data->cond_code = instr_nibl & 0x7;
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break;
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case CLASS_0DISP7:
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instr_data->displacement = instr_byte & 0x7f;
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nibl_count += 1;
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break;
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case CLASS_1DISP7:
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instr_data->displacement = instr_byte & 0x7f;
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nibl_count += 1;
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break;
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case CLASS_01II:
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instr_data->interrupts = instr_nibl & 0x3;
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break;
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case CLASS_00II:
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instr_data->interrupts = instr_nibl & 0x3;
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break;
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case CLASS_BIT:
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/* do nothing */
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break;
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case CLASS_IR:
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instr_data->arg_reg[datum_value] = instr_nibl;
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break;
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case CLASS_FLAGS:
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instr_data->flags = instr_nibl;
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break;
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case CLASS_REG:
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instr_data->arg_reg[datum_value] = instr_nibl;
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break;
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case CLASS_REG_BYTE:
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instr_data->arg_reg[datum_value] = instr_nibl;
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break;
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case CLASS_REG_WORD:
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instr_data->arg_reg[datum_value] = instr_nibl;
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break;
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case CLASS_REG_QUAD:
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instr_data->arg_reg[datum_value] = instr_nibl;
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break;
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case CLASS_REG_LONG:
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instr_data->arg_reg[datum_value] = instr_nibl;
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break;
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case CLASS_REGN0:
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instr_data->arg_reg[datum_value] = instr_nibl;
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break;
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default:
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break;
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}
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loop += 1;
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nibl_count += 1;
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}
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}
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static void unparse_instr( instr_data )
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instr_data_s *instr_data;
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{
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unsigned short tabl_datum, datum_class, datum_value;
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int loop, loop_limit;
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char out_str[80], tmp_str[25];
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sprintf( out_str, "\t%-10s", z8k_table[instr_data->tabl_index].name );
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loop_limit = z8k_table[instr_data->tabl_index].noperands;
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for( loop = 0; loop < loop_limit; loop++ )
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{
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if( loop )
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strcat( out_str, "," );
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tabl_datum = z8k_table[instr_data->tabl_index].arg_info[loop];
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datum_class = tabl_datum & CLASS_MASK;
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datum_value = tabl_datum & ~CLASS_MASK;
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switch( datum_class )
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{
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case CLASS_X:
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sprintf( tmp_str, "0x%0x(R%d)", instr_data->address,
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instr_data->arg_reg[datum_value] );
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strcat( out_str, tmp_str );
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break;
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case CLASS_BA:
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sprintf( tmp_str, "r%d(#%x)", instr_data->arg_reg[datum_value],
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instr_data->displacement);
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strcat( out_str, tmp_str );
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break;
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case CLASS_BX:
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sprintf( tmp_str, "r%d(R%d)", instr_data->arg_reg[datum_value],
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instr_data->arg_reg[ARG_RX] );
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strcat( out_str, tmp_str );
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break;
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case CLASS_DISP:
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sprintf( tmp_str, "#0x%0x", instr_data->displacement );
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strcat( out_str, tmp_str );
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break;
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case CLASS_IMM:
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sprintf( tmp_str, "#0x%0x", instr_data->immediate );
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strcat( out_str, tmp_str );
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break;
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case CLASS_CC:
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sprintf( tmp_str, "%s", codes[instr_data->cond_code] );
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strcat( out_str, tmp_str );
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break;
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case CLASS_CTRL:
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sprintf( tmp_str, "0x%0x", instr_data->ctrl_code );
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strcat( out_str, tmp_str );
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break;
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case CLASS_DA:
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case CLASS_ADDRESS:
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sprintf( tmp_str, "#0x%0x", instr_data->address );
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strcat( out_str, tmp_str );
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break;
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case CLASS_IR:
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sprintf( tmp_str, "@R%d", instr_data->arg_reg[datum_value] );
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strcat( out_str, tmp_str );
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break;
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case CLASS_FLAGS:
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sprintf( tmp_str, "0x%0x", instr_data->flags );
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strcat( out_str, tmp_str );
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break;
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case CLASS_REG_BYTE:
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if( instr_data->arg_reg[datum_value] >= 0x8 )
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{
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sprintf( tmp_str, "rl%d",
|
||||
instr_data->arg_reg[datum_value] - 0x8 );
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf( tmp_str, "rh%d", instr_data->arg_reg[datum_value] );
|
||||
}
|
||||
strcat( out_str, tmp_str );
|
||||
break;
|
||||
case CLASS_REG_WORD:
|
||||
sprintf( tmp_str, "r%d", instr_data->arg_reg[datum_value] );
|
||||
strcat( out_str, tmp_str );
|
||||
break;
|
||||
case CLASS_REG_QUAD:
|
||||
sprintf( tmp_str, "rq%d", instr_data->arg_reg[datum_value] );
|
||||
strcat( out_str, tmp_str );
|
||||
break;
|
||||
case CLASS_REG_LONG:
|
||||
sprintf( tmp_str, "rr%d", instr_data->arg_reg[datum_value] );
|
||||
strcat( out_str, tmp_str );
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
strcpy( instr_data->instr_asmsrc, out_str );
|
||||
}
|
||||
867
opcodes/z8k-opc.h
Normal file
867
opcodes/z8k-opc.h
Normal file
@ -0,0 +1,867 @@
|
||||
/* THIS FILE IS AUTOMAGICALLY GENERATED, DON'T EDIT IT */
|
||||
#define ARG_MASK 0x0f
|
||||
#define ARG_RS 0x01
|
||||
#define ARG_RD 0x02
|
||||
#define ARG_RA 0x03
|
||||
#define ARG_RB 0x04
|
||||
#define ARG_RR 0x05
|
||||
#define ARG_RX 0x06
|
||||
#define ARG_IMM4 0x01
|
||||
#define ARG_IMM8 0x02
|
||||
#define ARG_IMM16 0x03
|
||||
#define ARG_IMM32 0x04
|
||||
#define ARG_IMMN 0x05
|
||||
#define ARG_IMMNMINUS1 0x05
|
||||
#define ARG_IMM_1 0x06
|
||||
#define ARG_IMM_2 0x07
|
||||
#define ARG_DISP16 0x08
|
||||
#define ARG_NIM16 0x09
|
||||
#define ARG_IMM2 0x0a
|
||||
#define ARG_DISP12 0x0b
|
||||
#define ARG_DISP8 0x0c
|
||||
#define CLASS_MASK 0xfff0
|
||||
#define CLASS_X 0x10
|
||||
#define CLASS_BA 0x20
|
||||
#define CLASS_DA 0x30
|
||||
#define CLASS_BX 0x40
|
||||
#define CLASS_DISP 0x50
|
||||
#define CLASS_IMM 0x60
|
||||
#define CLASS_CC 0x70
|
||||
#define CLASS_CTRL 0x80
|
||||
#define CLASS_ADDRESS 0xd0
|
||||
#define CLASS_0CCC 0xe0
|
||||
#define CLASS_1CCC 0xf0
|
||||
#define CLASS_0DISP7 0x100
|
||||
#define CLASS_1DISP7 0x200
|
||||
#define CLASS_01II 0x300
|
||||
#define CLASS_00II 0x400
|
||||
#define CLASS_BIT 0x500
|
||||
#define CLASS_FLAGS 0x600
|
||||
#define CLASS_IR 0x700
|
||||
#define CLASS_DISP8 0x800
|
||||
#define CLASS_REG 0x7000
|
||||
#define CLASS_REG_BYTE 0x2000
|
||||
#define CLASS_REG_WORD 0x3000
|
||||
#define CLASS_REG_QUAD 0x4000
|
||||
#define CLASS_REG_LONG 0x5000
|
||||
#define CLASS_REGN0 0x8000
|
||||
typedef struct {
|
||||
char *name;
|
||||
unsigned short arg_info[4];
|
||||
unsigned short byte_info[10];
|
||||
int noperands;
|
||||
int length;
|
||||
int idx;
|
||||
} opcode_entry_type;
|
||||
#ifdef DEFINE_TABLE
|
||||
opcode_entry_type z8k_table[] = {
|
||||
{"adc",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+11,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,0},
|
||||
{"adcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+11,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,1},
|
||||
{"add",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,2},
|
||||
{"add",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,3},
|
||||
{"add",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,4},
|
||||
{"add",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,5},
|
||||
{"add",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,6},
|
||||
{"addb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,7},
|
||||
{"addb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,8},
|
||||
{"addb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,9},
|
||||
{"addb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+0,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,10},
|
||||
{"addb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,11},
|
||||
{"addl",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,12},
|
||||
{"addl",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,13},
|
||||
{"addl",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,14},
|
||||
{"addl",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),},
|
||||
{CLASS_BIT+1,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,15},
|
||||
{"addl",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,16},
|
||||
{"and",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,17},
|
||||
{"and",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,18},
|
||||
{"and",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,19},
|
||||
{"and",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+0,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,20},
|
||||
{"and",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,21},
|
||||
{"andb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,22},
|
||||
{"andb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,23},
|
||||
{"andb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,24},
|
||||
{"andb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+0,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,25},
|
||||
{"andb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,26},
|
||||
{"bit",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+2,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,27},
|
||||
{"bit",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,28},
|
||||
{"bit",{CLASS_DA,CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+7,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,29},
|
||||
{"bit",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+10,CLASS_BIT+7,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,30},
|
||||
{"bit",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,31},
|
||||
{"bitb",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+2,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,32},
|
||||
{"bitb",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,33},
|
||||
{"bitb",{CLASS_DA,CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+6,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,34},
|
||||
{"bitb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+10,CLASS_BIT+6,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,35},
|
||||
{"bitb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,36},
|
||||
{"call",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+1,CLASS_BIT+15,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,37},
|
||||
{"call",{CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+15,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},1,4,38},
|
||||
{"call",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+5,CLASS_BIT+15,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},1,4,39},
|
||||
{"calr",{CLASS_DISP,},
|
||||
{CLASS_BIT+13,CLASS_DISP+(ARG_DISP12),0,0,0,0,0,0,0,},1,2,40},
|
||||
{"clr",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,41},
|
||||
{"clr",{CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},1,2,42},
|
||||
{"clr",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,43},
|
||||
{"clr",{CLASS_REG_WORD+(ARG_RD),},
|
||||
{CLASS_BIT+8,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,44},
|
||||
{"clrb",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,45},
|
||||
{"clrb",{CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},1,2,46},
|
||||
{"clrb",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,47},
|
||||
{"clrb",{CLASS_REG_BYTE+(ARG_RD),},
|
||||
{CLASS_BIT+8,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,48},
|
||||
{"com",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,49},
|
||||
{"com",{CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},1,2,50},
|
||||
{"com",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,51},
|
||||
{"com",{CLASS_REG_WORD+(ARG_RD),},
|
||||
{CLASS_BIT+8,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,52},
|
||||
{"comb",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,53},
|
||||
{"comb",{CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},1,2,54},
|
||||
{"comb",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,55},
|
||||
{"comb",{CLASS_REG_BYTE+(ARG_RD),},
|
||||
{CLASS_BIT+8,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,56},
|
||||
{"comflg",{CLASS_FLAGS,},
|
||||
{CLASS_BIT+8,CLASS_BIT+13,CLASS_IMM+(ARG_IMM4),CLASS_BIT+5,0,0,0,0,0,},1,2,57},
|
||||
{"cp",{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,58},
|
||||
{"cp",{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,59},
|
||||
{"cp",{CLASS_DA,CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,60},
|
||||
{"cp",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,61},
|
||||
{"cp",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,62},
|
||||
{"cp",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,63},
|
||||
{"cp",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+0,CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,64},
|
||||
{"cp",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+11,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,65},
|
||||
{"cpb",{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,66},
|
||||
{"cpb",{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,67},
|
||||
{"cpb",{CLASS_DA,CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,68},
|
||||
{"cpb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,69},
|
||||
{"cpb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,70},
|
||||
{"cpb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,71},
|
||||
{"cpb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+0,CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,72},
|
||||
{"cpb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+10,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,73},
|
||||
{"cpd",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,74},
|
||||
{"cpdb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,75},
|
||||
{"cpdr",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+12,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,76},
|
||||
{"cpdrb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+12,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,77},
|
||||
{"cpi",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,78},
|
||||
{"cpib",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,79},
|
||||
{"cpir",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,80},
|
||||
{"cpirb",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,81},
|
||||
{"cpl",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,82},
|
||||
{"cpl",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,83},
|
||||
{"cpl",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,84},
|
||||
{"cpl",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),},
|
||||
{CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,85},
|
||||
{"cpl",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,86},
|
||||
{"cpsd",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,87},
|
||||
{"cpsdb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,88},
|
||||
{"cpsdr",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+14,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,89},
|
||||
{"cpsdrb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+14,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,90},
|
||||
{"cpsi",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,91},
|
||||
{"cpsib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,92},
|
||||
{"cpsir",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,93},
|
||||
{"cpsirb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,},
|
||||
{CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,94},
|
||||
{"dab",{CLASS_REG_BYTE+(ARG_RD),},
|
||||
{CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,95},
|
||||
{"dbjnz",{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,},
|
||||
{CLASS_BIT+15,CLASS_REG+(ARG_RD),CLASS_1DISP7,0,0,0,0,0,0,},2,2,96},
|
||||
{"dec",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+2,CLASS_BIT+11,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,97},
|
||||
{"dec",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+11,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,98},
|
||||
{"dec",{CLASS_DA,CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+11,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,99},
|
||||
{"dec",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+10,CLASS_BIT+11,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,100},
|
||||
{"decb",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+2,CLASS_BIT+10,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,101},
|
||||
{"decb",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+10,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,102},
|
||||
{"decb",{CLASS_DA,CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+10,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,103},
|
||||
{"decb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+10,CLASS_BIT+10,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,104},
|
||||
{"di",{CLASS_IMM+(ARG_IMM2),},
|
||||
{CLASS_BIT+7,CLASS_BIT+12,CLASS_BIT+0,CLASS_00II,0,0,0,0,0,},1,2,105},
|
||||
{"div",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,106},
|
||||
{"div",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,107},
|
||||
{"div",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,108},
|
||||
{"div",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+1,CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,109},
|
||||
{"div",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+11,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,110},
|
||||
{"divl",{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,111},
|
||||
{"divl",{CLASS_REG_QUAD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,112},
|
||||
{"divl",{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,113},
|
||||
{"divl",{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),},
|
||||
{CLASS_BIT+1,CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,114},
|
||||
{"divl",{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+10,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,115},
|
||||
{"djnz",{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,},
|
||||
{CLASS_BIT+15,CLASS_REG+(ARG_RD),CLASS_0DISP7,0,0,0,0,0,0,},2,2,116},
|
||||
{"ei",{CLASS_IMM+(ARG_IMM2),},
|
||||
{CLASS_BIT+7,CLASS_BIT+12,CLASS_BIT+0,CLASS_01II,0,0,0,0,0,},1,2,117},
|
||||
{"ex",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+10,CLASS_BIT+13,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,118},
|
||||
{"ex",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+13,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,119},
|
||||
{"ex",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+6,CLASS_BIT+13,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,120},
|
||||
{"ex",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+6,CLASS_BIT+13,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,121},
|
||||
{"exb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,122},
|
||||
{"exb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+6,CLASS_BIT+12,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,123},
|
||||
{"exb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+6,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,124},
|
||||
{"exb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+10,CLASS_BIT+12,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,125},
|
||||
{"exts",{CLASS_REG_LONG+(ARG_RD),},
|
||||
{CLASS_BIT+11,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+10,0,0,0,0,0,},1,2,126},
|
||||
{"extsb",{CLASS_REG_WORD+(ARG_RD),},
|
||||
{CLASS_BIT+11,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,127},
|
||||
{"extsl",{CLASS_REG_QUAD+(ARG_RD),},
|
||||
{CLASS_BIT+11,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+7,0,0,0,0,0,},1,2,128},
|
||||
{"halt",{0},
|
||||
{CLASS_BIT+7,CLASS_BIT+10,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,129},
|
||||
{"in",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+13,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,130},
|
||||
{"in",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+3,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,131},
|
||||
{"inb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,132},
|
||||
{"inb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,133},
|
||||
{"inc",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+2,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,134},
|
||||
{"inc",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,135},
|
||||
{"inc",{CLASS_DA,CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+9,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,136},
|
||||
{"inc",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+10,CLASS_BIT+9,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,137},
|
||||
{"incb",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+2,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,138},
|
||||
{"incb",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,139},
|
||||
{"incb",{CLASS_DA,CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+8,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,140},
|
||||
{"incb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+10,CLASS_BIT+8,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,141},
|
||||
{"ind",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,142},
|
||||
{"indb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,143},
|
||||
{"inib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,144},
|
||||
{"inibr",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,145},
|
||||
{"iret",{0},
|
||||
{CLASS_BIT+7,CLASS_BIT+11,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,146},
|
||||
{"jp",{CLASS_CC,CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+1,CLASS_BIT+14,CLASS_REGN0+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,147},
|
||||
{"jp",{CLASS_CC,CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+14,CLASS_BIT+0,CLASS_CC,CLASS_ADDRESS,0,0,0,0,},2,4,148},
|
||||
{"jp",{CLASS_CC,CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+5,CLASS_BIT+14,CLASS_REGN0+(ARG_RD),CLASS_CC,CLASS_ADDRESS,0,0,0,0,},2,4,149},
|
||||
{"jr",{CLASS_CC,CLASS_DISP,},
|
||||
{CLASS_BIT+14,CLASS_CC,CLASS_DISP8,0,0,0,0,0,0,},2,2,150},
|
||||
{"ld",{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,151},
|
||||
{"ld",{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+15,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,152},
|
||||
{"ld",{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,153},
|
||||
{"ld",{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+6,CLASS_BIT+15,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,154},
|
||||
{"ld",{CLASS_DA,CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,155},
|
||||
{"ld",{CLASS_DA,CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+6,CLASS_BIT+15,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,156},
|
||||
{"ld",{CLASS_BA+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,157},
|
||||
{"ld",{CLASS_BX+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+7,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,158},
|
||||
{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,159},
|
||||
{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+6,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,160},
|
||||
{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+6,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,161},
|
||||
{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+2,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,162},
|
||||
{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+10,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,163},
|
||||
{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_BA+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,164},
|
||||
{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_BX+(ARG_RS),},
|
||||
{CLASS_BIT+7,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,165},
|
||||
{"lda",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+7,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,166},
|
||||
{"lda",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+7,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,167},
|
||||
{"lda",{CLASS_REG_WORD+(ARG_RD),CLASS_BA+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,168},
|
||||
{"lda",{CLASS_REG_WORD+(ARG_RD),CLASS_BX+(ARG_RS),},
|
||||
{CLASS_BIT+7,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,169},
|
||||
{"ldar",{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,},
|
||||
{CLASS_BIT+3,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,170},
|
||||
{"ldb",{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,171},
|
||||
{"ldb",{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+14,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,172},
|
||||
{"ldb",{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,173},
|
||||
{"ldb",{CLASS_X+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+14,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,174},
|
||||
{"ldb",{CLASS_DA,CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,175},
|
||||
{"ldb",{CLASS_DA,CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+6,CLASS_BIT+14,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,176},
|
||||
{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,177},
|
||||
{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,178},
|
||||
{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+6,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,179},
|
||||
{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},2,2,180},
|
||||
{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+2,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,181},
|
||||
{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,181},
|
||||
{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_BA+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,182},
|
||||
{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_BX+(ARG_RS),},
|
||||
{CLASS_BIT+7,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,183},
|
||||
{"ldb",{CLASS_BA+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,184},
|
||||
{"ldb",{CLASS_BX+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+7,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,185},
|
||||
{"ldctl",{CLASS_CTRL,CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+7,CLASS_BIT+13,CLASS_REG+(ARG_RS),CLASS_1CCC,0,0,0,0,0,},2,2,186},
|
||||
{"ldctl",{CLASS_REG_WORD+(ARG_RD),CLASS_CTRL,},
|
||||
{CLASS_BIT+7,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_0CCC,0,0,0,0,0,},2,2,187},
|
||||
{"ldir",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),},
|
||||
{CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,188},
|
||||
{"ldirb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),},
|
||||
{CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,189},
|
||||
{"ldk",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+11,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,190},
|
||||
{"ldl",{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,191},
|
||||
{"ldl",{CLASS_X+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,192},
|
||||
{"ldl",{CLASS_DA,CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+13,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,193},
|
||||
{"ldl",{CLASS_BA+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,194},
|
||||
{"ldl",{CLASS_BX+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+7,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,195},
|
||||
{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,196},
|
||||
{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,197},
|
||||
{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,198},
|
||||
{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),},
|
||||
{CLASS_BIT+1,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,199},
|
||||
{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,200},
|
||||
{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_BA+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,201},
|
||||
{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_BX+(ARG_RS),},
|
||||
{CLASS_BIT+7,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,202},
|
||||
{"ldm",{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),},
|
||||
{CLASS_BIT+1,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),0,},3,4,203},
|
||||
{"ldm",{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),},
|
||||
{CLASS_BIT+5,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS,},3,6,204},
|
||||
{"ldm",{CLASS_DA,CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),},
|
||||
{CLASS_BIT+5,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS,},3,6,205},
|
||||
{"ldm",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_IMM + (ARG_IMMN),},
|
||||
{CLASS_BIT+1,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),0,},3,4,206},
|
||||
{"ldm",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),CLASS_IMM + (ARG_IMMN),},
|
||||
{CLASS_BIT+5,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS,},3,6,207},
|
||||
{"ldm",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,CLASS_IMM + (ARG_IMMN),},
|
||||
{CLASS_BIT+5,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS,},3,6,208},
|
||||
{"ldps",{CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,0,0,0,0,},1,2,209},
|
||||
{"ldps",{CLASS_DA,},
|
||||
{CLASS_BIT+7,CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},1,4,210},
|
||||
{"ldps",{CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+7,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},1,4,211},
|
||||
{"ldr",{CLASS_DISP,CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,212},
|
||||
{"ldr",{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,},
|
||||
{CLASS_BIT+3,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,213},
|
||||
{"ldrb",{CLASS_DISP,CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,214},
|
||||
{"ldrb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,},
|
||||
{CLASS_BIT+3,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,215},
|
||||
{"ldrl",{CLASS_DISP,CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,216},
|
||||
{"ldrl",{CLASS_REG_LONG+(ARG_RD),CLASS_DISP,},
|
||||
{CLASS_BIT+3,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,217},
|
||||
{"mbit",{0},
|
||||
{CLASS_BIT+7,CLASS_BIT+11,CLASS_BIT+0,CLASS_BIT+10,0,0,0,0,0,},0,2,218},
|
||||
{"mreq",{CLASS_REG_WORD+(ARG_RD),},
|
||||
{CLASS_BIT+7,CLASS_BIT+11,CLASS_REG+(ARG_RD),CLASS_BIT+13,0,0,0,0,0,},1,2,219},
|
||||
{"mres",{0},
|
||||
{CLASS_BIT+7,CLASS_BIT+11,CLASS_BIT+0,CLASS_BIT+9,0,0,0,0,0,},0,2,220},
|
||||
{"mset",{0},
|
||||
{CLASS_BIT+7,CLASS_BIT+11,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},0,2,221},
|
||||
{"mult",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,222},
|
||||
{"mult",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,223},
|
||||
{"mult",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,224},
|
||||
{"mult",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+1,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,225},
|
||||
{"mult",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,226},
|
||||
{"multl",{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,227},
|
||||
{"multl",{CLASS_REG_QUAD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,228},
|
||||
{"multl",{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,229},
|
||||
{"multl",{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),},
|
||||
{CLASS_BIT+1,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,230},
|
||||
{"multl",{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,231},
|
||||
{"neg",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,232},
|
||||
{"neg",{CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+2,0,0,0,0,0,},1,2,233},
|
||||
{"neg",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,234},
|
||||
{"neg",{CLASS_REG_WORD+(ARG_RD),},
|
||||
{CLASS_BIT+8,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,235},
|
||||
{"negb",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,236},
|
||||
{"negb",{CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+2,0,0,0,0,0,},1,2,237},
|
||||
{"negb",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,238},
|
||||
{"negb",{CLASS_REG_WORD+(ARG_RD),},
|
||||
{CLASS_BIT+8,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,239},
|
||||
{"nop",{0},
|
||||
{CLASS_BIT+8,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+7,0,0,0,0,0,},0,2,240},
|
||||
{"or",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,241},
|
||||
{"or",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,242},
|
||||
{"or",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,243},
|
||||
{"or",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+0,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,244},
|
||||
{"or",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,245},
|
||||
{"orb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,246},
|
||||
{"orb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,247},
|
||||
{"orb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,248},
|
||||
{"orb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+0,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,249},
|
||||
{"orb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,250},
|
||||
{"out",{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+15,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,251},
|
||||
{"out",{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+11,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,252},
|
||||
{"outb",{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+14,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,253},
|
||||
{"outb",{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+10,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,254},
|
||||
{"outd",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,255},
|
||||
{"outdb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,256},
|
||||
{"outib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,257},
|
||||
{"outibr",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,258},
|
||||
{"pop",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,259},
|
||||
{"pop",{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,260},
|
||||
{"pop",{CLASS_DA,CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},2,4,261},
|
||||
{"pop",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,262},
|
||||
{"popl",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,263},
|
||||
{"popl",{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,264},
|
||||
{"popl",{CLASS_DA,CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},2,4,265},
|
||||
{"popl",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,266},
|
||||
{"push",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,267},
|
||||
{"push",{CLASS_IR+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},2,4,268},
|
||||
{"push",{CLASS_IR+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},2,4,269},
|
||||
{"push",{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,269},
|
||||
{"push",{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,270},
|
||||
{"push",{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,271},
|
||||
{"pushl",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,272},
|
||||
{"pushl",{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,273},
|
||||
{"pushl",{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,274},
|
||||
{"res",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+2,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,275},
|
||||
{"res",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,276},
|
||||
{"res",{CLASS_DA,CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+3,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,277},
|
||||
{"res",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+10,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,278},
|
||||
{"res",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,279},
|
||||
{"resb",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+2,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,280},
|
||||
{"resb",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,281},
|
||||
{"resb",{CLASS_DA,CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+2,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,282},
|
||||
{"resb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+10,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,283},
|
||||
{"resb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,284},
|
||||
{"resflg",{CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+8,CLASS_BIT+13,CLASS_IMM+(ARG_IMM4),CLASS_BIT+3,0,0,0,0,0,},1,2,285},
|
||||
{"ret",{CLASS_CC,},
|
||||
{CLASS_BIT+9,CLASS_BIT+14,CLASS_BIT+0,CLASS_CC,0,0,0,0,0,},1,2,286},
|
||||
{"rl",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_1),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},2,2,287},
|
||||
{"rl",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_2),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},2,2,288},
|
||||
{"rlb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_1),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},2,2,289},
|
||||
{"rlb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_2),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},2,2,290},
|
||||
{"rlc",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_1),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},2,2,291},
|
||||
{"rlc",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_2),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+10,0,0,0,0,0,},2,2,292},
|
||||
{"rlcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_1),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},2,2,293},
|
||||
{"rlcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_2),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+10,0,0,0,0,0,},2,2,294},
|
||||
{"rldb",{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),},
|
||||
{CLASS_BIT+11,CLASS_BIT+14,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,295},
|
||||
{"rr",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_1),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},2,2,296},
|
||||
{"rr",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_2),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},2,2,297},
|
||||
{"rrb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_1),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},2,2,298},
|
||||
{"rrb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_2),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},2,2,299},
|
||||
{"rrc",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_1),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+12,0,0,0,0,0,},2,2,300},
|
||||
{"rrc",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_2),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+14,0,0,0,0,0,},2,2,301},
|
||||
{"rrcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_1),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+12,0,0,0,0,0,},2,2,302},
|
||||
{"rrcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_2),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+14,0,0,0,0,0,},2,2,303},
|
||||
{"rrdb",{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),},
|
||||
{CLASS_BIT+11,CLASS_BIT+12,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,304},
|
||||
{"sbc",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+11,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,305},
|
||||
{"sbcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+11,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,306},
|
||||
{"sda",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,307},
|
||||
{"sdab",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,308},
|
||||
{"sdal",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+15,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,309},
|
||||
{"sdl",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,310},
|
||||
{"sdlb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,311},
|
||||
{"sdll",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,312},
|
||||
{"set",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+2,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,313},
|
||||
{"set",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,314},
|
||||
{"set",{CLASS_DA,CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+5,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,315},
|
||||
{"set",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+10,CLASS_BIT+5,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,316},
|
||||
{"set",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,317},
|
||||
{"setb",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+2,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,318},
|
||||
{"setb",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,319},
|
||||
{"setb",{CLASS_DA,CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+6,CLASS_BIT+4,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,320},
|
||||
{"setb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+10,CLASS_BIT+4,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,321},
|
||||
{"setb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+2,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,322},
|
||||
{"setflg",{CLASS_IMM +(ARG_IMM4),},
|
||||
{CLASS_BIT+8,CLASS_BIT+13,CLASS_IMM+(ARG_IMM4),CLASS_BIT+1,0,0,0,0,0,},1,2,323},
|
||||
{"sinb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,324},
|
||||
{"sinb",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+3,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,325},
|
||||
{"sind",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,326},
|
||||
{"sindb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,327},
|
||||
{"sinib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,328},
|
||||
{"sinibr",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,329},
|
||||
{"sla",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,330},
|
||||
{"slab",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,331},
|
||||
{"slal",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+13,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,332},
|
||||
{"sll",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,333},
|
||||
{"sllb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,334},
|
||||
{"slll",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,335},
|
||||
{"sout",{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+11,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,336},
|
||||
{"soutb",{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+3,CLASS_BIT+10,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,337},
|
||||
{"soutd",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,338},
|
||||
{"soutdb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,339},
|
||||
{"soutib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,340},
|
||||
{"soutibr",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
|
||||
{CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,341},
|
||||
{"sra",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,342},
|
||||
{"srab",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,343},
|
||||
{"sral",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+13,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,344},
|
||||
{"srl",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,345},
|
||||
{"srlb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,346},
|
||||
{"srll",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,347},
|
||||
{"sub",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,348},
|
||||
{"sub",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,349},
|
||||
{"sub",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,350},
|
||||
{"sub",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+0,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,351},
|
||||
{"sub",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+3,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,352},
|
||||
{"subb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,353},
|
||||
{"subb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,354},
|
||||
{"subb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,355},
|
||||
{"subb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+0,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,356},
|
||||
{"subb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,357},
|
||||
{"subl",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+1,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,358},
|
||||
{"subl",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,359},
|
||||
{"subl",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+5,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,360},
|
||||
{"subl",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),},
|
||||
{CLASS_BIT+1,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,361},
|
||||
{"subl",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),},
|
||||
{CLASS_BIT+9,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,362},
|
||||
{"tcc",{CLASS_CC,CLASS_REG_WORD+(ARG_RD),},
|
||||
{CLASS_BIT+10,CLASS_BIT+15,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,363},
|
||||
{"tccb",{CLASS_CC,CLASS_REG_BYTE+(ARG_RD),},
|
||||
{CLASS_BIT+10,CLASS_BIT+14,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,364},
|
||||
{"test",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,365},
|
||||
{"test",{CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+4,0,0,0,0,0,},1,2,366},
|
||||
{"test",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,367},
|
||||
{"test",{CLASS_REG_WORD+(ARG_RD),},
|
||||
{CLASS_BIT+8,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,368},
|
||||
{"testb",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,369},
|
||||
{"testb",{CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+4,0,0,0,0,0,},1,2,370},
|
||||
{"testb",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,371},
|
||||
{"testb",{CLASS_REG_BYTE+(ARG_RD),},
|
||||
{CLASS_BIT+8,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,372},
|
||||
{"testl",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+1,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,373},
|
||||
{"testl",{CLASS_DA,},
|
||||
{CLASS_BIT+5,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},1,2,374},
|
||||
{"testl",{CLASS_REG_LONG+(ARG_RD),},
|
||||
{CLASS_BIT+9,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,375},
|
||||
{"trdb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),},
|
||||
{CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,376},
|
||||
{"trdrb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),},
|
||||
{CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+12,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,377},
|
||||
{"trib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),},
|
||||
{CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,378},
|
||||
{"trirb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),},
|
||||
{CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,379},
|
||||
{"trtdrb",{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),},
|
||||
{CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+14,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+14,0,},3,4,380},
|
||||
{"trtib",{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_WORD+(ARG_RR),},
|
||||
{CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,381},
|
||||
{"trtirb",{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),},
|
||||
{CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+14,0,},3,4,382},
|
||||
{"trtrb",{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),},
|
||||
{CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,383},
|
||||
{"tset",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,384},
|
||||
{"tset",{CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+6,0,0,0,0,0,},1,2,385},
|
||||
{"tset",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,386},
|
||||
{"tset",{CLASS_REG_WORD+(ARG_RD),},
|
||||
{CLASS_BIT+8,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,387},
|
||||
{"tsetb",{CLASS_IR+(ARG_RD),},
|
||||
{CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,388},
|
||||
{"tsetb",{CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+6,0,0,0,0,0,},1,2,389},
|
||||
{"tsetb",{CLASS_X+(ARG_RD),},
|
||||
{CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,390},
|
||||
{"tsetb",{CLASS_REG_BYTE+(ARG_RD),},
|
||||
{CLASS_BIT+8,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,391},
|
||||
{"xor",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,392},
|
||||
{"xor",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,393},
|
||||
{"xor",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,394},
|
||||
{"xor",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),},
|
||||
{CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,395},
|
||||
{"xor",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,396},
|
||||
{"xorb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),},
|
||||
{CLASS_BIT+0,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,397},
|
||||
{"xorb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,},
|
||||
{CLASS_BIT+4,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,398},
|
||||
{"xorb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),},
|
||||
{CLASS_BIT+4,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,399},
|
||||
{"xorb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
|
||||
{CLASS_BIT+0,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,400},
|
||||
{"xorb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),},
|
||||
{CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,401},
|
||||
0,0};
|
||||
#endif
|
||||
879
opcodes/z8kgen.c
Normal file
879
opcodes/z8kgen.c
Normal file
@ -0,0 +1,879 @@
|
||||
#include <stdio.h>
|
||||
#define BYTE_INFO_LEN 10
|
||||
/*#include "z8opcode.h"*/
|
||||
struct op {
|
||||
char *bits;
|
||||
char *name;
|
||||
} ;
|
||||
#define iswhite(x) ((x) == ' ' || (x) == '\t')
|
||||
struct op opt[] =
|
||||
{
|
||||
"1011 0101 ssss dddd","adc rd,rs",
|
||||
"1011 0100 ssss dddd","adcb rbd,rbs",
|
||||
"0000 0001 ssN0 dddd","add rd,@rs",
|
||||
"0100 0001 0000 dddd address","add rd,address",
|
||||
"0100 0001 ssN0 dddd address","add rd,address(rs)",
|
||||
"0000 0001 0000 dddd imm16","add rd,imm16",
|
||||
"1000 0001 ssss dddd","add rd,rs",
|
||||
"0000 0000 ssN0 dddd","addb rbd,@rs",
|
||||
"0100 0000 0000 dddd address","addb rbd,address",
|
||||
"0100 0000 ssN0 dddd address","addb rbd,address(rs)",
|
||||
"0000 0000 0000 dddd imm8 imm8","addb rbd,imm8",
|
||||
"1000 0000 ssss dddd","addb rbd,rbs",
|
||||
"0001 0110 ssN0 dddd","addl rrd,@rs",
|
||||
"0101 0110 0000 dddd address","addl rrd,address",
|
||||
"0101 0110 ssN0 dddd address","addl rrd,address(rs)",
|
||||
"0001 0110 0000 dddd imm32","addl rrd,imm32",
|
||||
"1001 0110 ssss dddd","addl rrd,rrs",
|
||||
"0000 0111 ssN0 dddd","and rd,@rs",
|
||||
"0100 0111 0000 dddd address","and rd,address",
|
||||
"0100 0111 ssN0 dddd address","and rd,address(rs)",
|
||||
"0000 0111 0000 dddd imm16","and rd,imm16",
|
||||
"1000 0111 ssss dddd","and rd,rs",
|
||||
"0000 0110 ssN0 dddd","andb rbd,@rs",
|
||||
"0100 0110 0000 dddd address","andb rbd,address",
|
||||
"0100 0110 ssN0 dddd address","andb rbd,address(rs)",
|
||||
"0000 0110 0000 dddd imm8 imm8","andb rbd,imm8",
|
||||
"1000 0110 ssss dddd","andb rbd,rbs",
|
||||
"0010 0111 ddN0 imm4","bit @rd,imm4",
|
||||
"0110 0111 ddN0 imm4 address","bit address(rd),imm4",
|
||||
"0110 0111 0000 imm4 address","bit address,imm4",
|
||||
"1010 0111 dddd imm4","bit rd,imm4",
|
||||
"0010 0111 0000 ssss 0000 dddd 0000 0000","bit rd,rs",
|
||||
"0010 0110 ddN0 imm4","bitb @rd,imm4",
|
||||
"0110 0110 ddN0 imm4 address","bitb address(rd),imm4",
|
||||
"0110 0110 0000 imm4 address","bitb address,imm4",
|
||||
"1010 0110 dddd imm4","bitb rbd,imm4",
|
||||
"0010 0110 0000 ssss 0000 dddd 0000 0000","bitb rbd,rs",
|
||||
"0001 1111 ddN0 0000","call @rd",
|
||||
"0101 1111 0000 0000 address","call address",
|
||||
"0101 1111 ddN0 0000 address","call address(rd)",
|
||||
"1101 disp12","calr disp12",
|
||||
"0000 1101 ddN0 1000","clr @rd",
|
||||
"0100 1101 0000 1000","clr address",
|
||||
"0100 1101 ddN0 1000","clr address(rd)",
|
||||
"1000 1101 dddd 1000","clr rd",
|
||||
"0000 1100 ddN0 1000","clrb @rd",
|
||||
"0100 1100 0000 1000","clrb address",
|
||||
"0100 1100 ddN0 1000","clrb address(rd)",
|
||||
"1000 1100 dddd 1000","clrb rbd",
|
||||
"1011 1011 ssN0 1010 0000 rrrr ddN0 cccc","cpsd @rd,@rs,rr,cc",
|
||||
"1011 1010 ssN0 1010 0000 rrrr ddN0 cccc","cpsdb @rd,@rs,rr,cc",
|
||||
"1011 1011 ssN0 1110 0000 rrrr ddN0 cccc","cpsdr @rd,@rs,rr,cc",
|
||||
"1011 1010 ssN0 1110 0000 rrrr ddN0 cccc","cpsdrb @rd,@rs,rr,cc",
|
||||
"1011 1011 ssN0 0010 0000 rrrr ddN0 cccc","cpsi @rd,@rs,rr,cc",
|
||||
"1011 1010 ssN0 0010 0000 rrrr ddN0 cccc","cpsib @rd,@rs,rr,cc",
|
||||
"1011 1011 ssN0 0110 0000 rrrr ddN0 cccc","cpsir @rd,@rs,rr,cc",
|
||||
"1011 1010 ssN0 0110 0000 rrrr ddN0 cccc","cpsirb @rd,@rs,rr,cc",
|
||||
"0000 1101 ddN0 0000","com @rd",
|
||||
"0100 1101 0000 0000","com address",
|
||||
"0100 1101 ddN0 0000","com address(rd)",
|
||||
"1000 1101 dddd 0000","com rd",
|
||||
"0000 1100 ddN0 0000","comb @rd",
|
||||
"0100 1100 0000 0000","comb address",
|
||||
"0100 1100 ddN0 0000","comb address(rd)",
|
||||
"1000 1100 dddd 0000","comb rbd",
|
||||
"1000 1101 imm4 0101","comflg flags",
|
||||
"0000 1101 ddN0 0001 imm16","cp @rd,imm16",
|
||||
"0100 1101 ddN0 0001 address imm16","cp address(rd),imm16",
|
||||
"0100 1101 0000 0001 address imm16","cp address,imm16",
|
||||
"0000 1011 ssN0 dddd","cp rd,@rs",
|
||||
"0100 1011 0000 dddd address","cp rd,address",
|
||||
"0100 1011 ssN0 dddd address","cp rd,address(rs)",
|
||||
"0000 1011 0000 dddd imm16","cp rd,imm16",
|
||||
"1000 1011 ssss dddd","cp rd,rs",
|
||||
"0000 1100 ddN0 0001 imm8 imm8","cpb @rd,imm8",
|
||||
"0100 1100 ddN0 0001 address imm8 imm8","cpb address(rd),imm8",
|
||||
"0100 1100 0000 0001 address imm8 imm8","cpb address,imm8",
|
||||
"0000 1010 ssN0 dddd","cpb rbd,@rs",
|
||||
"0100 1010 0000 dddd address","cpb rbd,address",
|
||||
"0100 1010 ssN0 dddd address","cpb rbd,address(rs)",
|
||||
"0000 1010 0000 dddd imm8 imm8","cpb rbd,imm8",
|
||||
"1000 1010 ssss dddd","cpb rbd,rbs",
|
||||
"1011 1011 ssN0 1000 0000 rrrr dddd cccc","cpd rd,@rs,rr,cc",
|
||||
"1011 1010 ssN0 1000 0000 rrrr dddd cccc","cpdb rbd,@rs,rr,cc",
|
||||
"1011 1011 ssN0 1100 0000 rrrr dddd cccc","cpdr rd,@rs,rr,cc",
|
||||
"1011 1010 ssN0 1100 0000 rrrr dddd cccc","cpdrb rbd,@rs,rr,cc",
|
||||
"1011 1011 ssN0 0000 0000 rrrr dddd cccc","cpi rbd,@rs,rr,cc",
|
||||
"1011 1010 ssN0 0000 0000 rrrr dddd cccc","cpib rd,@rs,rr,cc",
|
||||
"1011 1011 ssN0 0100 0000 rrrr dddd cccc","cpir rbd,@rs,rr,cc",
|
||||
"1011 1010 ssN0 0100 0000 rrrr dddd cccc","cpirb rd,@rs,rr,cc",
|
||||
"0001 0000 ssN0 dddd","cpl rrd,@rs",
|
||||
"0101 0000 0000 dddd address","cpl rrd,address",
|
||||
"0101 0000 ssN0 dddd address","cpl rrd,address(rs)",
|
||||
"0001 0000 0000 dddd imm32","cpl rrd,imm32",
|
||||
"1001 0000 ssss dddd","cpl rrd,rrs",
|
||||
"1011 0000 dddd 0000","dab rbd",
|
||||
"1111 dddd 1disp7","dbjnz rbd,disp7",
|
||||
"0010 1011 ddN0 imm4","dec @rd,imm4",
|
||||
"0110 1011 ddN0 imm4 address","dec address(rd),imm4",
|
||||
"0110 1011 0000 imm4 address","dec address,imm4",
|
||||
"1010 1011 dddd imm4","dec rd,imm4",
|
||||
"0010 1010 ddN0 imm4","decb @rd,imm4",
|
||||
"0110 1010 ddN0 imm4 address","decb address(rd),imm4",
|
||||
"0110 1010 0000 imm4 address","decb address,imm4",
|
||||
"1010 1010 dddd imm4","decb rbd,imm4",
|
||||
"0111 1100 0000 00ii","di i2",
|
||||
"0001 1011 ssN0 dddd","div rrd,@rs",
|
||||
"0101 1011 0000 dddd address","div rrd,address",
|
||||
"0101 1011 ssN0 dddd address","div rrd,address(rs)",
|
||||
"0001 1011 0000 dddd imm16","div rrd,imm16",
|
||||
"1001 1011 ssss dddd","div rrd,rs",
|
||||
"0001 1010 ssN0 dddd","divl rqd,@rs",
|
||||
"0101 1010 0000 dddd address","divl rqd,address",
|
||||
"0101 1010 ssN0 dddd address","divl rqd,address(rs)",
|
||||
"0001 1010 0000 dddd imm32","divl rqd,imm32",
|
||||
"1001 1010 ssss dddd","divl rqd,rrs",
|
||||
"1111 dddd 0disp7","djnz rd,disp7",
|
||||
"0111 1100 0000 01ii","ei i2",
|
||||
"1010 1101 ssss dddd","ex rbd,rbs",
|
||||
"0010 1101 ssN0 dddd","ex rd,@rs",
|
||||
"0110 1101 0000 dddd address","ex rd,address",
|
||||
"0110 1101 ssN0 dddd address","ex rd,address(rs)",
|
||||
"0010 1100 ssN0 dddd","exb rbd,@rs",
|
||||
"0110 1100 0000 dddd address","exb rbd,address",
|
||||
"0110 1100 ssN0 dddd address","exb rbd,address(rs)",
|
||||
"1010 1100 ssss dddd","exb rbd,rbs",
|
||||
"1011 0001 dddd 1010","exts rrd",
|
||||
"1011 0001 dddd 0000","extsb rd",
|
||||
"1011 0001 dddd 0111","extsl rqd",
|
||||
"0111 1010 0000 0000","halt",
|
||||
"0011 1101 ssN0 dddd","in rd,@rs",
|
||||
"0011 1101 dddd 0100 imm16","in rd,imm16",
|
||||
"0011 1100 ssN0 dddd","inb rbd,@rs",
|
||||
"0011 1100 dddd 0100 imm16","inb rbd,imm16",
|
||||
"0010 1001 ddN0 imm4","inc @rd,imm4",
|
||||
"0110 1001 ddN0 imm4 address","inc address(rd),imm4",
|
||||
"0110 1001 0000 imm4 address","inc address,imm4",
|
||||
"1010 1001 dddd imm4","inc rd,imm4",
|
||||
"0010 1000 ddN0 imm4","incb @rd,imm4",
|
||||
"0110 1000 ddN0 imm4 address","incb address(rd),imm4",
|
||||
"0110 1000 0000 imm4 address","incb address,imm4",
|
||||
"1010 1000 dddd imm4","incb rbd,imm4",
|
||||
"0011 1011 ssN0 1000 0000 aaaa ddN0 1000","ind @rd,@rs,ra",
|
||||
"0011 1010 ssN0 1000 0000 aaaa ddN0 1000","indb @rd,@rs,rba",
|
||||
"0011 1100 ssN0 0000 0000 aaaa ddN0 1000","inib @rd,@rs,ra",
|
||||
"0011 1100 ssN0 0000 0000 aaaa ddN0 0000","inibr @rd,@rs,ra",
|
||||
"0111 1011 0000 0000","iret",
|
||||
"0001 1110 ddN0 cccc","jp cc,@rd",
|
||||
"0101 1110 0000 cccc address","jp cc,address",
|
||||
"0101 1110 ddN0 cccc address","jp cc,address(rd)",
|
||||
"1110 cccc disp8","jr cc,disp8",
|
||||
"0000 1101 ddN0 0101 imm16","ld @rd,imm16",
|
||||
"0010 1111 ddN0 ssss","ld @rd,rs",
|
||||
"0100 1101 ddN0 0101 address imm16","ld address(rd),imm16",
|
||||
"0110 1111 ddN0 ssss address","ld address(rd),rs",
|
||||
"0100 1101 0000 0101 address imm16","ld address,imm16",
|
||||
"0110 1111 0000 ssss address","ld address,rs",
|
||||
"0011 0011 ddN0 ssss disp16","ld rd(disp16),rs",
|
||||
"0111 0011 ddN0 ssss 0000 xxN0 0000 0000","ld rd(rx),rs",
|
||||
"0010 0001 ssN0 dddd","ld rd,@rs",
|
||||
"0110 0001 0000 dddd address","ld rd,address",
|
||||
"0110 0001 ssN0 dddd address","ld rd,address(rs)",
|
||||
"0010 0001 0000 dddd imm16","ld rd,imm16",
|
||||
"1010 0001 ssss dddd","ld rd,rs",
|
||||
"0011 0001 ssN0 dddd disp16","ld rd,rs(disp16)",
|
||||
"0111 0001 ssN0 dddd 0000 xxN0 0000 0000","ld rd,rs(rx)",
|
||||
"0111 0110 0000 dddd address","lda rd,address",
|
||||
"0111 0110 ssN0 dddd address","lda rd,address(rs)",
|
||||
"0011 0100 ssN0 dddd disp16","lda rd,rs(disp16)",
|
||||
"0111 0100 ssN0 dddd 0000 xxN0 0000 0000","lda rd,rs(rx)",
|
||||
"0011 0100 0000 dddd disp16","ldar rd,disp16",
|
||||
"0000 1100 ddN0 0101 imm8 imm8","ldb @rd,imm8",
|
||||
"0010 1110 ddN0 ssss","ldb @rd,rbs",
|
||||
"0100 1100 ddN0 0101 address imm8 imm8","ldb address(rd),imm8",
|
||||
"0100 1110 ddN0 ssss address","ldb address(rd),rbs",
|
||||
"0100 1100 0000 0101 address imm8 imm8","ldb address,imm8",
|
||||
"0110 1110 0000 ssss address","ldb address,rbs",
|
||||
"0010 0000 ssN0 dddd","ldb rbd,@rs",
|
||||
"0110 0000 0000 dddd address","ldb rbd,address",
|
||||
"0110 0000 ssN0 dddd address","ldb rbd,address(rs)",
|
||||
"1100 dddd imm8","ldb rbd,imm8",
|
||||
"0010 0000 0000 dddd imm8 imm8","ldb rbd,imm8",
|
||||
"1010 0000 ssss dddd","ldb rbd,rbs",
|
||||
"0011 0000 ssN0 dddd disp16","ldb rbd,rs(disp16)",
|
||||
"0111 0000 ssN0 dddd 0000 xxN0 0000 0000","ldb rbd,rs(rx)",
|
||||
"0011 0010 ddN0 ssss disp16","ldb rd(disp16),rbs",
|
||||
"0111 0010 ddN0 ssss 0000 xxN0 0000 0000","ldb rd(rx),rbs",
|
||||
"0111 1101 ssss 1ccc","ldctl ctrl,rs",
|
||||
"0111 1101 dddd 0ccc","ldctl rd,ctrl",
|
||||
"0001 1101 ddN0 ssss","ldl @rd,rrs",
|
||||
"0101 1101 ddN0 ssss address","ldl address(rd),rrs",
|
||||
"0101 1101 0000 ssss address","ldl address,rrs",
|
||||
"0011 0111 ddN0 ssss disp16","ldl rd(disp16),rrs",
|
||||
"0111 0111 ddN0 ssss 0000 xxN0 0000 0000","ldl rd(rx),rrs",
|
||||
"0001 0100 ssN0 dddd","ldl rrd,@rs",
|
||||
"0101 0100 0000 dddd address","ldl rrd,address",
|
||||
"0101 0100 ssN0 dddd address","ldl rrd,address(rs)",
|
||||
"0001 0100 0000 dddd imm32","ldl rrd,imm32",
|
||||
"1001 0100 ssss dddd","ldl rrd,rrs",
|
||||
"0011 0101 ssN0 dddd disp16","ldl rrd,rs(disp16)",
|
||||
"0111 0101 ssN0 dddd 0000 xxN0 0000 0000","ldl rrd,rs(rx)",
|
||||
"0001 1100 ddN0 1001 0000 ssss 0000 nminus1","ldm @rd,rs,n",
|
||||
"0101 1100 ddN0 1001 0000 ssN0 0000 nminus1 address","ldm address(rd),rs,n",
|
||||
"0101 1100 0000 1001 0000 ssss 0000 nminus1 address","ldm address,rs,n",
|
||||
"0001 1100 ssN0 0001 0000 dddd 0000 nminus1","ldm rd,@rs,n",
|
||||
"0101 1100 ssN0 0001 0000 dddd 0000 nminus1 address","ldm rd,address(rs),n",
|
||||
"0101 1100 0000 0001 0000 dddd 0000 nminus1 address","ldm rd,address,n",
|
||||
"0011 1001 ssN0 0000","ldps @rs",
|
||||
"1011 1101 dddd imm4","ldk rd,imm4",
|
||||
"1011 1010 ssN0 0001 0000 rrrr ddN0 0000","ldirb @rd,@rs,rr",
|
||||
"1011 1011 ssN0 0001 0000 rrrr ddN0 0000","ldir @rd,@rs,rr",
|
||||
|
||||
"0111 1001 0000 0000 address","ldps address",
|
||||
"0111 1001 ssN0 0000 address","ldps address(rs)",
|
||||
"0011 0011 0000 ssss disp16","ldr disp16,rs",
|
||||
"0011 0001 0000 dddd disp16","ldr rd,disp16",
|
||||
"0011 0010 0000 ssss disp16","ldrb disp16,rbs",
|
||||
"0011 0000 0000 dddd disp16","ldrb rbd,disp16",
|
||||
"0011 0111 0000 ssss disp16","ldrl disp16,rrs",
|
||||
"0011 0101 0000 dddd disp16","ldrl rrd,disp16",
|
||||
"0111 1011 0000 1010","mbit",
|
||||
"0111 1011 dddd 1101","mreq rd",
|
||||
"0111 1011 0000 1001","mres",
|
||||
"0111 1011 0000 1000","mset",
|
||||
"0001 1001 ssN0 dddd","mult rrd,@rs",
|
||||
"0101 1001 0000 dddd address","mult rrd,address",
|
||||
"0101 1001 ssN0 dddd address","mult rrd,address(rs)",
|
||||
"0001 1001 0000 dddd imm16","mult rrd,imm16",
|
||||
"1001 1001 ssss dddd","mult rrd,rs",
|
||||
"0001 1000 ssN0 dddd","multl rqd,@rs",
|
||||
"0101 1000 0000 dddd address","multl rqd,address",
|
||||
"0101 1000 ssN0 dddd address","multl rqd,address(rs)",
|
||||
"0001 1000 0000 dddd imm32","multl rqd,imm32",
|
||||
"1001 1000 ssss dddd","multl rqd,rrs",
|
||||
"0000 1101 ddN0 0010","neg @rd",
|
||||
"0100 1101 0000 0010","neg address",
|
||||
"0100 1101 ddN0 0010","neg address(rd)",
|
||||
"1000 1101 dddd 0010","neg rd",
|
||||
"0000 1100 ddN0 0010","negb @rd",
|
||||
"0100 1100 0000 0010","negb address",
|
||||
"0100 1100 ddN0 0010","negb address(rd)",
|
||||
"1000 1100 dddd 0010","negb rd",
|
||||
"1000 1101 0000 0111","nop",
|
||||
"0000 0101 ssN0 dddd","or rd,@rs",
|
||||
"0100 0101 0000 dddd address","or rd,address",
|
||||
"0100 0101 ssN0 dddd address","or rd,address(rs)",
|
||||
"0000 0101 0000 dddd imm16","or rd,imm16",
|
||||
"1000 0101 ssss dddd","or rd,rs",
|
||||
"0000 0100 ssN0 dddd","orb rbd,@rs",
|
||||
"0100 0100 0000 dddd address","orb rbd,address",
|
||||
"0100 0100 ssN0 dddd address","orb rbd,address(rs)",
|
||||
"0000 0100 0000 dddd imm8 imm8","orb rbd,imm8",
|
||||
"1000 0100 ssss dddd","orb rbd,rbs",
|
||||
"0011 1111 ddN0 ssss","out @rd,rs",
|
||||
"0011 1011 ssss 0110 imm16","out imm16,rs",
|
||||
"0011 1110 ddN0 ssss","outb @rd,rbs",
|
||||
"0011 1010 ssss 0110 imm16","outb imm16,rbs",
|
||||
"0011 1011 ssN0 1010 0000 aaaa ddN0 1000","outd @rd,@rs,ra",
|
||||
"0011 1010 ssN0 1010 0000 aaaa ddN0 1000","outdb @rd,@rs,rba",
|
||||
"0011 1100 ssN0 0010 0000 aaaa ddN0 1000","outib @rd,@rs,ra",
|
||||
"0011 1100 ssN0 0010 0000 aaaa ddN0 0000","outibr @rd,@rs,ra",
|
||||
"0001 0111 ssN0 ddN0","pop @rd,@rs",
|
||||
"0101 0111 ssN0 ddN0 address","pop address(rd),@rs",
|
||||
"0101 0111 ssN0 0000 address","pop address,@rs",
|
||||
"1001 0111 ssN0 dddd","pop rd,@rs",
|
||||
"0001 0101 ssN0 ddN0","popl @rd,@rs",
|
||||
"0101 0101 ssN0 ddN0 address","popl address(rd),@rs",
|
||||
"0101 0101 ssN0 0000 address","popl address,@rs",
|
||||
"1001 0101 ssN0 dddd","popl rrd,@rs",
|
||||
"0001 0011 ddN0 ssN0","push @rd,@rs",
|
||||
"0101 0011 ddN0 0000 address","push @rd,address",
|
||||
"0000 1101 ddN0 1001 imm16","push @rd,imm16",
|
||||
"1001 0011 ddN0 ssss","push @rd,rs",
|
||||
"0101 0011 ddN0 ssN0 address","push @rd,address(rs)",
|
||||
"0001 0001 ddN0 ssN0","pushl @rd,@rs",
|
||||
"0101 0001 ddN0 0000 address","push @rd,address",
|
||||
"1001 0001 ddN0 ssss","pushl @rd,rrs",
|
||||
"0101 0001 ddN0 ssN0 address","pushl @rd,address(rs)",
|
||||
"0010 0011 ddN0 imm4","res @rd,imm4",
|
||||
"0110 0011 ddN0 imm4 address","res address(rd),imm4",
|
||||
"0110 0011 0000 imm4 address","res address,imm4",
|
||||
"1010 0011 dddd imm4","res rd,imm4",
|
||||
"0010 0011 0000 ssss 0000 dddd 0000 0000","res rd,rs",
|
||||
"0010 0010 ddN0 imm4","resb @rd,imm4",
|
||||
"0110 0010 ddN0 imm4 address","resb address(rd),imm4",
|
||||
"0110 0010 0000 imm4 address","resb address,imm4",
|
||||
"1010 0010 dddd imm4","resb rbd,imm4",
|
||||
"0010 0010 0000 ssss 0000 dddd 0000 0000","resb rbd,rs",
|
||||
"1000 1101 imm4 0011","resflg imm4",
|
||||
"1001 1110 0000 cccc","ret cc",
|
||||
"1011 0011 dddd 0000","rl rd,1",
|
||||
"1011 0011 dddd 0010","rl rd,2",
|
||||
"1011 0010 dddd 0000","rlb rbd,1",
|
||||
"1011 0010 dddd 0010","rlb rbd,2",
|
||||
"1011 0011 dddd 1000","rlc rd,1",
|
||||
"1011 0011 dddd 1010","rlc rd,2",
|
||||
"1011 0010 dddd 1000","rlcb rbd,1",
|
||||
"1011 0010 dddd 1010","rlcb rbd,2",
|
||||
"1011 1110 aaaa bbbb","rldb rbb,rba",
|
||||
"1011 0011 dddd 0100","rr rd,1",
|
||||
"1011 0011 dddd 0110","rr rd,2",
|
||||
"1011 0010 dddd 0100","rrb rbd,1",
|
||||
"1011 0010 dddd 0110","rrb rbd,2",
|
||||
"1011 0011 dddd 1100","rrc rd,1",
|
||||
"1011 0011 dddd 1110","rrc rd,2",
|
||||
"1011 0010 dddd 1100","rrcb rbd,1",
|
||||
"1011 0010 dddd 1110","rrcb rbd,2",
|
||||
"1011 1100 aaaa bbbb","rrdb rbb,rba",
|
||||
"1011 0111 ssss dddd","sbc rd,rs",
|
||||
"1011 0110 ssss dddd","sbcb rbd,rbs",
|
||||
"1011 0011 dddd 1011 0000 ssss 0000 0000","sda rd,rs",
|
||||
"1011 0010 dddd 1011 0000 ssss 0000 0000","sdab rbd,rs",
|
||||
"1011 0011 dddd 1111 0000 ssss 0000 0000","sdal rrd,rs",
|
||||
"1011 0011 dddd 0011 0000 ssss 0000 0000","sdl rd,rs",
|
||||
"1011 0010 dddd 0011 0000 ssss 0000 0000","sdlb rbd,rs",
|
||||
"1011 0011 dddd 0111 0000 ssss 0000 0000","sdll rrd,rs",
|
||||
"0010 0101 ddN0 imm4","set @rd,imm4",
|
||||
"0110 0101 ddN0 imm4 address","set address(rd),imm4",
|
||||
"0110 0101 0000 imm4 address","set address,imm4",
|
||||
"1010 0101 dddd imm4","set rd,imm4",
|
||||
"0010 0101 0000 ssss 0000 dddd 0000 0000","set rd,rs",
|
||||
"0010 0100 ddN0 imm4","setb @rd,imm4",
|
||||
"0110 0100 ddN0 imm4 address","setb address(rd),imm4",
|
||||
"0110 0100 0000 imm4 address","setb address,imm4",
|
||||
"1010 0100 dddd imm4","setb rbd,imm4",
|
||||
"0010 0100 0000 ssss 0000 dddd 0000 0000","setb rbd,rs",
|
||||
"1000 1101 imm4 0001","setflg imm4",
|
||||
"0011 1100 dddd 0101 imm16","sinb rbd,imm16",
|
||||
"0011 1101 dddd 0101 imm16","sinb rd,imm16",
|
||||
"0011 1011 ssN0 1000 0001 aaaa ddN0 1000","sind @rd,@rs,ra",
|
||||
"0011 1010 ssN0 1000 0001 aaaa ddN0 1000","sindb @rd,@rs,rba",
|
||||
"0011 1100 ssN0 0001 0000 aaaa ddN0 1000","sinib @rd,@rs,ra",
|
||||
"0011 1100 ssN0 0001 0000 aaaa ddN0 0000","sinibr @rd,@rs,ra",
|
||||
"1011 0011 dddd 1001 imm16","sla rd,imm16",
|
||||
"1011 0010 dddd 1001 imm16","slab rbd,imm16",
|
||||
"1011 0011 dddd 1101 imm16","slal rrd,imm16",
|
||||
"1011 0011 dddd 0001 imm16","sll rd,imm16",
|
||||
"1011 0010 dddd 0001 imm16","sllb rbd,imm16",
|
||||
"1011 0011 dddd 0101 imm16","slll rrd,imm16",
|
||||
"0011 1011 ssss 0111 imm16","sout imm16,rs",
|
||||
"0011 1010 ssss 0111 imm16","soutb imm16,rbs",
|
||||
"0011 1011 ssN0 1011 0000 aaaa ddN0 1000","soutd @rd,@rs,ra",
|
||||
"0011 1010 ssN0 1011 0000 aaaa ddN0 1000","soutdb @rd,@rs,rba",
|
||||
"0011 1100 ssN0 0011 0000 aaaa ddN0 1000","soutib @rd,@rs,ra",
|
||||
"0011 1100 ssN0 0011 0000 aaaa ddN0 0000","soutibr @rd,@rs,ra",
|
||||
"1011 0011 dddd 1001 nim16","sra rd,imm16",
|
||||
"1011 0010 dddd 1001 nim16","srab rbd,imm16",
|
||||
"1011 0011 dddd 1101 nim16","sral rrd,imm16",
|
||||
"1011 0011 dddd 0001 nim16","srl rd,imm16",
|
||||
"1011 0010 dddd 0001 nim16","srlb rbd,imm16",
|
||||
"1011 0011 dddd 0101 nim16","srll rrd,imm16",
|
||||
"0000 0011 ssN0 dddd","sub rd,@rs",
|
||||
"0100 0011 0000 dddd address","sub rd,address",
|
||||
"0100 0011 ssN0 dddd address","sub rd,address(rs)",
|
||||
"0000 0010 0000 dddd imm16","sub rd,imm16",
|
||||
"1000 0011 ssss dddd","sub rd,rs",
|
||||
"0000 0010 ssN0 dddd","subb rbd,@rs",
|
||||
"0100 0010 0000 dddd address","subb rbd,address",
|
||||
"0100 0010 ssN0 dddd address","subb rbd,address(rs)",
|
||||
"0000 0010 0000 dddd imm8 imm8","subb rbd,imm8",
|
||||
"1000 0010 ssss dddd","subb rbd,rbs",
|
||||
"0001 0010 ssN0 dddd","subl rrd,@rs",
|
||||
"0101 0010 0000 dddd address","subl rrd,address",
|
||||
"0101 0010 ssN0 dddd address","subl rrd,address(rs)",
|
||||
"0001 0010 0000 dddd imm32","subl rrd,imm32",
|
||||
"1001 0010 ssss dddd","subl rrd,rrs",
|
||||
"1010 1111 dddd cccc","tcc cc,rd",
|
||||
"1010 1110 dddd cccc","tccb cc,rbd",
|
||||
"0000 1101 ddN0 0100","test @rd",
|
||||
"0100 1101 0000 0100","test address",
|
||||
"0100 1101 ddN0 0100","test address(rd)",
|
||||
"1000 1101 dddd 0100","test rd",
|
||||
"0000 1100 ddN0 0100","testb @rd",
|
||||
"0100 1100 0000 0100","testb address",
|
||||
"0100 1100 ddN0 0100","testb address(rd)",
|
||||
"1000 1100 dddd 0100","testb rbd",
|
||||
"0001 1100 ddN0 1000","testl @rd",
|
||||
"0101 1100 0000 1000","testl address",
|
||||
"1001 1100 dddd 1000","testl rrd",
|
||||
"1011 1000 ddN0 1000 0000 aaaa ssN0 0000","trdb @rd,@rs,rba",
|
||||
"1011 1000 ddN0 1100 0000 aaaa ssN0 0000","trdrb @rd,@rs,rba",
|
||||
"1011 1000 ddN0 0000 0000 rrrr ssN0 0000","trib @rd,@rs,rbr",
|
||||
"1011 1000 ddN0 0100 0000 rrrr ssN0 0000","trirb @rd,@rs,rbr",
|
||||
"1011 1000 aaN0 1110 0000 rrrr bbN0 1110","trtdrb @ra,@rb,rbr",
|
||||
"1011 1000 aaN0 0010 0000 rrrr bbN0 0000","trtib @ra,@rb,rr",
|
||||
"1011 1000 aaN0 0110 0000 rrrr bbN0 1110","trtirb @ra,@rb,rbr",
|
||||
"1011 1000 aaN0 1010 0000 rrrr bbN0 0000","trtrb @ra,@rb,rbr",
|
||||
"0000 1101 ddN0 0110","tset @rd",
|
||||
"0100 1101 0000 0110","tset address",
|
||||
"0100 1101 ddN0 0110","tset address(rd)",
|
||||
"1000 1101 dddd 0110","tset rd",
|
||||
"0000 1100 ddN0 0110","tsetb @rd",
|
||||
"0100 1100 0000 0110","tsetb address",
|
||||
"0100 1100 ddN0 0110","tsetb address(rd)",
|
||||
"1000 1100 dddd 0110","tsetb rbd",
|
||||
"0000 1001 ssN0 dddd","xor rd,@rs",
|
||||
"0100 1001 0000 dddd address","xor rd,address",
|
||||
"0100 1001 ssN0 dddd address","xor rd,address(rs)",
|
||||
"0000 1001 0000 dddd imm16","xor rd,imm16",
|
||||
"1000 1001 ssss dddd","xor rd,rs",
|
||||
"0000 1000 ssN0 dddd","xorb rbd,@rs",
|
||||
"0100 1000 0000 dddd address","xorb rbd,address",
|
||||
"0100 1000 ssN0 dddd address","xorb rbd,address(rs)",
|
||||
"0000 1000 0000 dddd imm8 imm8","xorb rbd,imm8",
|
||||
"1000 1000 ssss dddd","xorb rbd,rbs",
|
||||
|
||||
|
||||
0,0
|
||||
}
|
||||
;
|
||||
|
||||
int count()
|
||||
{
|
||||
struct op *p = opt;
|
||||
int r = 0;
|
||||
while (p->name)
|
||||
{
|
||||
r++;
|
||||
p++;
|
||||
}
|
||||
return r;
|
||||
|
||||
}
|
||||
func(a,b)
|
||||
struct op *a;
|
||||
struct op *b;
|
||||
{
|
||||
return strcmp((a)->name, (b)->name);
|
||||
|
||||
|
||||
}
|
||||
|
||||
func1(a,b)
|
||||
struct op *a;
|
||||
struct op *b;
|
||||
{
|
||||
return strcmp((a)->bits, (b)->bits);
|
||||
|
||||
|
||||
}
|
||||
|
||||
/* opcode
|
||||
|
||||
literal 0000 nnnn insert nnn into stream
|
||||
operand 0001 nnnn insert operand reg nnn into stream
|
||||
*/
|
||||
|
||||
typedef struct tok_struct
|
||||
{
|
||||
|
||||
char *match;
|
||||
char *token;
|
||||
int length;
|
||||
};
|
||||
|
||||
|
||||
|
||||
struct tok_struct args[] =
|
||||
{
|
||||
|
||||
{ "address(rs)", "CLASS_X+(ARG_RS)",},
|
||||
{ "address(rd)", "CLASS_X+(ARG_RD)",},
|
||||
|
||||
{ "rs(disp16)","CLASS_BA+(ARG_RS)",},
|
||||
{ "rd(disp16)","CLASS_BA+(ARG_RD)",},
|
||||
|
||||
{ "address", "CLASS_DA",},
|
||||
{ "rd(rx)", "CLASS_BX+(ARG_RD)",},
|
||||
{ "rs(rx)","CLASS_BX+(ARG_RS)",},
|
||||
{ "disp16", "CLASS_DISP",},
|
||||
{ "disp12", "CLASS_DISP",},
|
||||
{ "disp7", "CLASS_DISP",},
|
||||
{ "disp8", "CLASS_DISP",},
|
||||
{ "flags","CLASS_FLAGS",},
|
||||
{ "imm16", "CLASS_IMM+(ARG_IMM16)",},
|
||||
{ "imm32", "CLASS_IMM+(ARG_IMM32)",},
|
||||
{ "imm4", "CLASS_IMM +(ARG_IMM4)",},
|
||||
{ "n", "CLASS_IMM + (ARG_IMMN)",},
|
||||
{ "ctrl", "CLASS_CTRL",},
|
||||
{ "rba", "CLASS_REG_BYTE+(ARG_RA)",},
|
||||
{ "rbb", "CLASS_REG_BYTE+(ARG_RB)",},
|
||||
{ "rbd", "CLASS_REG_BYTE+(ARG_RD)",},
|
||||
{ "rbs", "CLASS_REG_BYTE+(ARG_RS)",},
|
||||
{ "rbr", "CLASS_REG_BYTE+(ARG_RR)",},
|
||||
|
||||
{ "rrd","CLASS_REG_LONG+(ARG_RD)",},
|
||||
{ "rrs","CLASS_REG_LONG+(ARG_RS)",},
|
||||
|
||||
{ "rqd", "CLASS_REG_QUAD+(ARG_RD)",},
|
||||
|
||||
{ "rd", "CLASS_REG_WORD+(ARG_RD)",},
|
||||
{ "rs", "CLASS_REG_WORD+(ARG_RS)",},
|
||||
|
||||
{ "@rd", "CLASS_IR+(ARG_RD)",},
|
||||
{ "@ra", "CLASS_IR+(ARG_RA)",},
|
||||
{ "@rb", "CLASS_IR+(ARG_RB)",},
|
||||
{ "@rs", "CLASS_IR+(ARG_RS)",},
|
||||
|
||||
{ "imm8", "CLASS_IMM+(ARG_IMM8)",},
|
||||
{ "i2", "CLASS_IMM+(ARG_IMM2)",},
|
||||
{ "cc", "CLASS_CC",},
|
||||
|
||||
{ "rr", "CLASS_REG_WORD+(ARG_RR)",},
|
||||
{ "ra", "CLASS_REG_WORD+(ARG_RA)",},
|
||||
{ "rs", "CLASS_REG_WORD+(ARG_RS)",},
|
||||
|
||||
{ "1", "CLASS_IMM+(ARG_IMM_1)",},
|
||||
{ "2", "CLASS_IMM+(ARG_IMM_2)",},
|
||||
|
||||
0,0
|
||||
};
|
||||
|
||||
struct tok_struct toks[] =
|
||||
{
|
||||
"0000", "CLASS_BIT+0",1,
|
||||
"0001", "CLASS_BIT+1",1,
|
||||
"0010", "CLASS_BIT+2",1,
|
||||
"0011", "CLASS_BIT+3",1,
|
||||
"0100", "CLASS_BIT+4",1,
|
||||
"0101", "CLASS_BIT+5",1,
|
||||
"0110", "CLASS_BIT+6",1,
|
||||
"0111", "CLASS_BIT+7",1,
|
||||
"1000", "CLASS_BIT+8",1,
|
||||
"1001", "CLASS_BIT+9",1,
|
||||
"1010", "CLASS_BIT+10",1,
|
||||
"1011", "CLASS_BIT+11",1,
|
||||
"1100", "CLASS_BIT+12",1,
|
||||
"1101", "CLASS_BIT+13",1,
|
||||
"1110", "CLASS_BIT+14",1,
|
||||
"1111", "CLASS_BIT+15",1,
|
||||
|
||||
"ssss", "CLASS_REG+(ARG_RS)",1,
|
||||
"dddd", "CLASS_REG+(ARG_RD)",1,
|
||||
"aaaa", "CLASS_REG+(ARG_RA)",1,
|
||||
"bbbb", "CLASS_REG+(ARG_RB)",1,
|
||||
"rrrr", "CLASS_REG+(ARG_RR)",1,
|
||||
|
||||
"ssN0", "CLASS_REGN0+(ARG_RS)",1,
|
||||
"ddN0", "CLASS_REGN0+(ARG_RD)",1,
|
||||
"aaN0", "CLASS_REGN0+(ARG_RA)",1,
|
||||
"bbN0", "CLASS_REGN0+(ARG_RB)",1,
|
||||
"rrN0", "CLASS_REGN0+(ARG_RR)",1,
|
||||
|
||||
"cccc", "CLASS_CC",1,
|
||||
"nnnn", "CLASS_IMM+(ARG_IMMN)",1,
|
||||
"xxxx", "CLASS_REG+(ARG_RX)",1,
|
||||
"xxN0", "CLASS_REGN0+(ARG_RX)",1,
|
||||
"nminus1", "CLASS_IMM+(ARG_IMMNMINUS1)",1,
|
||||
|
||||
"disp16", "CLASS_DISP+(ARG_DISP16)",4,
|
||||
"disp12", "CLASS_DISP+(ARG_DISP12)",3,
|
||||
"flags", "CLASS_FLAGS",1,
|
||||
"address", "CLASS_ADDRESS",4,
|
||||
"imm4", "CLASS_IMM+(ARG_IMM4)",1,
|
||||
"imm8", "CLASS_IMM+(ARG_IMM8)",2,
|
||||
"imm16", "CLASS_IMM+(ARG_IMM16)",4,
|
||||
"imm32", "CLASS_IMM+(ARG_IMM32)",8,
|
||||
"nim16", "CLASS_IMM+(ARG_NIM16)",4,
|
||||
"0ccc", "CLASS_0CCC",1,
|
||||
"1ccc", "CLASS_1CCC",1,
|
||||
"disp8", "CLASS_DISP8",2,
|
||||
"0disp7", "CLASS_0DISP7",2,
|
||||
"1disp7", "CLASS_1DISP7",2,
|
||||
"01ii", "CLASS_01II",1,
|
||||
"00ii", "CLASS_00II",1,
|
||||
0,0
|
||||
|
||||
};
|
||||
|
||||
|
||||
char *translate(table, x, length)
|
||||
struct tok_struct *table;
|
||||
char *x;
|
||||
int *length;
|
||||
{
|
||||
|
||||
int found;
|
||||
found = 0;
|
||||
while (table->match)
|
||||
{
|
||||
int l = strlen(table->match);
|
||||
if (strncmp(table->match, x, l) == 0)
|
||||
{
|
||||
/* Got a hit */
|
||||
printf("%s", table->token);
|
||||
*length += table->length;
|
||||
return x + l;
|
||||
}
|
||||
|
||||
table++;
|
||||
}
|
||||
fprintf(stderr,"Can't find %s\n", x);
|
||||
while (*x)
|
||||
x++;
|
||||
return x;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
chewbits(bits, length)
|
||||
char *bits;
|
||||
int *length;
|
||||
{
|
||||
int i;
|
||||
int found;
|
||||
|
||||
int n = 0;
|
||||
*length = 0;
|
||||
printf("{");
|
||||
while (*bits)
|
||||
{
|
||||
while (*bits == ' ')
|
||||
{
|
||||
bits++;
|
||||
}
|
||||
bits = translate(toks, bits, length);
|
||||
n++;
|
||||
printf(",");
|
||||
|
||||
}
|
||||
while (n < BYTE_INFO_LEN-1) {
|
||||
printf("0,");
|
||||
n++;
|
||||
}
|
||||
printf("}");
|
||||
}
|
||||
|
||||
doreg(x)
|
||||
char *x;
|
||||
{
|
||||
printf("REGH %c ", x[0]);
|
||||
|
||||
}
|
||||
int chewname(name)
|
||||
char *name;
|
||||
{
|
||||
char *n;
|
||||
int nargs = 0;
|
||||
int nbytes= 0;
|
||||
n = name;
|
||||
printf("\"");
|
||||
while (*n && !iswhite(*n)) {
|
||||
printf("%c", *n );
|
||||
n++;
|
||||
}
|
||||
printf("\",{");
|
||||
/* Scan the operands and make entires for them -remember indirect things */
|
||||
while (*n) {
|
||||
int d;
|
||||
while (*n == ',' || iswhite(*n))
|
||||
n++;
|
||||
nargs++;
|
||||
n= translate(args, n, &d);
|
||||
printf(",");
|
||||
}
|
||||
if (nargs == 0) {
|
||||
printf("0");
|
||||
}
|
||||
printf("},");
|
||||
return nargs;
|
||||
}
|
||||
sub(x,c)
|
||||
char *x;
|
||||
char c;
|
||||
{
|
||||
while (*x)
|
||||
{
|
||||
if (x[0] == c
|
||||
&& x[1] == c
|
||||
&& x[2] == c
|
||||
&& x[3] == c) {
|
||||
x[2] = 'N';
|
||||
x[3] = '0';
|
||||
}
|
||||
x++;
|
||||
}
|
||||
}
|
||||
internal()
|
||||
{
|
||||
int c = count();
|
||||
struct op *new = malloc(sizeof(struct op) * c);
|
||||
struct op *p = opt;
|
||||
memcpy(new, p, c * sizeof(struct op));
|
||||
|
||||
/* sort all names in table alphabetically */
|
||||
qsort(new, c, sizeof(struct op), func);
|
||||
p = new;
|
||||
while (p->name) {
|
||||
/* If there are any @rs, sub the ssss into a ssn0,
|
||||
(rs), (ssn0)
|
||||
*/
|
||||
int loop = 1;
|
||||
while (loop) {
|
||||
char *s = p->name;
|
||||
loop = 0;
|
||||
while (*s) {
|
||||
if(s[0] == '@') {
|
||||
char c ;
|
||||
/* skip the r and sub the string */
|
||||
s++;
|
||||
c = s[1];
|
||||
sub(p->bits,c);
|
||||
}
|
||||
if (s[0] == '(' && s[3] == ')')
|
||||
{
|
||||
sub(p->bits, s[2]);
|
||||
}
|
||||
if (s[0] == '(')
|
||||
{
|
||||
sub(p->bits, s[-1]);
|
||||
}
|
||||
|
||||
s++;
|
||||
}
|
||||
|
||||
}
|
||||
printf("\"%s\",\"%s\",\n", p->bits, p->name);
|
||||
p++;
|
||||
}
|
||||
}
|
||||
gas()
|
||||
{
|
||||
|
||||
int c = count();
|
||||
int i;
|
||||
struct op *p = opt;
|
||||
int idx = 0;
|
||||
char *oldname = "";
|
||||
struct op *new = malloc(sizeof(struct op) * c);
|
||||
|
||||
memcpy(new, p, c * sizeof(struct op));
|
||||
|
||||
/* sort all names in table alphabetically */
|
||||
qsort(new, c, sizeof(struct op), func);
|
||||
|
||||
printf(" /* THIS FILE IS AUTOMAGICALLY GENERATED, DON'T EDIT IT */\n");
|
||||
|
||||
printf("#define ARG_MASK 0x0f\n");
|
||||
printf("#define ARG_RS 0x01\n");
|
||||
printf("#define ARG_RD 0x02\n");
|
||||
printf("#define ARG_RA 0x03\n");
|
||||
printf("#define ARG_RB 0x04\n");
|
||||
printf("#define ARG_RR 0x05\n");
|
||||
printf("#define ARG_RX 0x06\n");
|
||||
printf("#define ARG_IMM4 0x01\n");
|
||||
printf("#define ARG_IMM8 0x02\n");
|
||||
printf("#define ARG_IMM16 0x03\n");
|
||||
printf("#define ARG_IMM32 0x04\n");
|
||||
printf("#define ARG_IMMN 0x05\n");
|
||||
printf("#define ARG_IMMNMINUS1 0x05\n");
|
||||
printf("#define ARG_IMM_1 0x06\n");
|
||||
printf("#define ARG_IMM_2 0x07\n");
|
||||
printf("#define ARG_DISP16 0x08\n");
|
||||
printf("#define ARG_NIM16 0x09\n");
|
||||
printf("#define ARG_IMM2 0x0a\n");
|
||||
printf("#define ARG_DISP12 0x0b\n");
|
||||
printf("#define ARG_DISP8 0x0c\n");
|
||||
|
||||
printf("#define CLASS_MASK 0xfff0\n");
|
||||
printf("#define CLASS_X 0x10\n");
|
||||
printf("#define CLASS_BA 0x20\n");
|
||||
printf("#define CLASS_DA 0x30\n");
|
||||
printf("#define CLASS_BX 0x40\n");
|
||||
printf("#define CLASS_DISP 0x50\n");
|
||||
printf("#define CLASS_IMM 0x60\n");
|
||||
printf("#define CLASS_CC 0x70\n");
|
||||
printf("#define CLASS_CTRL 0x80\n");
|
||||
printf("#define CLASS_ADDRESS 0xd0\n");
|
||||
printf("#define CLASS_0CCC 0xe0\n");
|
||||
printf("#define CLASS_1CCC 0xf0\n");
|
||||
printf("#define CLASS_0DISP7 0x100\n");
|
||||
printf("#define CLASS_1DISP7 0x200\n");
|
||||
printf("#define CLASS_01II 0x300\n");
|
||||
printf("#define CLASS_00II 0x400\n");
|
||||
printf("#define CLASS_BIT 0x500\n");
|
||||
printf("#define CLASS_FLAGS 0x600\n");
|
||||
printf("#define CLASS_IR 0x700\n");
|
||||
printf("#define CLASS_DISP8 0x800\n");
|
||||
|
||||
|
||||
printf("#define CLASS_REG 0x7000\n");
|
||||
printf("#define CLASS_REG_BYTE 0x2000\n");
|
||||
printf("#define CLASS_REG_WORD 0x3000\n");
|
||||
printf("#define CLASS_REG_QUAD 0x4000\n");
|
||||
printf("#define CLASS_REG_LONG 0x5000\n");
|
||||
printf("#define CLASS_REGN0 0x8000\n");
|
||||
|
||||
|
||||
|
||||
#if 0
|
||||
for (i = 0; toks[i].token; i++)
|
||||
printf("#define %s\t0x%x\n",toks[i].token,i*16);
|
||||
#endif
|
||||
printf("typedef struct {\n");
|
||||
printf("char *name;\n");
|
||||
printf("unsigned short arg_info[4];\n");
|
||||
printf("unsigned short byte_info[%d];\n", BYTE_INFO_LEN);
|
||||
printf("int noperands;\n");
|
||||
printf("int length;\n");
|
||||
printf("int idx;\n");
|
||||
printf("} opcode_entry_type;\n");
|
||||
printf("#ifdef DEFINE_TABLE\n");
|
||||
printf("opcode_entry_type z8k_table[] = {\n");
|
||||
|
||||
while (new->name) {
|
||||
int nargs;
|
||||
int length;
|
||||
printf("{");
|
||||
nargs = chewname(new->name);
|
||||
|
||||
printf("\n\t");
|
||||
chewbits(new->bits, &length);
|
||||
length /=2;
|
||||
if (length &1) fail();
|
||||
|
||||
printf(",%d,%d,%d", nargs, length, idx);
|
||||
if(strcmp(oldname, new->name))
|
||||
{
|
||||
idx++;
|
||||
oldname = new->name;
|
||||
}
|
||||
printf("},\n");
|
||||
new++;
|
||||
}
|
||||
printf("0,0};\n");
|
||||
printf("#endif\n");
|
||||
}
|
||||
main(ac,av)
|
||||
int ac;
|
||||
char **av;
|
||||
{
|
||||
struct op *p = opt;
|
||||
|
||||
if (ac == 2 && strcmp(av[1],"-t")==0)
|
||||
{
|
||||
internal();
|
||||
}
|
||||
else if (ac == 2 && strcmp(av[1],"-h")==0)
|
||||
{
|
||||
while (p->name) {
|
||||
printf("%-25s\t%s\n", p->name, p->bits);
|
||||
p++;
|
||||
}
|
||||
}
|
||||
|
||||
else if (ac== 2 && strcmp(av[1], "-a") == 0)
|
||||
{
|
||||
gas();
|
||||
}
|
||||
else if (ac== 2 && strcmp(av[1], "-d") == 0)
|
||||
{
|
||||
/*dis();*/
|
||||
}
|
||||
else {
|
||||
printf("Usage: %s -t\n", av[0]);
|
||||
printf("-t : generate new z8.c internal table\n");
|
||||
printf("-a : generate new table for gas\n");
|
||||
printf("-d : generate new table for disassemble\n");
|
||||
printf("-h : generate new table for humans\n");
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
fail()
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user