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Add support for Score7 architecture.

This commit is contained in:
Nick Clifton 2009-03-02 10:33:08 +00:00
parent 9af17804e9
commit c3b7224ae4
76 changed files with 22948 additions and 5227 deletions
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17
bfd/ChangeLog
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@ -1,3 +1,20 @@
2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
* elf32-score7.c: New file.
* elf32-score.h: New file.
* elf32-score.c: Add code to support score 7. Set score7 as the
default.
* cpu-score.c: Add score7 architecure.
(compatibile): New function.
* Makefile.am: Add rules for building elf32-score7 object.
* Makefile.in: Regenerate.
* configure.in: Add elf32-score7 object to score vectors.
* configure: Regenerate.
* reloc.c: Add score7 relocs.
* archures.c: Add score3 and score7 machine numbers.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
2009-03-01 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* configure: Regenerate.

9
bfd/Makefile.am
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@ -289,6 +289,7 @@ BFD32_BACKENDS = \
elf32-ppc.lo \
elf32-s390.lo \
elf32-score.lo \
elf32-score7.lo \
elf32-sh.lo \
elf32-sh-symbian.lo \
elf32-sh64.lo \
@ -474,6 +475,7 @@ BFD32_BACKENDS_CFILES = \
elf32-sh64-com.c \
elf32-s390.c \
elf32-score.c \
elf32-score7.c \
elf32-sh.c \
elf32-sh-symbian.c \
elfxx-sparc.c \
@ -1570,7 +1572,12 @@ elf32-s390.lo: elf32-s390.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
elf32-score.lo: elf32-score.c $(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h $(INCDIR)/libiberty.h elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
$(INCDIR)/bfdlink.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
$(INCDIR)/bfdlink.h elf32-score.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
elf32-target.h
elf32-score7.lo: elf32-score7.c $(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h $(INCDIR)/libiberty.h elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
$(INCDIR)/bfdlink.h elf32-score.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
elf32-target.h
elf32-sh.lo: elf32-sh.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
$(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \

8
bfd/Makefile.in
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@ -555,6 +555,7 @@ BFD32_BACKENDS = \
elf32-ppc.lo \
elf32-s390.lo \
elf32-score.lo \
elf32-score7.lo \
elf32-sh.lo \
elf32-sh-symbian.lo \
elf32-sh64.lo \
@ -739,6 +740,7 @@ BFD32_BACKENDS_CFILES = \
elf32-sh64.c \
elf32-sh64-com.c \
elf32-s390.c \
elf32-score7.c \
elf32-score.c \
elf32-sh.c \
elf32-sh-symbian.c \
@ -2167,6 +2169,12 @@ elf32-score.lo: elf32-score.c $(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h $(INCDIR)/libiberty.h elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
$(INCDIR)/bfdlink.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
$(INCDIR)/bfdlink.h elf32-score.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
elf32-target.h
elf32-score7.lo: elf32-score7.c $(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h $(INCDIR)/libiberty.h elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
$(INCDIR)/bfdlink.h elf32-score.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
elf32-target.h
elf32-sh.lo: elf32-sh.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
$(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \

4
bfd/archures.c
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@ -1,6 +1,6 @@
/* BFD library support routines for architectures.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
Free Software Foundation, Inc.
Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
@ -376,6 +376,8 @@ DESCRIPTION
.#define bfd_mach_s390_31 31
.#define bfd_mach_s390_64 64
. bfd_arch_score, {* Sunplus score *}
.#define bfd_mach_score3 3
.#define bfd_mach_score7 7
. bfd_arch_openrisc, {* OpenRISC *}
. bfd_arch_mmix, {* Donald Knuth's educational processor. *}
. bfd_arch_xstormy16,

17
bfd/bfd-in2.h
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@ -2002,6 +2002,8 @@ enum bfd_architecture
#define bfd_mach_s390_31 31
#define bfd_mach_s390_64 64
bfd_arch_score, /* Sunplus score */
#define bfd_mach_score3 3
#define bfd_mach_score7 7
bfd_arch_openrisc, /* OpenRISC */
bfd_arch_mmix, /* Donald Knuth's educational processor. */
bfd_arch_xstormy16,
@ -3889,10 +3891,8 @@ instructions */
BFD_RELOC_390_GOTPLT20,
BFD_RELOC_390_TLS_GOTIE20,
/* Score relocations */
BFD_RELOC_SCORE_DUMMY1,
/* Low 16 bit for load/store */
/* Score relocations
Low 16 bit for load/store */
BFD_RELOC_SCORE_GPREL15,
/* This is a 24-bit reloc with the right 1 bit assumed to be 0 */
@ -3902,12 +3902,21 @@ instructions */
/* This is a 19-bit reloc with the right 1 bit assumed to be 0 */
BFD_RELOC_SCORE_BRANCH,
/* This is a 32-bit reloc for 48-bit instructions. */
BFD_RELOC_SCORE_IMM30,
/* This is a 32-bit reloc for 48-bit instructions. */
BFD_RELOC_SCORE_IMM32,
/* This is a 11-bit reloc with the right 1 bit assumed to be 0 */
BFD_RELOC_SCORE16_JMP,
/* This is a 8-bit reloc with the right 1 bit assumed to be 0 */
BFD_RELOC_SCORE16_BRANCH,
/* This is a 9-bit reloc with the right 1 bit assumed to be 0 */
BFD_RELOC_SCORE_BCMP,
/* Undocumented Score relocs */
BFD_RELOC_SCORE_GOT15,
BFD_RELOC_SCORE_GOT_LO16,

4
bfd/configure vendored
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@ -20783,8 +20783,8 @@ do
bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;;
bfd_elf32_bigscore_vec) tb="$tb elf32-score.lo elf32.lo $elf" ;;
bfd_elf32_littlescore_vec) tb="$tb elf32-score.lo elf32.lo $elf" ;;
bfd_elf32_bigscore_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true;;
bfd_elf32_littlescore_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true;;
# FIXME: We include cofflink.lo not because it's needed for
# bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec
# which needs it but does not list it. Should be fixed in right place.

4
bfd/configure.in
View File

@ -724,8 +724,8 @@ do
bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;;
bfd_elf32_bigscore_vec) tb="$tb elf32-score.lo elf32.lo $elf" ;;
bfd_elf32_littlescore_vec) tb="$tb elf32-score.lo elf32.lo $elf" ;;
bfd_elf32_bigscore_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true;;
bfd_elf32_littlescore_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true;;
# FIXME: We include cofflink.lo not because it's needed for
# bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec
# which needs it but does not list it. Should be fixed in right place.

68
bfd/cpu-score.c
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@ -1,8 +1,9 @@
/* BFD support for the score processor
Copyright 2006, 2007 Free Software Foundation, Inc.
Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Contributed by
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of BFD, the Binary File Descriptor library.
@ -21,32 +22,47 @@
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
const bfd_arch_info_type
bfd_score_arch =
/* This routine is provided two arch_infos and works out which Score
machine which would be compatible with both and returns a pointer
to its info structure. */
static const bfd_arch_info_type *
compatible (const bfd_arch_info_type * a, const bfd_arch_info_type * b)
{
32, /* There's 32 bits_per_word. */
32, /* There's 32 bits_per_address. */
8, /* There's 8 bits_per_byte. */
bfd_arch_score, /* One of enum bfd_architecture, defined
in archures.c and provided in
generated header files. */
0, /* Only 1 machine, but #255 for
historical reasons. */
"score", /* The arch_name. */
"score", /* The printable name is the same. */
4, /* Section alignment power; each section
is aligned to (only) 2^4 bytes. */
TRUE, /* This is the default "machine", since
there's only one. */
bfd_default_compatible, /* A default function for testing
"machine" compatibility of two
bfd_arch_info_type. */
bfd_default_scan, /* Check if an bfd_arch_info_type is a
match. */
NULL /* Pointer to next bfd_arch_info_type in
the same family. */
/* If a & b are for different architectures we can do nothing. */
if (a->arch != b->arch)
return NULL;
if (a->mach != b->mach)
return NULL;
return a;
}
#define N(addr_bits, machine, print, default, next) \
{ \
32, /* 16 bits in a word. */ \
32, /* Bits in an address. */ \
8, /* 8 bits in a byte. */ \
bfd_arch_score, \
machine, /* Machine number. */ \
"score", /* Architecture name. */ \
print, /* Printable name. */ \
4, /* Section align power. */ \
default, /* The default machine. */ \
compatible, \
bfd_default_scan, \
next \
}
static const bfd_arch_info_type arch_info_struct[] =
{
N (16, bfd_mach_score3, "score3", FALSE, NULL),
};
const bfd_arch_info_type bfd_score_arch =
N (16, bfd_mach_score7, "score7", TRUE, & arch_info_struct[0]);

2200
bfd/elf32-score.c
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File diff suppressed because it is too large Load Diff

152
bfd/elf32-score.h Normal file
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@ -0,0 +1,152 @@
/* 32-bit ELF support for S+core.
Copyright 2009 Free Software Foundation, Inc.
Contributed by
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "elf/common.h"
#include "elf/internal.h"
extern void
s7_bfd_score_elf_hide_symbol (struct bfd_link_info *,
struct elf_link_hash_entry *,
bfd_boolean);
extern void
s7_bfd_score_info_to_howto (bfd *, arelent *, Elf_Internal_Rela *);
extern bfd_boolean
s7_bfd_score_elf_relocate_section (bfd *,
struct bfd_link_info *,
bfd *,
asection *,
bfd_byte *,
Elf_Internal_Rela *,
Elf_Internal_Sym *,
asection **);
extern bfd_boolean
s7_bfd_score_elf_check_relocs (bfd *,
struct bfd_link_info *,
asection *,
const Elf_Internal_Rela *);
extern bfd_boolean
s7_bfd_score_elf_add_symbol_hook (bfd *,
struct bfd_link_info *,
Elf_Internal_Sym *,
const char **,
flagword *,
asection **,
bfd_vma *);
extern void
s7_bfd_score_elf_symbol_processing (bfd *, asymbol *);
extern bfd_boolean
s7_bfd_score_elf_link_output_symbol_hook (struct bfd_link_info *,
const char *,
Elf_Internal_Sym *,
asection *,
struct elf_link_hash_entry *);
extern bfd_boolean
s7_bfd_score_elf_section_from_bfd_section (bfd *,
asection *,
int *);
extern bfd_boolean
s7_bfd_score_elf_adjust_dynamic_symbol (struct bfd_link_info *,
struct elf_link_hash_entry *);
extern bfd_boolean
s7_bfd_score_elf_always_size_sections (bfd *, struct bfd_link_info *);
extern bfd_boolean
s7_bfd_score_elf_size_dynamic_sections (bfd *, struct bfd_link_info *);
extern bfd_boolean
s7_bfd_score_elf_create_dynamic_sections (bfd *, struct bfd_link_info *);
extern bfd_boolean
s7_bfd_score_elf_finish_dynamic_symbol (bfd *,
struct bfd_link_info *,
struct elf_link_hash_entry *,
Elf_Internal_Sym *);
extern bfd_boolean
s7_bfd_score_elf_finish_dynamic_sections (bfd *, struct bfd_link_info *);
extern bfd_boolean
s7_bfd_score_elf_fake_sections (bfd *,
Elf_Internal_Shdr *,
asection *);
extern bfd_boolean
s7_bfd_score_elf_section_processing (bfd *, Elf_Internal_Shdr *);
extern bfd_boolean
s7_bfd_score_elf_write_section (bfd *, asection *, bfd_byte *);
extern void
s7_bfd_score_elf_copy_indirect_symbol (struct bfd_link_info *,
struct elf_link_hash_entry *,
struct elf_link_hash_entry *);
extern bfd_boolean
s7_bfd_score_elf_discard_info (bfd *, struct elf_reloc_cookie *,
struct bfd_link_info *);
extern bfd_boolean
s7_bfd_score_elf_ignore_discarded_relocs (asection *);
extern asection *
s7_bfd_score_elf_gc_mark_hook (asection *,
struct bfd_link_info *,
Elf_Internal_Rela *,
struct elf_link_hash_entry *,
Elf_Internal_Sym *);
extern bfd_boolean
s7_bfd_score_elf_grok_prstatus (bfd *, Elf_Internal_Note *);
extern bfd_boolean
s7_bfd_score_elf_grok_psinfo (bfd *, Elf_Internal_Note *);
extern reloc_howto_type *
s7_elf32_score_reloc_type_lookup (bfd *, bfd_reloc_code_real_type);
extern struct bfd_link_hash_table *
s7_elf32_score_link_hash_table_create (bfd *);
extern bfd_boolean
s7_elf32_score_print_private_bfd_data (bfd *, void *);
extern bfd_boolean
s7_elf32_score_merge_private_bfd_data (bfd *, bfd *);
extern bfd_boolean
s7_elf32_score_new_section_hook (bfd *, asection *);
extern bfd_boolean
_bfd_score_elf_common_definition (Elf_Internal_Sym *);
#define elf_backend_common_definition _bfd_score_elf_common_definition

3947
bfd/elf32-score7.c Normal file
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File diff suppressed because it is too large Load Diff

4
bfd/libbfd.h
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@ -1683,13 +1683,15 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_390_GOT20",
"BFD_RELOC_390_GOTPLT20",
"BFD_RELOC_390_TLS_GOTIE20",
"BFD_RELOC_SCORE_DUMMY1",
"BFD_RELOC_SCORE_GPREL15",
"BFD_RELOC_SCORE_DUMMY2",
"BFD_RELOC_SCORE_JMP",
"BFD_RELOC_SCORE_BRANCH",
"BFD_RELOC_SCORE_IMM30",
"BFD_RELOC_SCORE_IMM32",
"BFD_RELOC_SCORE16_JMP",
"BFD_RELOC_SCORE16_BRANCH",
"BFD_RELOC_SCORE_BCMP",
"BFD_RELOC_SCORE_GOT15",
"BFD_RELOC_SCORE_GOT_LO16",
"BFD_RELOC_SCORE_CALL15",

17
bfd/reloc.c
View File

@ -4194,13 +4194,10 @@ ENUMX
ENUMDOC
Long displacement extension.
ENUM
BFD_RELOC_SCORE_DUMMY1
ENUMDOC
Score relocations
ENUM
BFD_RELOC_SCORE_GPREL15
ENUMDOC
Score relocations
Low 16 bit for load/store
ENUM
BFD_RELOC_SCORE_DUMMY2
@ -4212,6 +4209,14 @@ ENUM
BFD_RELOC_SCORE_BRANCH
ENUMDOC
This is a 19-bit reloc with the right 1 bit assumed to be 0
ENUM
BFD_RELOC_SCORE_IMM30
ENUMDOC
This is a 32-bit reloc for 48-bit instructions.
ENUM
BFD_RELOC_SCORE_IMM32
ENUMDOC
This is a 32-bit reloc for 48-bit instructions.
ENUM
BFD_RELOC_SCORE16_JMP
ENUMDOC
@ -4220,6 +4225,10 @@ ENUM
BFD_RELOC_SCORE16_BRANCH
ENUMDOC
This is a 8-bit reloc with the right 1 bit assumed to be 0
ENUM
BFD_RELOC_SCORE_BCMP
ENUMDOC
This is a 9-bit reloc with the right 1 bit assumed to be 0
ENUM
BFD_RELOC_SCORE_GOT15
ENUMX

14
gas/ChangeLog
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@ -1,3 +1,17 @@
2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
* config/tc-score7.c: New file.
* doc/c-score.texi: New file.
* Makefile.am: Update dependencies for tc-score.c.
* Makefile.in: Regenerate.
* NEWS: Mention support for Score7 architecture.
* config/tc-score.c: Add support for Score7 architecture.
* config/tc-score.h: Likewise.
* doc/Makefile.am: Add c-score.texi.
* doc/Makefile.in: Regenerate.
* doc/all.texi: Add Score7.
* doc/as.texinfo: Add Score7.
2009-03-01 Mark Mitchell <mark@codesourcery.com>
* config/tc-arm.c (md_assemble): Allow barrier instructions on

11
gas/Makefile.am
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@ -1396,8 +1396,9 @@ DEPTC_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
$(INCDIR)/opcode/score-inst.h $(INCDIR)/opcode/score-datadep.h \
struc-symbol.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h
$(INCDIR)/opcode/score-inst.h $(srcdir)/config/tc-score7.c \
struc-symbol.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
dwarf2dbg.h
DEPTC_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
$(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
@ -1786,8 +1787,8 @@ DEPOBJ_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
DEPOBJ_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
struc-symbol.h $(INCDIR)/aout/aout64.h
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/config/tc-score7.c \
$(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
DEPOBJ_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
$(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@ -2116,7 +2117,7 @@ DEP_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
$(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
$(BFDDIR)/libcoff.h
$(BFDDIR)/libcoff.h $(srcdir)/config/tc-score7.c
DEP_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
$(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h

6
gas/Makefile.in
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@ -1200,7 +1200,7 @@ DEPTC_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
$(INCDIR)/opcode/score-inst.h $(INCDIR)/opcode/score-datadep.h \
$(INCDIR)/opcode/score-inst.h dwarf2dbg.h $(srcdir)/config/tc-score7.c \
struc-symbol.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h
DEPTC_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
@ -1671,8 +1671,8 @@ DEPOBJ_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
DEPOBJ_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
struc-symbol.h $(INCDIR)/aout/aout64.h
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/config/tc-score7.c \
$(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
DEPOBJ_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
$(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \

2
gas/NEWS
View File

@ -1,5 +1,7 @@
-*- text -*-
* Add support for Sunplus score architecture.
* Add support for Lattice Mico32 (lm32) architecture.
Changes in 2.19:

8261
gas/config/tc-score.c
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File diff suppressed because it is too large Load Diff

11
gas/config/tc-score.h
View File

@ -1,6 +1,7 @@
/* tc-score.h -- Score specific file for assembler
Copyright 2006, 2007 Free Software Foundation, Inc.
Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Contributed by:
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
@ -38,7 +39,7 @@
#define md_relax_frag(segment, fragp, stretch) score_relax_frag (segment, fragp, stretch)
extern int score_relax_frag (asection *, struct frag *, long);
#define md_frag_check(fragp) score_frag_check (fragp)
/* #define md_frag_check(fragp) score_frag_check (fragp) */
extern void score_frag_check (fragS *);
#define TC_VALIDATE_FIX(FIXP, SEGTYPE, SKIP) score_validate_fix (FIXP)
@ -74,10 +75,4 @@ struct score_tc_frag_data
#define GLOBAL_OFFSET_TABLE_NAME "__GLOBAL_OFFSET_TABLE_"
#endif
enum score_pic_level
{
NO_PIC,
PIC
};
#endif /*TC_SCORE */

6987
gas/config/tc-score7.c Normal file
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File diff suppressed because it is too large Load Diff

3
gas/doc/Makefile.am
View File

@ -58,6 +58,7 @@ CPU_DOCS = \
c-pj.texi \
c-ppc.texi \
c-s390.texi \
c-score.texi \
c-sh.texi \
c-sh64.texi \
c-sparc.texi \
@ -75,7 +76,7 @@ install-data-local: install-info
pdf__strip_dir = `echo $$p | sed -e 's|^.*/||'`;
install-pdf: install-pdf-am
install-pdf-am: $(PDFS)
@$(NORMAL_INSTALL)
test -z "$(pdfdir)" || $(mkinstalldirs) "$(DESTDIR)$(pdfdir)"

1
gas/doc/Makefile.in
View File

@ -279,6 +279,7 @@ CPU_DOCS = \
c-pj.texi \
c-ppc.texi \
c-s390.texi \
c-score.texi \
c-sh.texi \
c-sh64.texi \
c-sparc.texi \

3
gas/doc/all.texi
View File

@ -1,5 +1,5 @@
@c Copyright 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002,
@c 2003, 2005
@c 2003, 2005, 2009
@c Free Software Foundation, Inc.
@c This file is part of the documentation for the GAS manual
@ -58,6 +58,7 @@
@set PJ
@set PPC
@set S390
@set SCORE
@set SH
@set SPARC
@set TIC54X

33
gas/doc/as.texinfo
View File

@ -1,6 +1,6 @@
\input texinfo @c -*-Texinfo-*-
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
@c Free Software Foundation, Inc.
@c UPDATE!! On future updates--
@c (1) check for new machine-dep cmdline options in
@ -101,7 +101,7 @@ This file documents the GNU Assembler "@value{AS}".
@c man begin COPYRIGHT
Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
2006, 2007, 2008 Free Software Foundation, Inc.
2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
@ -151,7 +151,7 @@ done.
@vskip 0pt plus 1filll
Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
2006, 2007, 2008 Free Software Foundation, Inc.
2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
@ -423,6 +423,14 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-mregnames}|@b{-mno-regnames}]
[@b{-mwarn-areg-zero}]
@end ifset
@ifset SCORE
@emph{Target SCORE options:}
[@b{-EB}][@b{-EL}][@b{-FIXDD}][@b{-NWARN}]
[@b{-SCORE5}][@b{-SCORE5U}][@b{-SCORE7}][@b{-SCORE3}]
[@b{-march=score7}][@b{-march=score3}]
[@b{-USE_R1}][@b{-KPIC}][@b{-O0}][@b{-G} @var{num}][@b{-V}]
@end ifset
@ifset SPARC
@emph{Target SPARC options:}
@ -2233,9 +2241,15 @@ is considered a comment and is ignored. The line comment character is
@ifset PPC
@samp{#} for Motorola PowerPC;
@end ifset
<<<<<<< as.texinfo
@ifset SCORE
@samp{#} for the Sunplus SCORE;
@end ifset
=======
@ifset S390
@samp{#} for IBM S/390;
@end ifset
>>>>>>> 1.196
@ifset SH
@samp{!} for the Renesas / SuperH SH;
@end ifset
@ -6750,9 +6764,15 @@ subject, see the hardware manufacturer's manual.
@ifset PPC
* PPC-Dependent:: PowerPC Dependent Features
@end ifset
<<<<<<< as.texinfo
@ifset SCORE
* SCORE-Dependent:: SCORE Dependent Features
@end ifset
=======
@ifset S390
* S/390-Dependent:: IBM S/390 Dependent Features
@end ifset
>>>>>>> 1.196
@ifset SPARC
* Sparc-Dependent:: SPARC Dependent Features
@end ifset
@ -6921,10 +6941,17 @@ family.
@include c-ppc.texi
@end ifset
<<<<<<< as.texinfo
@ifset SCORE
@include c-score.texi
@end ifset
=======
@ifset S390
@include c-s390.texi
@end ifset
>>>>>>> 1.196
@ifset SH
@include c-sh.texi
@include c-sh64.texi

142
gas/doc/c-score.texi Normal file
View File

@ -0,0 +1,142 @@
@c Copyright 2009
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node SCORE-Dependent
@chapter SCORE Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter SCORE Dependent Features
@end ifclear
@cindex SCORE processor
@menu
* SCORE-Opts:: Assembler options
* SCORE-Pseudo:: SCORE Assembler Directives
@end menu
@node SCORE-Opts
@section Options
@cindex options for SCORE
@cindex SCORE options
@cindex architectures, SCORE
@cindex SCORE architectures
The following table lists all available SCORE options.
@table @code
@item -G @var{num}
This option sets the largest size of an object that can be referenced
implicitly with the @code{gp} register. The default value is 8.
@item -EB
Assemble code for a big-endian cpu
@itemx -EL
Assemble code for a little-endian cpu
@item -FIXDD
Assemble code for fix data dependency
@item -NWARN
Assemble code for no warning message for fix data dependency
@item -SCORE5
Assemble code for target is SCORE5
@itemx -SCORE5U
Assemble code for target is SCORE5U
@itemx -SCORE7
Assemble code for target is SCORE7, this is default setting
@itemx -SCORE3
Assemble code for target is SCORE3
@item -march=score7
Assemble code for target is SCORE7, this is default setting
@item -march=score3
Assemble code for target is SCORE3
@item -USE_R1
Assemble code for no warning message when using temp register r1
@item -KPIC
Generate code for PIC. This option tells the assembler to generate
score position-independent macro expansions. It also tells the
assembler to mark the output file as PIC.
@item -O0
Assembler will not perform any optimizations
@item -V
Sunplus release version
@end table
@node SCORE-Pseudo
@section SCORE Assembler Directives
@cindex directives for SCORE
@cindex SCORE directives
A number of assembler directives are available for SCORE. The
following table is far from complete.
@table @code
@item .set nwarn
Let the assembler not to generate warnings if the source machine
language instructions happen data dependency.
@item .set fixdd
Let the assembler to insert bubbles (32 bit nop instruction /
16 bit nop! Instruction) if the source machine language instructions
happen data dependency.
@item .set nofixdd
Let the assembler to generate warnings if the source machine
language instructions happen data dependency. (Default)
@item .set r1
Let the assembler not to generate warnings if the source program
uses r1. allow user to use r1
@item set nor1
Let the assembler to generate warnings if the source program uses
r1. (Default)
@item .sdata
Tell the assembler to add subsequent data into the sdata section
@item .rdata
Tell the assembler to add subsequent data into the rdata section
@item .frame "frame-register", "offset", "return-pc-register"
Describe a stack frame. "frame-register" is the frame register,
"offset" is the distance from the frame register to the virtual
frame pointer, "return-pc-register" is the return program register.
You must use ".ent" before ".frame" and only one ".frame" can be
used per ".ent".
@item .mask "bitmask", "frameoffset"
Indicate which of the integer registers are saved in the current
function's stack frame, this is for the debugger to explain the
frame chain.
@item .ent "proc-name"
Set the beginning of the procedure "proc_name". Use this directive
when you want to generate information for the debugger.
@item .end proc-name
Set the end of a procedure. Use this directive to generate information
for the debugger.
@item .bss
Switch the destination of following statements into the bss section,
which is used for data that is uninitialized anywhere.
@end table

32
gas/testsuite/ChangeLog
View File

@ -1,3 +1,35 @@
2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
* gas/score/arith_32-lt.d: New file.
* gas/score/arith_32.d: New file.
* gas/score/arith_32.s: New file.
* gas/score/bit_32-lt.d: New file.
* gas/score/bit_32.d: New file.
* gas/score/bit_32.s: New file.
* gas/score/branch_32-lt.d: New file.
* gas/score/branch_32.d: New file.
* gas/score/branch_32.s: New file.
* gas/score/cmp_32-lt.d: New file.
* gas/score/cmp_32.d: New file.
* gas/score/cmp_32.s: New file.
* gas/score/load_store_32-lt.d: New file.
* gas/score/load_store_32.d: New file.
* gas/score/load_store_32.s: New file.
* gas/score/logical_32-lt.d: New file.
* gas/score/logical_32.d: New file.
* gas/score/logical_32.s: New file.
* gas/score/mv_32-lt.d: New file.
* gas/score/mv_32.d: New file.
* gas/score/mv_32.s: New file.
* gas/score/relax_32.exp: New file.
* gas/score/relaxation_macro.h: New file.
* gas/score/shift_32-lt.d: New file.
* gas/score/shift_32.d: New file.
* gas/score/shift_32.s: New file.
* gas/score/syscontrol_32-lt.d: New file.
* gas/score/syscontrol_32.d: New file.
* gas/score/syscontrol_32.s: New file.
2009-03-01 Mark Mitchell <mark@codesourcery.com>
* gas/arm/archv6m.s: Add dmb, dsb, and isb.

16
gas/testsuite/gas/score/arith_32-lt.d Normal file
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@ -0,0 +1,16 @@
#as: -march=score3 -I${srcdir}/${subdir} -EL
#objdump: -s
#source: arith_32.s
.*: file format elf32-littlescore
Contents of section .text:
0000 0f480f48 0f480f48 0f480f48 0f480f48 .*
0010 0f480080 113c0080 10401082 10001082 .*
0020 10440180 10080f49 0f490f49 0f490f49 .*
0030 0f490f49 0f490f49 0080153c 00801440 .*
0040 10821400 10821444 01801408 205c1f5c .*
0050 e05fdf5f 205c205c 205c205c 205c205c .*
0060 205c205c 0384c17f 0384be7f 00844000 .*
0070 0386c07f 00863e00 .*
#pass

55
gas/testsuite/gas/score/arith_32.d Normal file
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@ -0,0 +1,55 @@
#as: -march=score3 -I${srcdir}/${subdir}
#objdump: -d
#source: arith_32.s
.*: file format .*
Disassembly of section .text:
00000000 <.text>:
0: 480f add! r0, r15
2: 480f add! r0, r15
4: 480f add! r0, r15
6: 480f add! r0, r15
8: 480f add! r0, r15
a: 480f add! r0, r15
c: 480f add! r0, r15
e: 480f add! r0, r15
10: 480f add! r0, r15
12: 8000 3c11 add.c r0, r0, r15
16: 8000 4010 add r0, r0, r16
1a: 8210 0010 add r16, r16, r0
1e: 8210 4410 add r16, r16, r17
22: 8001 0810 add r0, r1, r2
26: 490f sub! r0, r15
28: 490f sub! r0, r15
2a: 490f sub! r0, r15
2c: 490f sub! r0, r15
2e: 490f sub! r0, r15
30: 490f sub! r0, r15
32: 490f sub! r0, r15
34: 490f sub! r0, r15
36: 490f sub! r0, r15
38: 8000 3c15 sub.c r0, r0, r15
3c: 8000 4014 sub r0, r0, r16
40: 8210 0014 sub r16, r16, r0
44: 8210 4414 sub r16, r16, r17
48: 8001 0814 sub r0, r1, r2
4c: 5c20 addi! r0, -32
4e: 5c1f addi! r0, 31
50: 5fe0 addi! r15, -32
52: 5fdf addi! r15, 31
54: 5c20 addi! r0, -32
56: 5c20 addi! r0, -32
58: 5c20 addi! r0, -32
5a: 5c20 addi! r0, -32
5c: 5c20 addi! r0, -32
5e: 5c20 addi! r0, -32
60: 5c20 addi! r0, -32
62: 5c20 addi! r0, -32
64: 8403 7fc1 addi.c r0, -32
68: 8403 7fbe addi r0, -33
6c: 8400 0040 addi r0, 32
70: 8603 7fc0 addi r16, -32
74: 8600 003e addi r16, 31
#pass

43
gas/testsuite/gas/score/arith_32.s Normal file
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@ -0,0 +1,43 @@
/*
* tests for arithmetic instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.macro _arith_op_pattern insn insn1
insn_32 "\insn r0, r0, r15"
tran_16_32 "\insn! r0, r15", "\insn r0, r0, r15"
/* shouldn't alter */
.set r1
insn_32 "\insn1 r0, r0, r15"
insn_32 "\insn r0, r0, r16"
insn_32 "\insn r16, r16, r0"
insn_32 "\insn r16, r16, r17"
insn_32 "\insn r0, r1, r2"
.endm
.text
/* add rD,rA,rB -> add! rD,rA */
_arith_op_pattern "add", "add.c"
/* sub rD,rA,rB -> sub rD,rA */
_arith_op_pattern "sub", "sub.c"
/* addi rD,SImm16 -> addi! rD,SImm6 */
insn_32 "addi r0, -32"
insn_32 "addi r0, 31"
insn_32 "addi r15, -32"
insn_32 "addi r15, 31"
tran_16_32 "addi! r0,-32", "addi r0,-32"
/* shouldn't alter */
insn_32 "addi.c r0, -32"
insn_32 "addi r0, -33"
insn_32 "addi r0, 32"
insn_32 "addi r16, -32"
insn_32 "addi r16, 31"

17
gas/testsuite/gas/score/bit_32-lt.d Normal file
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@ -0,0 +1,17 @@
#as: -march=score3 -I${srcdir}/${subdir} -EL
#objdump: -s
#source: bit_32.s
.*: file format elf32-littlescore
Contents of section .text:
0000 00501f50 e051ff51 00500050 00500050 .*
0010 00500050 00500050 00802900 10822800 .*
0020 1082287c 00521f52 e053ff53 00520052 .*
0030 00520052 00520052 00520052 00802b00 .*
0040 10822a00 10822a7c 00561f56 e057ff57 .*
0050 00560056 00560056 00560056 00560056 .*
0060 00802f00 10822e00 10822e7c 00541f54 .*
0070 e055ff55 00540054 00540054 00540054 .*
0080 00540054 10802d00 10802d7c .*
#pass

69
gas/testsuite/gas/score/bit_32.d Normal file
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@ -0,0 +1,69 @@
#as: -march=score3 -I${srcdir}/${subdir}
#objdump: -d
#source: bit_32.s
.*: file format .*
Disassembly of section .text:
00000000 <.text>:
0: 5000 bitclr! r0, 0x0
2: 501f bitclr! r0, 0x1f
4: 51e0 bitclr! r15, 0x0
6: 51ff bitclr! r15, 0x1f
8: 5000 bitclr! r0, 0x0
a: 5000 bitclr! r0, 0x0
c: 5000 bitclr! r0, 0x0
e: 5000 bitclr! r0, 0x0
10: 5000 bitclr! r0, 0x0
12: 5000 bitclr! r0, 0x0
14: 5000 bitclr! r0, 0x0
16: 5000 bitclr! r0, 0x0
18: 8000 0029 bitclr.c r0, r0, 0x0
1c: 8210 0028 bitclr r16, r16, 0x0
20: 8210 7c28 bitclr r16, r16, 0x1f
24: 5200 bitset! r0, 0x0
26: 521f bitset! r0, 0x1f
28: 53e0 bitset! r15, 0x0
2a: 53ff bitset! r15, 0x1f
2c: 5200 bitset! r0, 0x0
2e: 5200 bitset! r0, 0x0
30: 5200 bitset! r0, 0x0
32: 5200 bitset! r0, 0x0
34: 5200 bitset! r0, 0x0
36: 5200 bitset! r0, 0x0
38: 5200 bitset! r0, 0x0
3a: 5200 bitset! r0, 0x0
3c: 8000 002b bitset.c r0, r0, 0x0
40: 8210 002a bitset r16, r16, 0x0
44: 8210 7c2a bitset r16, r16, 0x1f
48: 5600 bittgl! r0, 0x0
4a: 561f bittgl! r0, 0x1f
4c: 57e0 bittgl! r15, 0x0
4e: 57ff bittgl! r15, 0x1f
50: 5600 bittgl! r0, 0x0
52: 5600 bittgl! r0, 0x0
54: 5600 bittgl! r0, 0x0
56: 5600 bittgl! r0, 0x0
58: 5600 bittgl! r0, 0x0
5a: 5600 bittgl! r0, 0x0
5c: 5600 bittgl! r0, 0x0
5e: 5600 bittgl! r0, 0x0
60: 8000 002f bittgl.c r0, r0, 0x0
64: 8210 002e bittgl r16, r16, 0x0
68: 8210 7c2e bittgl r16, r16, 0x1f
6c: 5400 bittst! r0, 0x0
6e: 541f bittst! r0, 0x1f
70: 55e0 bittst! r15, 0x0
72: 55ff bittst! r15, 0x1f
74: 5400 bittst! r0, 0x0
76: 5400 bittst! r0, 0x0
78: 5400 bittst! r0, 0x0
7a: 5400 bittst! r0, 0x0
7c: 5400 bittst! r0, 0x0
7e: 5400 bittst! r0, 0x0
80: 5400 bittst! r0, 0x0
82: 5400 bittst! r0, 0x0
84: 8010 002d bittst.c r16, 0x0
88: 8010 7c2d bittst.c r16, 0x1f
#pass

43
gas/testsuite/gas/score/bit_32.s Normal file
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@ -0,0 +1,43 @@
/*
* tests for bit operations' instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.macro _bit_op_pattern insn insn1
insn_32 "\insn r0, r0, 0"
insn_32 "\insn r0, r0, 0x1f"
insn_32 "\insn r15, r15, 0"
insn_32 "\insn r15, r15, 0x1f"
tran_16_32 "\insn! r0,0", "\insn r0,r0,0"
/* shouldn't alter */
insn_32 "\insn1 r0, r0, 0"
insn_32 "\insn r16, r16, 0"
insn_32 "\insn r16, r16, 0x1f"
.endm
.text
/*
* bitclr rD,rA,BN5 -> bitclr! rD,BN5
* bitset rD,rA,BN5 -> bitset! rD,BN5
* bittgl rD,rA,BN5 -> bittgl! rD,BN5
*/
_bit_op_pattern "bitclr", "bitclr.c"
_bit_op_pattern "bitset", "bitset.c"
_bit_op_pattern "bittgl", "bittgl.c"
/* bittst.c rA,BN5 <-> bittst! rD,BN5" */
insn_32 "bittst.c r0, 0"
insn_32 "bittst.c r0, 0x1f"
insn_32 "bittst.c r15, 0"
insn_32 "bittst.c r15, 0x1f"
tran_16_32 "bittst! r0,0", "bittst.c r0,0"
/* shouldn't alter */
insn_32 "bittst.c r16, 0"
insn_32 "bittst.c r16, 0x1f"

1652
gas/testsuite/gas/score/branch_32-lt.d Normal file
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File diff suppressed because it is too large Load Diff

578
gas/testsuite/gas/score/branch_32.d Normal file
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@ -0,0 +1,578 @@
#as: -march=score3 -I${srcdir}/${subdir}
#objdump: -d
#source: branch_32.s
.*: file format .*
Disassembly of section .text:
00000000 <.text>:
0: 3400 bgtu! 0x0
2: 35ff bgtu! 0x0
4: 35fe bgtu! 0x0
6: 35fd bgtu! 0x0
8: 93ff 0bf8 bgtu 0x0
c: 93ff 0bf4 bgtu 0x0
10: 35f8 bgtu! 0x0
12: 93ff 0bee bgtu 0x0
16: 93ff 0bea bgtu 0x0
1a: 93ff 0be7 bgtul 0x0
...
21e: 93ff 09e2 bgtu 0x0
222: 93ff 09de bgtu 0x0
226: 93ff 09da bgtu 0x0
22a: 93ff 09d6 bgtu 0x0
22e: 93ff 09d2 bgtu 0x0
232: 93ff 09ce bgtu 0x0
236: 93ff 09ca bgtu 0x0
23a: 93ff 09c6 bgtu 0x0
23e: 93ff 09c2 bgtu 0x0
242: 93ff 09bf bgtul 0x0
246: 9000 0a46 bgtu 0x48c
24a: 9000 0a42 bgtu 0x48c
24e: 9000 0a3e bgtu 0x48c
252: 9000 0a3a bgtu 0x48c
256: 9000 0a36 bgtu 0x48c
25a: 9000 0a32 bgtu 0x48c
25e: 9000 0a2e bgtu 0x48c
262: 9000 0a2a bgtu 0x48c
266: 9000 0a26 bgtu 0x48c
26a: 9000 0a23 bgtul 0x48c
...
46e: 340f bgtu! 0x48c
470: 340e bgtu! 0x48c
472: 340d bgtu! 0x48c
474: 340c bgtu! 0x48c
476: 9000 0816 bgtu 0x48c
47a: 9000 0812 bgtu 0x48c
47e: 3407 bgtu! 0x48c
480: 9000 080c bgtu 0x48c
484: 9000 0808 bgtu 0x48c
488: 9000 0805 bgtul 0x48c
...
68c: 0000 nop!
68e: 3500 bgtu! 0x48e
690: 93ff 09fe bgtu 0x48e
694: 9000 0a06 bgtu 0x89a
698: 9000 0a02 bgtu 0x89a
...
89c: 0000 nop!
89e: 3600 bleu! 0x89e
8a0: 37ff bleu! 0x89e
8a2: 37fe bleu! 0x89e
8a4: 37fd bleu! 0x89e
8a6: 93ff 0ff8 bleu 0x89e
8aa: 93ff 0ff4 bleu 0x89e
8ae: 37f8 bleu! 0x89e
8b0: 93ff 0fee bleu 0x89e
8b4: 93ff 0fea bleu 0x89e
8b8: 93ff 0fe7 bleul 0x89e
...
abc: 93ff 0de2 bleu 0x89e
ac0: 93ff 0dde bleu 0x89e
ac4: 93ff 0dda bleu 0x89e
ac8: 93ff 0dd6 bleu 0x89e
acc: 93ff 0dd2 bleu 0x89e
ad0: 93ff 0dce bleu 0x89e
ad4: 93ff 0dca bleu 0x89e
ad8: 93ff 0dc6 bleu 0x89e
adc: 93ff 0dc2 bleu 0x89e
ae0: 93ff 0dbf bleul 0x89e
ae4: 9000 0e46 bleu 0xd2a
ae8: 9000 0e42 bleu 0xd2a
aec: 9000 0e3e bleu 0xd2a
af0: 9000 0e3a bleu 0xd2a
af4: 9000 0e36 bleu 0xd2a
af8: 9000 0e32 bleu 0xd2a
afc: 9000 0e2e bleu 0xd2a
b00: 9000 0e2a bleu 0xd2a
b04: 9000 0e26 bleu 0xd2a
b08: 9000 0e23 bleul 0xd2a
...
d0c: 360f bleu! 0xd2a
d0e: 360e bleu! 0xd2a
d10: 360d bleu! 0xd2a
d12: 360c bleu! 0xd2a
d14: 9000 0c16 bleu 0xd2a
d18: 9000 0c12 bleu 0xd2a
d1c: 3607 bleu! 0xd2a
d1e: 9000 0c0c bleu 0xd2a
d22: 9000 0c08 bleu 0xd2a
d26: 9000 0c05 bleul 0xd2a
...
f2a: 0000 nop!
f2c: 3700 bleu! 0xd2c
f2e: 93ff 0dfe bleu 0xd2c
f32: 9000 0e06 bleu 0x1138
f36: 9000 0e02 bleu 0x1138
...
113a: 0000 nop!
113c: 3800 beq! 0x113c
113e: 39ff beq! 0x113c
1140: 39fe beq! 0x113c
1142: 39fd beq! 0x113c
1144: 93ff 13f8 beq 0x113c
1148: 93ff 13f4 beq 0x113c
114c: 39f8 beq! 0x113c
114e: 93ff 13ee beq 0x113c
1152: 93ff 13ea beq 0x113c
1156: 93ff 13e7 beql 0x113c
...
135a: 93ff 11e2 beq 0x113c
135e: 93ff 11de beq 0x113c
1362: 93ff 11da beq 0x113c
1366: 93ff 11d6 beq 0x113c
136a: 93ff 11d2 beq 0x113c
136e: 93ff 11ce beq 0x113c
1372: 93ff 11ca beq 0x113c
1376: 93ff 11c6 beq 0x113c
137a: 93ff 11c2 beq 0x113c
137e: 93ff 11bf beql 0x113c
1382: 9000 1246 beq 0x15c8
1386: 9000 1242 beq 0x15c8
138a: 9000 123e beq 0x15c8
138e: 9000 123a beq 0x15c8
1392: 9000 1236 beq 0x15c8
1396: 9000 1232 beq 0x15c8
139a: 9000 122e beq 0x15c8
139e: 9000 122a beq 0x15c8
13a2: 9000 1226 beq 0x15c8
13a6: 9000 1223 beql 0x15c8
...
15aa: 380f beq! 0x15c8
15ac: 380e beq! 0x15c8
15ae: 380d beq! 0x15c8
15b0: 380c beq! 0x15c8
15b2: 9000 1016 beq 0x15c8
15b6: 9000 1012 beq 0x15c8
15ba: 3807 beq! 0x15c8
15bc: 9000 100c beq 0x15c8
15c0: 9000 1008 beq 0x15c8
15c4: 9000 1005 beql 0x15c8
...
17c8: 0000 nop!
17ca: 3900 beq! 0x15ca
17cc: 93ff 11fe beq 0x15ca
17d0: 9000 1206 beq 0x19d6
17d4: 9000 1202 beq 0x19d6
...
19d8: 0000 nop!
19da: 3a00 bne! 0x19da
19dc: 3bff bne! 0x19da
19de: 3bfe bne! 0x19da
19e0: 3bfd bne! 0x19da
19e2: 93ff 17f8 bne 0x19da
19e6: 93ff 17f4 bne 0x19da
19ea: 3bf8 bne! 0x19da
19ec: 93ff 17ee bne 0x19da
19f0: 93ff 17ea bne 0x19da
19f4: 93ff 17e7 bnel 0x19da
...
1bf8: 93ff 15e2 bne 0x19da
1bfc: 93ff 15de bne 0x19da
1c00: 93ff 15da bne 0x19da
1c04: 93ff 15d6 bne 0x19da
1c08: 93ff 15d2 bne 0x19da
1c0c: 93ff 15ce bne 0x19da
1c10: 93ff 15ca bne 0x19da
1c14: 93ff 15c6 bne 0x19da
1c18: 93ff 15c2 bne 0x19da
1c1c: 93ff 15bf bnel 0x19da
1c20: 9000 1646 bne 0x1e66
1c24: 9000 1642 bne 0x1e66
1c28: 9000 163e bne 0x1e66
1c2c: 9000 163a bne 0x1e66
1c30: 9000 1636 bne 0x1e66
1c34: 9000 1632 bne 0x1e66
1c38: 9000 162e bne 0x1e66
1c3c: 9000 162a bne 0x1e66
1c40: 9000 1626 bne 0x1e66
1c44: 9000 1623 bnel 0x1e66
...
1e48: 3a0f bne! 0x1e66
1e4a: 3a0e bne! 0x1e66
1e4c: 3a0d bne! 0x1e66
1e4e: 3a0c bne! 0x1e66
1e50: 9000 1416 bne 0x1e66
1e54: 9000 1412 bne 0x1e66
1e58: 3a07 bne! 0x1e66
1e5a: 9000 140c bne 0x1e66
1e5e: 9000 1408 bne 0x1e66
1e62: 9000 1405 bnel 0x1e66
...
2066: 0000 nop!
2068: 3b00 bne! 0x1e68
206a: 93ff 15fe bne 0x1e68
206e: 9000 1606 bne 0x2274
2072: 9000 1602 bne 0x2274
...
2276: 0000 nop!
2278: 3c00 bgt! 0x2278
227a: 3dff bgt! 0x2278
227c: 3dfe bgt! 0x2278
227e: 3dfd bgt! 0x2278
2280: 93ff 1bf8 bgt 0x2278
2284: 93ff 1bf4 bgt 0x2278
2288: 3df8 bgt! 0x2278
228a: 93ff 1bee bgt 0x2278
228e: 93ff 1bea bgt 0x2278
2292: 93ff 1be7 bgtl 0x2278
...
2496: 93ff 19e2 bgt 0x2278
249a: 93ff 19de bgt 0x2278
249e: 93ff 19da bgt 0x2278
24a2: 93ff 19d6 bgt 0x2278
24a6: 93ff 19d2 bgt 0x2278
24aa: 93ff 19ce bgt 0x2278
24ae: 93ff 19ca bgt 0x2278
24b2: 93ff 19c6 bgt 0x2278
24b6: 93ff 19c2 bgt 0x2278
24ba: 93ff 19bf bgtl 0x2278
24be: 9000 1a46 bgt 0x2704
24c2: 9000 1a42 bgt 0x2704
24c6: 9000 1a3e bgt 0x2704
24ca: 9000 1a3a bgt 0x2704
24ce: 9000 1a36 bgt 0x2704
24d2: 9000 1a32 bgt 0x2704
24d6: 9000 1a2e bgt 0x2704
24da: 9000 1a2a bgt 0x2704
24de: 9000 1a26 bgt 0x2704
24e2: 9000 1a23 bgtl 0x2704
...
26e6: 3c0f bgt! 0x2704
26e8: 3c0e bgt! 0x2704
26ea: 3c0d bgt! 0x2704
26ec: 3c0c bgt! 0x2704
26ee: 9000 1816 bgt 0x2704
26f2: 9000 1812 bgt 0x2704
26f6: 3c07 bgt! 0x2704
26f8: 9000 180c bgt 0x2704
26fc: 9000 1808 bgt 0x2704
2700: 9000 1805 bgtl 0x2704
...
2904: 0000 nop!
2906: 3d00 bgt! 0x2706
2908: 93ff 19fe bgt 0x2706
290c: 9000 1a06 bgt 0x2b12
2910: 9000 1a02 bgt 0x2b12
...
2b14: 0000 nop!
2b16: 3e00 ble! 0x2b16
2b18: 3fff ble! 0x2b16
2b1a: 3ffe ble! 0x2b16
2b1c: 3ffd ble! 0x2b16
2b1e: 93ff 1ff8 ble 0x2b16
2b22: 93ff 1ff4 ble 0x2b16
2b26: 3ff8 ble! 0x2b16
2b28: 93ff 1fee ble 0x2b16
2b2c: 93ff 1fea ble 0x2b16
2b30: 93ff 1fe7 blel 0x2b16
...
2d34: 93ff 1de2 ble 0x2b16
2d38: 93ff 1dde ble 0x2b16
2d3c: 93ff 1dda ble 0x2b16
2d40: 93ff 1dd6 ble 0x2b16
2d44: 93ff 1dd2 ble 0x2b16
2d48: 93ff 1dce ble 0x2b16
2d4c: 93ff 1dca ble 0x2b16
2d50: 93ff 1dc6 ble 0x2b16
2d54: 93ff 1dc2 ble 0x2b16
2d58: 93ff 1dbf blel 0x2b16
2d5c: 9000 1e46 ble 0x2fa2
2d60: 9000 1e42 ble 0x2fa2
2d64: 9000 1e3e ble 0x2fa2
2d68: 9000 1e3a ble 0x2fa2
2d6c: 9000 1e36 ble 0x2fa2
2d70: 9000 1e32 ble 0x2fa2
2d74: 9000 1e2e ble 0x2fa2
2d78: 9000 1e2a ble 0x2fa2
2d7c: 9000 1e26 ble 0x2fa2
2d80: 9000 1e23 blel 0x2fa2
...
2f84: 3e0f ble! 0x2fa2
2f86: 3e0e ble! 0x2fa2
2f88: 3e0d ble! 0x2fa2
2f8a: 3e0c ble! 0x2fa2
2f8c: 9000 1c16 ble 0x2fa2
2f90: 9000 1c12 ble 0x2fa2
2f94: 3e07 ble! 0x2fa2
2f96: 9000 1c0c ble 0x2fa2
2f9a: 9000 1c08 ble 0x2fa2
2f9e: 9000 1c05 blel 0x2fa2
...
31a2: 0000 nop!
31a4: 3f00 ble! 0x2fa4
31a6: 93ff 1dfe ble 0x2fa4
31aa: 9000 1e06 ble 0x33b0
31ae: 9000 1e02 ble 0x33b0
...
33b2: 0000 nop!
33b4: 3200 bcnz! 0x33b4
33b6: 33ff bcnz! 0x33b4
33b8: 33fe bcnz! 0x33b4
33ba: 33fd bcnz! 0x33b4
33bc: 93ff 3bf8 bcnz 0x33b4
33c0: 93ff 3bf4 bcnz 0x33b4
33c4: 33f8 bcnz! 0x33b4
33c6: 93ff 3bee bcnz 0x33b4
33ca: 93ff 3bea bcnz 0x33b4
33ce: 93ff 3be7 bcnzl 0x33b4
...
35d2: 93ff 39e2 bcnz 0x33b4
35d6: 93ff 39de bcnz 0x33b4
35da: 93ff 39da bcnz 0x33b4
35de: 93ff 39d6 bcnz 0x33b4
35e2: 93ff 39d2 bcnz 0x33b4
35e6: 93ff 39ce bcnz 0x33b4
35ea: 93ff 39ca bcnz 0x33b4
35ee: 93ff 39c6 bcnz 0x33b4
35f2: 93ff 39c2 bcnz 0x33b4
35f6: 93ff 39bf bcnzl 0x33b4
35fa: 9000 3a46 bcnz 0x3840
35fe: 9000 3a42 bcnz 0x3840
3602: 9000 3a3e bcnz 0x3840
3606: 9000 3a3a bcnz 0x3840
360a: 9000 3a36 bcnz 0x3840
360e: 9000 3a32 bcnz 0x3840
3612: 9000 3a2e bcnz 0x3840
3616: 9000 3a2a bcnz 0x3840
361a: 9000 3a26 bcnz 0x3840
361e: 9000 3a23 bcnzl 0x3840
...
3822: 320f bcnz! 0x3840
3824: 320e bcnz! 0x3840
3826: 320d bcnz! 0x3840
3828: 320c bcnz! 0x3840
382a: 9000 3816 bcnz 0x3840
382e: 9000 3812 bcnz 0x3840
3832: 3207 bcnz! 0x3840
3834: 9000 380c bcnz 0x3840
3838: 9000 3808 bcnz 0x3840
383c: 9000 3805 bcnzl 0x3840
...
3a40: 0000 nop!
3a42: 3300 bcnz! 0x3842
3a44: 93ff 39fe bcnz 0x3842
3a48: 9000 3a06 bcnz 0x3c4e
3a4c: 9000 3a02 bcnz 0x3c4e
...
3c50: 0000 nop!
3c52: 3000 b! 0x3c52
3c54: 31ff b! 0x3c52
3c56: 31fe b! 0x3c52
3c58: 31fd b! 0x3c52
3c5a: 93ff 3ff8 b 0x3c52
3c5e: 93ff 3ff4 b 0x3c52
3c62: 31f8 b! 0x3c52
3c64: 93ff 3fee b 0x3c52
3c68: 93ff 3fea b 0x3c52
3c6c: 93ff 3fe7 bl 0x3c52
...
3e70: 93ff 3de2 b 0x3c52
3e74: 93ff 3dde b 0x3c52
3e78: 93ff 3dda b 0x3c52
3e7c: 93ff 3dd6 b 0x3c52
3e80: 93ff 3dd2 b 0x3c52
3e84: 93ff 3dce b 0x3c52
3e88: 93ff 3dca b 0x3c52
3e8c: 93ff 3dc6 b 0x3c52
3e90: 93ff 3dc2 b 0x3c52
3e94: 93ff 3dbf bl 0x3c52
3e98: 9000 3e46 b 0x40de
3e9c: 9000 3e42 b 0x40de
3ea0: 9000 3e3e b 0x40de
3ea4: 9000 3e3a b 0x40de
3ea8: 9000 3e36 b 0x40de
3eac: 9000 3e32 b 0x40de
3eb0: 9000 3e2e b 0x40de
3eb4: 9000 3e2a b 0x40de
3eb8: 9000 3e26 b 0x40de
3ebc: 9000 3e23 bl 0x40de
...
40c0: 300f b! 0x40de
40c2: 300e b! 0x40de
40c4: 300d b! 0x40de
40c6: 300c b! 0x40de
40c8: 9000 3c16 b 0x40de
40cc: 9000 3c12 b 0x40de
40d0: 3007 b! 0x40de
40d2: 9000 3c0c b 0x40de
40d6: 9000 3c08 b 0x40de
40da: 9000 3c05 bl 0x40de
...
42de: 0000 nop!
42e0: 3100 b! 0x40e0
42e2: 93ff 3dfe b 0x40e0
42e6: 9000 3e06 b 0x44ec
42ea: 9000 3e02 b 0x44ec
...
44ee: 0000 nop!
44f0: 0080 br! r0
44f2: 008f br! r15
44f4: 0080 br! r0
44f6: 0080 br! r0
44f8: 0080 br! r0
44fa: 0080 br! r0
44fc: 0080 br! r0
44fe: 0080 br! r0
4500: 0080 br! r0
4502: 0080 br! r0
4504: 0090 br! r16
4506: 009f br! r31
4508: 00a0 brl! r0
450a: 00af brl! r15
450c: 00a0 brl! r0
450e: 00a0 brl! r0
4510: 00a0 brl! r0
4512: 00a0 brl! r0
4514: 00a0 brl! r0
4516: 00a0 brl! r0
4518: 00a0 brl! r0
451a: 00a0 brl! r0
451c: 00b0 brl! r16
451e: 00bf brl! r31
4520: 8000 3c4c bcmpeq r0, r15 ,0x4520
4524: 83ef 43cc bcmpeq r15, r16 ,0x4520
4528: 83ef 7f4c bcmpeq r15, r31 ,0x4520
452c: 83f0 7ecc bcmpeq r16, r31 ,0x4520
...
4730: 440f cmp! r0, r15
4732: 93ff 11ee beq 0x4520
4736: 45f0 cmp! r15, r16
4738: 93ff 11e8 beq 0x4520
473c: 45ff cmp! r15, r31
473e: 93ff 11e2 beq 0x4520
4742: 461f cmp! r16, r31
4744: 93ff 11dc beq 0x4520
4748: 440f cmp! r0, r15
474a: 9000 1226 beq 0x4970
474e: 45f0 cmp! r15, r16
4750: 9000 1220 beq 0x4970
4754: 45ff cmp! r15, r31
4756: 9000 121a beq 0x4970
475a: 461f cmp! r16, r31
475c: 9000 1214 beq 0x4970
...
4960: 8000 3e4c bcmpeq r0, r15 ,0x4970
4964: 800f 41cc bcmpeq r15, r16 ,0x4970
4968: 800f 7d4c bcmpeq r15, r31 ,0x4970
496c: 8010 7ccc bcmpeq r16, r31 ,0x4970
...
4b70: 0000 nop!
4b72: 8200 3c4c bcmpeq r0, r15 ,0x4972
4b76: 460f cmp! r16, r15
4b78: 93ff 11fa beq 0x4972
4b7c: 440f cmp! r0, r15
4b7e: 9000 1208 beq 0x4d86
4b82: 460f cmp! r16, r15
4b84: 9000 1202 beq 0x4d86
...
4d88: 8000 3c4e bcmpne r0, r15 ,0x4d88
4d8c: 83ef 43ce bcmpne r15, r16 ,0x4d88
4d90: 83ef 7f4e bcmpne r15, r31 ,0x4d88
4d94: 83f0 7ece bcmpne r16, r31 ,0x4d88
...
4f98: 440f cmp! r0, r15
4f9a: 93ff 15ee bne 0x4d88
4f9e: 45f0 cmp! r15, r16
4fa0: 93ff 15e8 bne 0x4d88
4fa4: 45ff cmp! r15, r31
4fa6: 93ff 15e2 bne 0x4d88
4faa: 461f cmp! r16, r31
4fac: 93ff 15dc bne 0x4d88
4fb0: 440f cmp! r0, r15
4fb2: 9000 1626 bne 0x51d8
4fb6: 45f0 cmp! r15, r16
4fb8: 9000 1620 bne 0x51d8
4fbc: 45ff cmp! r15, r31
4fbe: 9000 161a bne 0x51d8
4fc2: 461f cmp! r16, r31
4fc4: 9000 1614 bne 0x51d8
...
51c8: 8000 3e4e bcmpne r0, r15 ,0x51d8
51cc: 800f 41ce bcmpne r15, r16 ,0x51d8
51d0: 800f 7d4e bcmpne r15, r31 ,0x51d8
51d4: 8010 7cce bcmpne r16, r31 ,0x51d8
...
53d8: 0000 nop!
53da: 8200 3c4e bcmpne r0, r15 ,0x51da
53de: 460f cmp! r16, r15
53e0: 93ff 15fa bne 0x51da
53e4: 440f cmp! r0, r15
53e6: 9000 1608 bne 0x55ee
53ea: 460f cmp! r16, r15
53ec: 9000 1602 bne 0x55ee
...
55f0: 8000 004c bcmpeqz r0, 0x55f0
55f4: 83ef 03cc bcmpeqz r15, 0x55f0
55f8: 83f0 034c bcmpeqz r16, 0x55f0
55fc: 83ff 02cc bcmpeqz r31, 0x55f0
...
5800: 6000 cmpi! r0, 0
5802: 93ff 11ee beq 0x55f0
5806: 61e0 cmpi! r15, 0
5808: 93ff 11e8 beq 0x55f0
580c: 6200 cmpi! r16, 0
580e: 93ff 11e2 beq 0x55f0
5812: 63e0 cmpi! r31, 0
5814: 93ff 11dc beq 0x55f0
5818: 6000 cmpi! r0, 0
581a: 9000 1226 beq 0x5a40
581e: 61e0 cmpi! r15, 0
5820: 9000 1220 beq 0x5a40
5824: 6200 cmpi! r16, 0
5826: 9000 121a beq 0x5a40
582a: 63e0 cmpi! r31, 0
582c: 9000 1214 beq 0x5a40
...
5a30: 8000 024c bcmpeqz r0, 0x5a40
5a34: 800f 01cc bcmpeqz r15, 0x5a40
5a38: 8010 014c bcmpeqz r16, 0x5a40
5a3c: 801f 00cc bcmpeqz r31, 0x5a40
...
5c40: 0000 nop!
5c42: 8200 004c bcmpeqz r0, 0x5a42
5c46: 6200 cmpi! r16, 0
5c48: 93ff 11fa beq 0x5a42
5c4c: 6000 cmpi! r0, 0
5c4e: 9000 1208 beq 0x5e56
5c52: 6200 cmpi! r16, 0
5c54: 9000 1202 beq 0x5e56
...
5e58: 8000 004e bcmpnez r0, 0x5e58
5e5c: 83ef 03ce bcmpnez r15, 0x5e58
5e60: 83f0 034e bcmpnez r16, 0x5e58
5e64: 83ff 02ce bcmpnez r31, 0x5e58
...
6068: 6000 cmpi! r0, 0
606a: 93ff 15ee bne 0x5e58
606e: 61e0 cmpi! r15, 0
6070: 93ff 15e8 bne 0x5e58
6074: 6200 cmpi! r16, 0
6076: 93ff 15e2 bne 0x5e58
607a: 63e0 cmpi! r31, 0
607c: 93ff 15dc bne 0x5e58
6080: 6000 cmpi! r0, 0
6082: 9000 1626 bne 0x62a8
6086: 61e0 cmpi! r15, 0
6088: 9000 1620 bne 0x62a8
608c: 6200 cmpi! r16, 0
608e: 9000 161a bne 0x62a8
6092: 63e0 cmpi! r31, 0
6094: 9000 1614 bne 0x62a8
...
6298: 8000 024e bcmpnez r0, 0x62a8
629c: 800f 01ce bcmpnez r15, 0x62a8
62a0: 8010 014e bcmpnez r16, 0x62a8
62a4: 801f 00ce bcmpnez r31, 0x62a8
...
64a8: 0000 nop!
64aa: 8200 004e bcmpnez r0, 0x62aa
64ae: 6200 cmpi! r16, 0
64b0: 93ff 15fa bne 0x62aa
64b4: 6000 cmpi! r0, 0
64b6: 9000 1608 bne 0x66be
64ba: 6200 cmpi! r16, 0
64bc: 9000 1602 bne 0x66be
...
#pass

181
gas/testsuite/gas/score/branch_32.s Normal file
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/*
* tests for branch instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.macro _b_op_pattern insn insn1
.balign 2
/*
* for local label 1, assembler should NOT alter instructions before .skip;
* but it SHOULD alter instructions afte it.
*/
1:
insn_16 "\insn! 1b"
tran_16_32 "\insn! 1b", "\insn 1b"
insn_16 "\insn1 1b"
.skip 512
insn_16 "\insn! 1b"
tran_16_32 "\insn! 1b", "\insn 1b"
insn_16 "\insn1 1b"
/*
* for local label 2, assembler SHOULD alter instructions before .skip;
* but it should NOT alter instructions after it.
*/
insn_16 "\insn! 2f"
tran_16_32 "\insn! 2f", "\insn 2f"
insn_16 "\insn1 2f"
.skip 511
insn_16 "\insn! 2f"
tran_16_32 "\insn! 2f", "\insn 2f"
insn_16 "\insn1 2f"
2:
nop!
/* tests for boundary */
3:
.skip 512
insn_16 "\insn! 3b"
insn_16 "\insn! 3b"
insn_16 "\insn! 4f"
insn_16 "\insn! 4f"
.skip 511
4:
nop!
.endm
.macro _br_op_pattern insn
.balign 2
insn_32 "\insn r0"
insn_32 "\insn r15"
tran_16_32 "\insn! r0", "\insn r0"
/* shouldn't alter */
insn_32 "\insn r16"
insn_32 "\insn r31"
.endm
.macro _bcmp_op_pattern1 insn
.balign 2
/* as will give "Using temp register(r1)" warning if you using r1 */
/*
* for local label 1, assembler should NOT alter instructions before .skip;
* but it SHOULD alter instructions afte it.
*/
1:
insn_32 "\insn r0, r15, 1b"
insn_32 "\insn r15, r16, 1b"
insn_32 "\insn r15, r31, 1b"
insn_32 "\insn r16, r31, 1b"
.skip 512
insn_32 "\insn r0, r15, 1b"
insn_32 "\insn r15, r16, 1b"
insn_32 "\insn r15, r31, 1b"
insn_32 "\insn r16, r31, 1b"
/*
* for local label 2, assembler SHOULD alter instructions before .skip;
* but it should NOT alter instructions after it.
*/
insn_32 "\insn r0, r15, 2f"
insn_32 "\insn r15, r16, 2f"
insn_32 "\insn r15, r31, 2f"
insn_32 "\insn r16, r31, 2f"
.skip 511
insn_32 "\insn r0, r15, 2f"
insn_32 "\insn r15, r16, 2f"
insn_32 "\insn r15, r31, 2f"
insn_32 "\insn r16, r31, 2f"
2:
nop!
/* tests for boundary */
3:
.skip 512
insn_32 "\insn r0, r15, 3b"
insn_32 "\insn r16, r15, 3b"
insn_32 "\insn r0, r15, 4f"
insn_32 "\insn r16, r15, 4f"
.skip 511
4:
.endm
.macro _bcmp_op_pattern2 insn
.balign 2
/* as will give "Using temp register(r1)" warning if you using r1 */
/*
* for local label 1, assembler should NOT alter instructions before .skip;
* but it SHOULD alter instructions afte it.
*/
1:
insn_32 "\insn r0, 1b"
insn_32 "\insn r15, 1b"
insn_32 "\insn r16, 1b"
insn_32 "\insn r31, 1b"
.skip 512
insn_32 "\insn r0, 1b"
insn_32 "\insn r15, 1b"
insn_32 "\insn r16, 1b"
insn_32 "\insn r31, 1b"
/*
* for local label 2, assembler SHOULD alter instructions before .skip;
* but it should NOT alter instructions after it.
*/
insn_32 "\insn r0, 2f"
insn_32 "\insn r15, 2f"
insn_32 "\insn r16, 2f"
insn_32 "\insn r31, 2f"
.skip 511
insn_32 "\insn r0, 2f"
insn_32 "\insn r15, 2f"
insn_32 "\insn r16, 2f"
insn_32 "\insn r31, 2f"
2:
nop!
/* tests for boundary */
3:
.skip 512
insn_32 "\insn r0, 3b"
insn_32 "\insn r16, 3b"
insn_32 "\insn r0, 4f"
insn_32 "\insn r16, 4f"
.skip 511
4:
.endm
.text
/* b Disp19 <-> b! Disp9 */
_b_op_pattern "bgtu", "bgtul"
_b_op_pattern "bleu", "bleul"
_b_op_pattern "beq", "beql"
_b_op_pattern "bne", "bnel"
_b_op_pattern "bgt", "bgtl"
_b_op_pattern "ble", "blel"
_b_op_pattern "bcnz", "bcnzl"
_b_op_pattern "b", "bl"
/* br rD <-> br! rD */
_br_op_pattern "br"
_br_op_pattern "brl"
/* bcmpeq/bcmpne rA,rB,Disp9 -> cmp/cmp! rA, rB; beq/bne Disp19 */
_bcmp_op_pattern1 "bcmpeq"
_bcmp_op_pattern1 "bcmpne"
/* bcmpeqz/bcmpnez rA,Disp9 -> cmpi! rA, 0; beq/bne Disp19 */
_bcmp_op_pattern2 "bcmpeqz"
_bcmp_op_pattern2 "bcmpnez"

12
gas/testsuite/gas/score/cmp_32-lt.d Normal file
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#as: -march=score3 -I${srcdir}/${subdir} -EL
#objdump: -s
#source: cmp_32.s
.*: file format elf32-littlescore
Contents of section .text:
0000 0f440f44 0f440f44 0f440f44 0f440f44 .*
0010 0f441044 00461f46 10600f60 f061ef61 .*
0020 10601060 10601060 10601060 10601060 .*
0030 1062ef63 0b84df7f e8852100 08862100 .*
#pass

39
gas/testsuite/gas/score/cmp_32.d Normal file
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#as: -march=score3 -I${srcdir}/${subdir}
#objdump: -d
#source: cmp_32.s
.*: file format .*
Disassembly of section .text:
00000000 <.text>:
0: 440f cmp! r0, r15
2: 440f cmp! r0, r15
4: 440f cmp! r0, r15
6: 440f cmp! r0, r15
8: 440f cmp! r0, r15
a: 440f cmp! r0, r15
c: 440f cmp! r0, r15
e: 440f cmp! r0, r15
10: 440f cmp! r0, r15
12: 4410 cmp! r0, r16
14: 4600 cmp! r16, r0
16: 461f cmp! r16, r31
18: 6010 cmpi! r0, -16
1a: 600f cmpi! r0, 15
1c: 61f0 cmpi! r15, -16
1e: 61ef cmpi! r15, 15
20: 6010 cmpi! r0, -16
22: 6010 cmpi! r0, -16
24: 6010 cmpi! r0, -16
26: 6010 cmpi! r0, -16
28: 6010 cmpi! r0, -16
2a: 6010 cmpi! r0, -16
2c: 6010 cmpi! r0, -16
2e: 6010 cmpi! r0, -16
30: 6210 cmpi! r16, -16
32: 63ef cmpi! r31, 15
34: 840b 7fdf cmpi.c r0, -17
38: 85e8 0021 cmpi.c r15, 16
3c: 8608 0021 cmpi.c r16, 16
#pass

33
gas/testsuite/gas/score/cmp_32.s Normal file
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/*
* tests for compare instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.text
/* cmp.c rA,rB -> cmp! rA,rB */
insn_32 "cmp.c r0, r15"
tran_16_32 "cmp! r0, r15", "cmp.c r0, r15"
/* shouln't alter */
insn_32 "cmp.c r0, r16"
insn_32 "cmp.c r16, r0"
insn_32 "cmp.c r16, r31"
/* cmpi.c rD,SImm16 -> cmpi! rD,SImm5 */
insn_32 "cmpi.c r0, -16"
insn_32 "cmpi.c r0, 15"
insn_32 "cmpi.c r15, -16"
insn_32 "cmpi.c r15, 15"
tran_16_32 "cmpi! r0, -16", "cmpi.c r0, -16"
/* shouldn't alter */
insn_32 "cmpi.c r16, -16"
insn_32 "cmpi.c r31, 15"
insn_32 "cmpi.c r0, -17"
insn_32 "cmpi.c r15, 16"
insn_32 "cmpi.c r16, 16"

19
gas/testsuite/gas/score/load_store_32-lt.d Normal file
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#as: -march=score3 -I${srcdir}/${subdir} -EL
#objdump: -s
#source: load_store_32.s
.*: file format elf32-littlescore
Contents of section .text:
0000 0010001f e010e01f 1f101f1f ff10ff1f .*
0010 1f101f10 1f101f10 1f101f10 1f101f10 .*
0020 00c20000 08c07c00 08c27c00 07c0ff7f .*
0030 07c08000 0020002f e020e02f 1f201f2f .*
0040 ff20ff2f 1f201f20 1f201f20 1f201f20 .*
0050 1f201f20 00d20000 08d07c00 08d27c00 .*
0060 07d0ff7f 07d08000 0064e065 1f64ff65 .*
0070 00640064 00640064 00640064 00640064 .*
0080 00661b84 fe7f1884 40001886 40004200 .*
0090 4f005000 829c2000 809ce07f 62006f00 .*
00a0 7000828c e47f808c 24000000 .*
#pass

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gas/testsuite/gas/score/load_store_32.d Normal file
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#as: -march=score3 -I${srcdir}/${subdir}
#objdump: -d
#source: load_store_32.s
.*: file format .*
Disassembly of section .text:
00000000 <.text>:
0: 1000 lw! r0, \[r0,0\]
2: 1f00 lw! r15, \[r0,0\]
4: 10e0 lw! r0, \[r7,0\]
6: 1fe0 lw! r15, \[r7,0\]
8: 101f lw! r0, \[r0,124\]
a: 1f1f lw! r15, \[r0,124\]
c: 10ff lw! r0, \[r7,124\]
e: 1fff lw! r15, \[r7,124\]
10: 101f lw! r0, \[r0,124\]
12: 101f lw! r0, \[r0,124\]
14: 101f lw! r0, \[r0,124\]
16: 101f lw! r0, \[r0,124\]
18: 101f lw! r0, \[r0,124\]
1a: 101f lw! r0, \[r0,124\]
1c: 101f lw! r0, \[r0,124\]
1e: 101f lw! r0, \[r0,124\]
20: c200 0000 lw r16, \[r0, 0\]
24: c008 007c lw r0, \[r8, 124\]
28: c208 007c lw r16, \[r8, 124\]
2c: c007 7fff lw r0, \[r7, -1\]
30: c007 0080 lw r0, \[r7, 128\]
34: 2000 sw! r0, \[r0,0\]
36: 2f00 sw! r15, \[r0,0\]
38: 20e0 sw! r0, \[r7,0\]
3a: 2fe0 sw! r15, \[r7,0\]
3c: 201f sw! r0, \[r0,124\]
3e: 2f1f sw! r15, \[r0,124\]
40: 20ff sw! r0, \[r7,124\]
42: 2fff sw! r15, \[r7,124\]
44: 201f sw! r0, \[r0,124\]
46: 201f sw! r0, \[r0,124\]
48: 201f sw! r0, \[r0,124\]
4a: 201f sw! r0, \[r0,124\]
4c: 201f sw! r0, \[r0,124\]
4e: 201f sw! r0, \[r0,124\]
50: 201f sw! r0, \[r0,124\]
52: 201f sw! r0, \[r0,124\]
54: d200 0000 sw r16, \[r0, 0\]
58: d008 007c sw r0, \[r8, 124\]
5c: d208 007c sw r16, \[r8, 124\]
60: d007 7fff sw r0, \[r7, -1\]
64: d007 0080 sw r0, \[r7, 128\]
68: 6400 ldiu! r0, 0
6a: 65e0 ldiu! r15, 0
6c: 641f ldiu! r0, 31
6e: 65ff ldiu! r15, 31
70: 6400 ldiu! r0, 0
72: 6400 ldiu! r0, 0
74: 6400 ldiu! r0, 0
76: 6400 ldiu! r0, 0
78: 6400 ldiu! r0, 0
7a: 6400 ldiu! r0, 0
7c: 6400 ldiu! r0, 0
7e: 6400 ldiu! r0, 0
80: 6600 ldiu! r16, 0
82: 841b 7ffe ldi r0, 0xffff\(-1\)
86: 8418 0040 ldi r0, 0x20\(32\)
8a: 8618 0040 ldi r16, 0x20\(32\)
8e: 0042 pop! r2
90: 004f pop! r15
92: 0050 pop! r16
94: 9c82 0020 lw r4, \[r2\]\+, 4
98: 9c80 7fe0 lw r4, \[r0\]\+, -4
9c: 0062 push! r2
9e: 006f push! r15
a0: 0070 push! r16
a2: 8c82 7fe4 sw r4, \[r2, -4\]\+
a6: 8c80 0024 sw r4, \[r0, 4\]\+
...
#pass

71
gas/testsuite/gas/score/load_store_32.s Normal file
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/*
* tests for load/store instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.macro _ls_op_pattern insn
.balign 2
insn_32 "\insn r0, [r0,0]"
insn_32 "\insn r15, [r0,0]"
insn_32 "\insn r0, [r7,0]"
insn_32 "\insn r15, [r7,0]"
/* NOTE: offset MUST be word aligned */
insn_32 "\insn r0, [r0,124]"
insn_32 "\insn r15, [r0,124]"
insn_32 "\insn r0, [r7,124]"
insn_32 "\insn r15, [r7,124]"
tran_16_32 "\insn! r0,[r0,124]", "\insn r0,[r0,124]"
/* shouldn't alter */
insn_32 "\insn r16, [r0, 0]"
insn_32 "\insn r0, [r8, 124]"
insn_32 "\insn r16, [r8, 124]"
insn_32 "\insn r0, [r7, -1]"
insn_32 "\insn r0, [r7, 128]"
.endm
.text
/* lw/sw rD,[rA,SImm15] -> lw!/sw! rD,[rA,Imm5] */
_ls_op_pattern "lw"
_ls_op_pattern "sw"
/* ldi rD,SImm16 -> ldiu! rD,Imm6 */
.balign 2
insn_32 "ldi r0, 0"
insn_32 "ldi r15, 0"
insn_32 "ldi r0, 31"
insn_32 "ldi r15, 31"
tran_16_32 "ldiu! r0, 0", "ldi r0, 0"
/* shouldn't alter */
insn_32 "ldi r16, 0"
insn_32 "ldi r0, -1"
insn_32 "ldi r0, 32"
insn_32 "ldi r16, 32"
/*
* lw rD,[rA]+,SImm12 -> pop! rD
*
* r0: stack pointer(sp)
*/
insn_32 "lw r2, [r0]+, 4"
insn_32 "lw r15, [r0]+, 4"
/* shouldn't alter */
insn_32 "lw r16, [r0]+, 4"
insn_32 "lw r4, [r2]+, 4"
insn_32 "lw r4, [r0]+, -4"
/* sw rD,[rA,SImm12]+ -> push! rD */
insn_32 "sw r2, [r0, -4]+"
insn_32 "sw r15, [r0, -4]+"
/* shouldn't alter */
insn_32 "sw r16, [r0, -4]+"
insn_32 "sw r4, [r2, -4]+"
insn_32 "sw r4, [r0, 4]+"

13
gas/testsuite/gas/score/logical_32-lt.d Normal file
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#as: -march=score3 -I${srcdir}/${subdir} -EL
#objdump: -s
#source: logical_32.s
.*: file format elf32-littlescore
Contents of section .text:
0000 0f4b0f4b 0f4b0f4b 0f4b0f4b 0f4b0f4b .*
0010 0f4b0080 213c0080 20401082 20001082 .*
0020 20440180 20080f4a 0f4a0f4a 0f4a0f4a .*
0030 0f4a0f4a 0f4a0f4a 0080233c 00802240 .*
0040 10822200 10822244 01802208 .*
#pass

38
gas/testsuite/gas/score/logical_32.d Normal file
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#as: -march=score3 -I${srcdir}/${subdir}
#objdump: -d
#source: logical_32.s
.*: file format .*
Disassembly of section .text:
00000000 <.text>:
0: 4b0f and! r0, r15
2: 4b0f and! r0, r15
4: 4b0f and! r0, r15
6: 4b0f and! r0, r15
8: 4b0f and! r0, r15
a: 4b0f and! r0, r15
c: 4b0f and! r0, r15
e: 4b0f and! r0, r15
10: 4b0f and! r0, r15
12: 8000 3c21 and.c r0, r0, r15
16: 8000 4020 and r0, r0, r16
1a: 8210 0020 and r16, r16, r0
1e: 8210 4420 and r16, r16, r17
22: 8001 0820 and r0, r1, r2
26: 4a0f or! r0, r15
28: 4a0f or! r0, r15
2a: 4a0f or! r0, r15
2c: 4a0f or! r0, r15
2e: 4a0f or! r0, r15
30: 4a0f or! r0, r15
32: 4a0f or! r0, r15
34: 4a0f or! r0, r15
36: 4a0f or! r0, r15
38: 8000 3c23 or.c r0, r0, r15
3c: 8000 4022 or r0, r0, r16
40: 8210 0022 or r16, r16, r0
44: 8210 4422 or r16, r16, r17
48: 8001 0822 or r0, r1, r2
#pass

26
gas/testsuite/gas/score/logical_32.s Normal file
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/*
* tests for logical instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.macro _logical_op_pattern insn insn1
insn_32 "\insn r0, r0, r15"
tran_16_32 "\insn! r0, r15", "\insn r0, r0, r15"
/* shouldn't alter */
.set r1
insn_32 "\insn1 r0, r0, r15"
insn_32 "\insn r0, r0, r16"
insn_32 "\insn r16, r16, r0"
insn_32 "\insn r16, r16, r17"
insn_32 "\insn r0, r1, r2"
.endm
.text
/* and/or rD,rA,rB -> and!/or! rD,rA */
_logical_op_pattern "and", "and.c"
_logical_op_pattern "or", "or.c"

10
gas/testsuite/gas/score/mv_32-lt.d Normal file
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#as: -march=score3 -I${srcdir}/${subdir} -EL
#objdump: -s
#source: mv_32.s
.*: file format elf32-littlescore
Contents of section .text:
0000 0f400f40 0f400f40 0f400f40 0f400f40 .*
0010 0f400f42 10401042 .*
#pass

22
gas/testsuite/gas/score/mv_32.d Normal file
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@ -0,0 +1,22 @@
#as: -march=score3 -I${srcdir}/${subdir}
#objdump: -d
#source: mv_32.s
.*: file format .*
Disassembly of section .text:
00000000 <.text>:
0: 400f mv! r0, r15
2: 400f mv! r0, r15
4: 400f mv! r0, r15
6: 400f mv! r0, r15
8: 400f mv! r0, r15
a: 400f mv! r0, r15
c: 400f mv! r0, r15
e: 400f mv! r0, r15
10: 400f mv! r0, r15
12: 420f mv! r16, r15
14: 4010 mv! r0, r16
16: 4210 mv! r16, r16
#pass

18
gas/testsuite/gas/score/mv_32.s Normal file
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/*
* tests for mv instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.text
/* mv rD,rA -> mv! rD,rA */
insn_32 "mv r0, r15"
tran_16_32 "mv! r0, r15", "mv r0, r15"
/* shouldn't alter */
insn_32 "mv r16, r15"
insn_32 "mv r0, r16"
insn_32 "mv r16, r16"

24
gas/testsuite/gas/score/relax_32.exp Normal file
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# tests for instruction relaxation
if [istarget score-*-*] then {
run_dump_test "arith_32"
run_dump_test "bit_32"
run_dump_test "branch_32"
run_dump_test "cmp_32"
run_dump_test "load_store_32"
run_dump_test "logical_32"
run_dump_test "mv_32"
run_dump_test "shift_32"
run_dump_test "syscontrol_32"
# tests for little endian
run_dump_test "arith_32-lt"
run_dump_test "bit_32-lt"
run_dump_test "branch_32-lt"
run_dump_test "cmp_32-lt"
run_dump_test "load_store_32-lt"
run_dump_test "logical_32-lt"
run_dump_test "mv_32-lt"
run_dump_test "shift_32-lt"
run_dump_test "syscontrol_32-lt"
}

32
gas/testsuite/gas/score/relaxation_macro.h Normal file
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/*
* macros for S+core 3 instruction relaxation
*
* partial copyed from testpatterns for S+core 7
*
* Author: libin
*/
.macro _tran insn1 insn2
.balign 2
.irp i1,"\insn1", "\insn2"
.irp i2,"\insn1", "\insn2"
\i1
\i2
.endr
.endr
.endm
/* insn32/insn16 may include special characters, for example, blank character */
.macro tran_16_32 insn16 insn32
_tran "\insn16", "\insn32"
.endm
.macro insn_16 insn16
.balign 2
\insn16
.endm
.macro insn_32 insn32
.balign 2
\insn32
.endm

13
gas/testsuite/gas/score/shift_32-lt.d Normal file
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#as: -march=score3 -I${srcdir}/${subdir} -EL
#objdump: -s
#source: shift_32.s
.*: file format elf32-littlescore
Contents of section .text:
0000 00581f58 e059ff59 00580058 00580058 .*
0010 00580058 00580058 00807100 02807000 .*
0020 10827000 005a1f5a e05bff5b 005a005a .*
0030 005a005a 005a005a 005a005a 00807500 .*
0040 02807400 10827400 .*
#pass

40
gas/testsuite/gas/score/shift_32.d Normal file
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#as: -march=score3 -I${srcdir}/${subdir}
#objdump: -d
#source: shift_32.s
.*: file format .*
Disassembly of section .text:
00000000 <.text>:
0: 5800 slli! r0, 0
2: 581f slli! r0, 31
4: 59e0 slli! r15, 0
6: 59ff slli! r15, 31
8: 5800 slli! r0, 0
a: 5800 slli! r0, 0
c: 5800 slli! r0, 0
e: 5800 slli! r0, 0
10: 5800 slli! r0, 0
12: 5800 slli! r0, 0
14: 5800 slli! r0, 0
16: 5800 slli! r0, 0
18: 8000 0071 slli.c r0, r0, 0
1c: 8002 0070 slli r0, r2, 0
20: 8210 0070 slli r16, r16, 0
24: 5a00 srli! r0, 0
26: 5a1f srli! r0, 31
28: 5be0 srli! r15, 0
2a: 5bff srli! r15, 31
2c: 5a00 srli! r0, 0
2e: 5a00 srli! r0, 0
30: 5a00 srli! r0, 0
32: 5a00 srli! r0, 0
34: 5a00 srli! r0, 0
36: 5a00 srli! r0, 0
38: 5a00 srli! r0, 0
3a: 5a00 srli! r0, 0
3c: 8000 0075 srli.c r0, r0, 0
40: 8002 0074 srli r0, r2, 0
44: 8210 0074 srli r16, r16, 0
#pass

26
gas/testsuite/gas/score/shift_32.s Normal file
View File

@ -0,0 +1,26 @@
/*
* tests for shift instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.macro _shift_op_pattern insn insn1
insn_32 "\insn r0, r0, 0"
insn_32 "\insn r0, r0, 31"
insn_32 "\insn r15, r15, 0"
insn_32 "\insn r15, r15, 31"
tran_16_32 "\insn! r0, 0", "\insn r0, r0, 0"
/* shouldn't alter */
insn_32 "\insn1 r0, r0, 0"
insn_32 "\insn r0, r2, 0"
insn_32 "\insn r16, r16, 0"
.endm
.text
/* slli/srli rD,rA,Imm5 -> slli!/srli! rD,Imm5 */
_shift_op_pattern "slli", "slli.c"
_shift_op_pattern "srli", "srli.c"

11
gas/testsuite/gas/score/syscontrol_32-lt.d Normal file
View File

@ -0,0 +1,11 @@
#as: -march=score3 -I${srcdir}/${subdir} -EL
#objdump: -s
#source: syscontrol_32.s
.*: file format elf32-littlescore
Contents of section .text:
0000 20003f00 20002000 20002000 20002000 .*
0010 20002000 00000000 00000000 00000000 .*
0020 00000000 00000000 .*
#pass

21
gas/testsuite/gas/score/syscontrol_32.d Normal file
View File

@ -0,0 +1,21 @@
#as: -march=score3 -I${srcdir}/${subdir}
#objdump: -d
#source: syscontrol_32.s
.*: file format .*
Disassembly of section .text:
00000000 <.text>:
0: 0020 sdbbp! 0
2: 003f sdbbp! 31
4: 0020 sdbbp! 0
6: 0020 sdbbp! 0
8: 0020 sdbbp! 0
a: 0020 sdbbp! 0
c: 0020 sdbbp! 0
e: 0020 sdbbp! 0
10: 0020 sdbbp! 0
12: 0020 sdbbp! 0
...
#pass

19
gas/testsuite/gas/score/syscontrol_32.s Normal file
View File

@ -0,0 +1,19 @@
/*
* tests for system control instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.text
/* sdbbp Imm5 -> sdbbp! Imm5 */
insn_32 "sdbbp 0"
insn_32 "sdbbp 31"
tran_16_32 "sdbbp! 0", "sdbbp 0"
/* nop -> nop! */
insn_32 "nop"
tran_16_32 "nop!", "nop"

5
include/elf/ChangeLog
View File

@ -1,3 +1,8 @@
2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
* score.h (RELOC_NUMBER): Add R_SCORE_IMM32.
* common.h (EM_SCORE_OLD): Define.
2009-02-23 H.J. Lu <hongjiu.lu@intel.com>
* common.h (STB_LOPROC): Replace Application-specific with

3
include/elf/common.h
View File

@ -334,6 +334,9 @@
#define EM_CYGNUS_MEP 0xF00D /* Toshiba MeP */
/* Old Sunplus S+core7 backend magic number. Written in the absence of an ABI. */
#define EM_SCORE_OLD 95
/* See the above comment before you add a new EM_* value here. */
/* Values for e_version. */

13
include/elf/score.h
View File

@ -1,6 +1,7 @@
/* Score ELF support for BFD.
Copyright 2006, 2008 Free Software Foundation, Inc.
Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Contributed by
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
@ -8,7 +9,7 @@
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@ -35,6 +36,10 @@
#define GP_DISP_LABEL "_gp_disp"
/* Processor specific flags for the ELF header e_flags field: */
#define EF_SCORE_MACH 0xffff0000
#define EF_OMIT_PIC_FIXDD 0x0fff0000
#define E_SCORE_MACH_SCORE3 0x00030000
#define E_SCORE_MACH_SCORE7 0x00070000
/* File contains position independent code. */
#define EF_SCORE_PIC 0x80000000
@ -101,7 +106,7 @@ START_RELOC_NUMBERS (elf_score_reloc_type)
RELOC_NUMBER (R_SCORE_NONE, 0)
RELOC_NUMBER (R_SCORE_HI16, 1)
RELOC_NUMBER (R_SCORE_LO16, 2)
RELOC_NUMBER (R_SCORE_DUMMY1, 3)
RELOC_NUMBER (R_SCORE_BCMP, 3)
RELOC_NUMBER (R_SCORE_24, 4)
RELOC_NUMBER (R_SCORE_PC19, 5)
RELOC_NUMBER (R_SCORE16_11, 6)
@ -118,6 +123,8 @@ START_RELOC_NUMBERS (elf_score_reloc_type)
RELOC_NUMBER (R_SCORE_GPREL32, 17)
RELOC_NUMBER (R_SCORE_REL32, 18)
RELOC_NUMBER (R_SCORE_DUMMY_HI16, 19)
RELOC_NUMBER (R_SCORE_IMM30, 20)
RELOC_NUMBER (R_SCORE_IMM32, 21)
END_RELOC_NUMBERS (R_SCORE_max)
#endif /* _ELF_SCORE_H */

6
include/opcode/ChangeLog
View File

@ -1,3 +1,9 @@
2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
* score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
and _IMM11 for mbitclr and mbitset.
* score-datadep.h: Update dependency information.
2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
* ppc.h (PPC_OPCODE_POWER7): New.

227
include/opcode/score-datadep.h
View File

@ -1,6 +1,7 @@
/* score-datadep.h -- Score Instructions data dependency table
Copyright 2006 Free Software Foundation, Inc.
Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Contributed by:
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
@ -8,7 +9,7 @@
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
@ -28,20 +29,7 @@
enum insn_type_for_dependency
{
D_pce,
D_cond_br,
D_cond_mv,
D_cached,
D_cachei,
D_ldst,
D_ldcombine,
D_mtcr,
D_mfcr,
D_mfsr,
D_mftlb,
D_mtptlb,
D_mtrtlb,
D_stlb,
D_all_insn
};
@ -58,225 +46,20 @@ struct data_dependency
enum insn_type_for_dependency cur_insn_type;
char cur_reg[6];
int bubblenum_7;
int bubblenum_5;
int bubblenum_3;
int warn_or_error; /* warning - 0; error - 1 */
};
static const struct insn_to_dependency insn_to_dependency_table[] =
{
/* pce instruction. */
{"pce", D_pce},
/* conditional branch instruction. */
{"bcs", D_cond_br},
{"bcc", D_cond_br},
{"bgtu", D_cond_br},
{"bleu", D_cond_br},
{"beq", D_cond_br},
{"bne", D_cond_br},
{"bgt", D_cond_br},
{"ble", D_cond_br},
{"bge", D_cond_br},
{"blt", D_cond_br},
{"bmi", D_cond_br},
{"bpl", D_cond_br},
{"bvs", D_cond_br},
{"bvc", D_cond_br},
{"bcsl", D_cond_br},
{"bccl", D_cond_br},
{"bgtul", D_cond_br},
{"bleul", D_cond_br},
{"beql", D_cond_br},
{"bnel", D_cond_br},
{"bgtl", D_cond_br},
{"blel", D_cond_br},
{"bgel", D_cond_br},
{"bltl", D_cond_br},
{"bmil", D_cond_br},
{"bpll", D_cond_br},
{"bvsl", D_cond_br},
{"bvcl", D_cond_br},
{"bcs!", D_cond_br},
{"bcc!", D_cond_br},
{"bgtu!", D_cond_br},
{"bleu!", D_cond_br},
{"beq!", D_cond_br},
{"bne!", D_cond_br},
{"bgt!", D_cond_br},
{"ble!", D_cond_br},
{"bge!", D_cond_br},
{"blt!", D_cond_br},
{"bmi!", D_cond_br},
{"bpl!", D_cond_br},
{"bvs!", D_cond_br},
{"bvc!", D_cond_br},
{"brcs", D_cond_br},
{"brcc", D_cond_br},
{"brgtu", D_cond_br},
{"brleu", D_cond_br},
{"breq", D_cond_br},
{"brne", D_cond_br},
{"brgt", D_cond_br},
{"brle", D_cond_br},
{"brge", D_cond_br},
{"brlt", D_cond_br},
{"brmi", D_cond_br},
{"brpl", D_cond_br},
{"brvs", D_cond_br},
{"brvc", D_cond_br},
{"brcsl", D_cond_br},
{"brccl", D_cond_br},
{"brgtul", D_cond_br},
{"brleul", D_cond_br},
{"breql", D_cond_br},
{"brnel", D_cond_br},
{"brgtl", D_cond_br},
{"brlel", D_cond_br},
{"brgel", D_cond_br},
{"brltl", D_cond_br},
{"brmil", D_cond_br},
{"brpll", D_cond_br},
{"brvsl", D_cond_br},
{"brvcl", D_cond_br},
{"brcs!", D_cond_br},
{"brcc!", D_cond_br},
{"brgtu!", D_cond_br},
{"brleu!", D_cond_br},
{"breq!", D_cond_br},
{"brne!", D_cond_br},
{"brgt!", D_cond_br},
{"brle!", D_cond_br},
{"brge!", D_cond_br},
{"brlt!", D_cond_br},
{"brmi!", D_cond_br},
{"brpl!", D_cond_br},
{"brvs!", D_cond_br},
{"brvc!", D_cond_br},
{"brcsl!", D_cond_br},
{"brccl!", D_cond_br},
{"brgtul!", D_cond_br},
{"brleul!", D_cond_br},
{"breql!", D_cond_br},
{"brnel!", D_cond_br},
{"brgtl!", D_cond_br},
{"brlel!", D_cond_br},
{"brgel!", D_cond_br},
{"brltl!", D_cond_br},
{"brmil!", D_cond_br},
{"brpll!", D_cond_br},
{"brvsl!", D_cond_br},
{"brvcl!", D_cond_br},
/* conditional move instruction. */
{"mvcs", D_cond_mv},
{"mvcc", D_cond_mv},
{"mvgtu", D_cond_mv},
{"mvleu", D_cond_mv},
{"mveq", D_cond_mv},
{"mvne", D_cond_mv},
{"mvgt", D_cond_mv},
{"mvle", D_cond_mv},
{"mvge", D_cond_mv},
{"mvlt", D_cond_mv},
{"mvmi", D_cond_mv},
{"mvpl", D_cond_mv},
{"mvvs", D_cond_mv},
{"mvvc", D_cond_mv},
/* move spectial instruction. */
{"mtcr", D_mtcr},
{"mftlb", D_mftlb},
{"mtptlb", D_mtptlb},
{"mtrtlb", D_mtrtlb},
{"stlb", D_stlb},
{"mfcr", D_mfcr},
{"mfsr", D_mfsr},
/* cache instruction. */
{"cache 8", D_cached},
{"cache 9", D_cached},
{"cache 10", D_cached},
{"cache 11", D_cached},
{"cache 12", D_cached},
{"cache 13", D_cached},
{"cache 14", D_cached},
{"cache 24", D_cached},
{"cache 26", D_cached},
{"cache 27", D_cached},
{"cache 29", D_cached},
{"cache 30", D_cached},
{"cache 31", D_cached},
{"cache 0", D_cachei},
{"cache 1", D_cachei},
{"cache 2", D_cachei},
{"cache 3", D_cachei},
{"cache 4", D_cachei},
{"cache 16", D_cachei},
{"cache 17", D_cachei},
/* load/store instruction. */
{"lb", D_ldst},
{"lbu", D_ldst},
{"lbu!", D_ldst},
{"lbup!", D_ldst},
{"lh", D_ldst},
{"lhu", D_ldst},
{"lh!", D_ldst},
{"lhp!", D_ldst},
{"lw", D_ldst},
{"lw!", D_ldst},
{"lwp!", D_ldst},
{"sb", D_ldst},
{"sb!", D_ldst},
{"sbp!", D_ldst},
{"sh", D_ldst},
{"sh!", D_ldst},
{"shp!", D_ldst},
{"sw", D_ldst},
{"sw!", D_ldst},
{"swp!", D_ldst},
{"alw", D_ldst},
{"asw", D_ldst},
{"push!", D_ldst},
{"pushhi!", D_ldst},
{"pop!", D_ldst},
{"pophi!", D_ldst},
{"ldc1", D_ldst},
{"ldc2", D_ldst},
{"ldc3", D_ldst},
{"stc1", D_ldst},
{"stc2", D_ldst},
{"stc3", D_ldst},
{"scb", D_ldst},
{"scw", D_ldst},
{"sce", D_ldst},
/* load combine instruction. */
{"lcb", D_ldcombine},
{"lcw", D_ldcombine},
{"lce", D_ldcombine},
};
static const struct data_dependency data_dependency_table[] =
{
/* Condition register. */
{D_mtcr, "cr1", D_pce, "", 2, 1, 1},
{D_mtcr, "cr1", D_cond_br, "", 1, 0, 1},
{D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1},
/* Status regiser. */
{D_mtcr, "cr0", D_all_insn, "", 5, 4, 0},
/* CCR regiser. */
{D_mtcr, "cr4", D_all_insn, "", 6, 5, 0},
/* EntryHi/EntryLo register. */
{D_mftlb, "", D_mtptlb, "", 1, 1, 1},
{D_mftlb, "", D_mtrtlb, "", 1, 1, 1},
{D_mftlb, "", D_stlb, "", 1, 1,1},
{D_mftlb, "", D_mfcr, "cr11", 1, 1, 1},
{D_mftlb, "", D_mfcr, "cr12", 1, 1, 1},
/* Index register. */
{D_stlb, "", D_mtptlb, "", 1, 1, 1},
{D_stlb, "", D_mftlb, "", 1, 1, 1},
{D_stlb, "", D_mfcr, "cr8", 2, 2, 1},
/* Cache. */
{D_cached, "", D_ldst, "", 1, 1, 0},
{D_cached, "", D_ldcombine, "", 1, 1, 0},
{D_cachei, "", D_all_insn, "", 5, 4, 0},
/* Load combine. */
{D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1},
{D_mtcr, "cr0", D_all_insn, "", 5, 1, 0},
};
#endif

313
include/opcode/score-inst.h
View File

@ -1,6 +1,7 @@
/* score-inst.h -- Score Instructions Table
Copyright 2006 Free Software Foundation, Inc.
Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Contributed by:
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
@ -8,7 +9,7 @@
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
@ -96,6 +97,8 @@ enum score_insn_type
Rd_Rs_I14,
I15,
Rd_I16,
Rd_I30,
Rd_I32,
Rd_rvalueRs_SI10,
Rd_lvalueRs_SI10,
Rd_rvalueRs_preSI12,
@ -105,6 +108,8 @@ enum score_insn_type
Rd_Rs_SI14,
Rd_rvalueRs_SI15,
Rd_lvalueRs_SI15,
Rd_SI5,
Rd_SI6,
Rd_SI16,
PC_DISP8div2,
PC_DISP11div2,
@ -139,6 +144,8 @@ enum score_insn_type
Insn_GP,
Insn_PIC,
Insn_internal,
Insn_BCMP,
Ra_I9_I5,
};
enum score_data_type
@ -178,6 +185,13 @@ enum score_data_type
_SIMM16_pic = 42, /* Index in score_df_range. */
_IMM16_LO16_pic = 43,
_IMM16_pic = 44,
_SIMM5 = 45,
_SIMM6 = 46,
_IMM32 = 47,
_SIMM32 = 48,
_IMM11 = 49,
_IMM5_MULTI_LOAD = 50,
};
#define REG_TMP 1
@ -206,302 +220,17 @@ enum score_data_type
#define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
#define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
struct datafield_range
{
int data_type;
int bits;
int range[2];
};
struct datafield_range score_df_range[] =
{
{_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */
{_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */
{_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */
{_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */
{_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
{_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
{_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */
{_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */
{_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */
{_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */
{_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */
{_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */
{_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_IMM20, 20, {0, (1 << 20) - 1}},
{_IMM25, 25, {0, (1 << 25) - 1}},
{_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */
{_DISP11div2, 11, {0, 0}},
{_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */
{_DISP24div2, 24, {0, 0}},
{_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}},
{_VALUE_HI16, 16, {0, (1 << 16) - 1}},
{_VALUE_LO16, 16, {0, (1 << 16) - 1}},
{_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}},
{_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */
{_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */
{_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
{_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */
{_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */
{_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */
{_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */
{_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */
{_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */
{_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */
{_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */
{_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
{_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
{_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */
{_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */
{_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */
{_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */
{_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
{_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
};
struct shift_bitmask
{
int opd_type;
int opd_num;
struct datafield_range *df_range;
int sh[4];
long fieldbits[4];
};
struct shift_bitmask score_sh_bits_map[] =
{
{
Rd_I4, 2, &score_df_range[_IMM4],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0xf, 0, 0},
},
{
Rd_I5, 2, &score_df_range[_IMM5],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0x1f, 0, 0},
},
{
Rd_rvalueBP_I5, 2, &score_df_range[_IMM5],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0x1f, 0, 0},
},
{
Rd_lvalueBP_I5, 2, &score_df_range[_IMM5],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0x1f, 0, 0},
},
{
Rd_Rs_I5, 3, &score_df_range[_IMM5],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0},
{0x1f, 0x1f, 0x1f, 0},
},
{
x_Rs_I5, 2, &score_df_range[_IMM5],
{OP_SH_REGS1, OP_SH_I5, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
x_I5_x, 1, &score_df_range[_IMM5],
{OP_SH_TRAPI5, 0, 0, 0},
{0x1f, 0, 0, 0},
},
{
Rd_I8, 2, &score_df_range[_IMM8],
{OP16_SH_REGD, OP16_SH_I8, 0, 0},
{0xf, 0xff, 0, 0},
},
{
Rd_Rs_I14, 3, &score_df_range[_IMM14],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
{0x1f, 0x1f, 0x3fff, 0},
},
{
I15, 1, &score_df_range[_IMM15],
{OP_SH_I15, 0, 0, 0},
{0x7fff, 0, 0, 0},
},
{
Rd_I16, 2, &score_df_range[_IMM16],
{OP_SH_REGD, OP_SH_I, 0, 0},
{0x1f, 0xffff, 0, 0},
},
{
Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
{0x1f, 0x1f, 0x3ff, 0},
},
{
Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
{0x1f, 0x1f, 0x3ff, 0},
},
{
Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_Rs_SI14, 3, &score_df_range[_SIMM14],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
{0x1f, 0x1f, 0x3fff, 0},
},
{
Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
{0x1f, 0x1f, 0x7fff, 0},
},
{
Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
{0x1f, 0x1f, 0x7fff, 0},
},
{
Rd_SI16, 2, &score_df_range[_SIMM16],
{OP_SH_REGD, OP_SH_I, 0, 0},
{0x1f, 0xffff, 0, 0},
},
{
PC_DISP8div2, 1, &score_df_range[_DISP8div2],
{OP16_SH_DISP8, 0, 0, 0},
{0xff, 0, 0, 0},
},
{
PC_DISP11div2, 1, &score_df_range[_DISP11div2],
{OP16_SH_DISP11, 0, 0, 0},
{0x7ff, 0, 0, 0},
},
{
PC_DISP19div2, 2, &score_df_range[_DISP19div2],
{OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0},
{0x3ff, 0x1ff, 0, 0},
},
{
PC_DISP24div2, 1, &score_df_range[_DISP24div2],
{OP_SH_DISP24, 0, 0, 0},
{0xffffff, 0, 0, 0},
},
{
Rd_Rs_Rs, 3, NULL,
{OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0},
{0x1f, 0x1f, 0x1f, 0}
},
{
Rd_Rs_x, 2, NULL,
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
Rd_x_Rs, 2, NULL,
{OP_SH_REGD, OP_SH_REGS2, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
Rd_x_x, 1, NULL,
{OP_SH_REGD, 0, 0, 0},
{0x1f, 0, 0, 0},
},
{
x_Rs_Rs, 2, NULL,
{OP_SH_REGS1, OP_SH_REGS2, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
x_Rs_x, 1, NULL,
{OP_SH_REGS1, 0, 0, 0},
{0x1f, 0, 0, 0},
},
{
Rd_Rs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0, 0},
},
{
Rd_HighRs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0x1f, 0},
},
{
Rd_rvalueRs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0, 0},
},
{
Rd_lvalueRs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0, 0}
},
{
Rd_lvalue32Rs, 2, NULL,
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
Rd_rvalue32Rs, 2, NULL,
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
x_Rs, 1, NULL,
{OP16_SH_REGS1, 0, 0, 0},
{0xf, 0, 0, 0},
},
{
NO_OPD, 0, NULL,
{0, 0, 0, 0},
{0, 0, 0, 0},
},
{
NO16_OPD, 0, NULL,
{0, 0, 0, 0},
{0, 0, 0, 0},
},
};
struct asm_opcode
{
/* Instruction name. */
const char *template;
/* Instruction Opcode. */
unsigned long value;
/* Instruction bit mask. */
unsigned long bitmask;
/* Relax instruction opcode. 0x8000 imply no relaxation. */
unsigned long relax_value;
/* Instruction type. */
enum score_insn_type type;
/* Function to call to parse args. */
void (*parms) (char *);
};
enum insn_class
{
INSN_CLASS_16,
INSN_CLASS_32,
INSN_CLASS_48,
INSN_CLASS_PCE,
INSN_CLASS_SYN
};
/* s3_s7: Globals for both tc-score.c and elf32-score.c. */
extern int score3;
extern int score7;
#endif

10
ld/ChangeLog
View File

@ -1,3 +1,13 @@
2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
* Makefile.am: Replace score elf emulation with score3 and score7
emulations.
* Makefile.in: Regenerate,
* NEWS: Mention support for Score7 architecture.
* configure.tgt: Add score7 emulation to score-elf target.
* emulparams/scoreelf.sh: Add score7 support.
* emultempl/scoreelf.em: Likewise.
2009-03-01 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
* configure.tgt: Only use elf64hppa target emulation for hpux.

15
ld/Makefile.am
View File

@ -356,7 +356,8 @@ ALL_EMULATIONS = \
eppcpe.o \
eppclynx.o \
eriscix.o \
escoreelf.o \
escore3_elf.o \
escore7_elf.o \
esh.o \
eshelf32.o \
eshlelf32.o \
@ -1556,10 +1557,14 @@ eppclynx.c: $(srcdir)/emulparams/ppclynx.sh \
eriscix.c: $(srcdir)/emulparams/riscix.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} riscix "$(tdir_riscix)"
escoreelf.c: $(srcdir)/emulparams/scoreelf.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/scoreelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} scoreelf "$(tdir_scoreelf)"
escore3_elf.c: $(srcdir)/emulparams/scoreelf.sh \
$(ELF_DEPS) $(srcdir)/emultempl/scoreelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} score3_elf "$(tdir_score3_elf)" scoreelf
escore7_elf.c: $(srcdir)/emulparams/scoreelf.sh \
$(ELF_DEPS) $(srcdir)/emultempl/scoreelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} score7_elf "$(tdir_score7_elf)" scoreelf
esh.c: $(srcdir)/emulparams/sh.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/sh.sc ${GEN_DEPENDS}
${GENSCRIPTS} sh "$(tdir_sh)"

15
ld/Makefile.in
View File

@ -620,7 +620,8 @@ ALL_EMULATIONS = \
eppcpe.o \
eppclynx.o \
eriscix.o \
escoreelf.o \
escore3_elf.o \
escore7_elf.o \
esh.o \
eshelf32.o \
eshlelf32.o \
@ -2402,10 +2403,14 @@ eppclynx.c: $(srcdir)/emulparams/ppclynx.sh \
eriscix.c: $(srcdir)/emulparams/riscix.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} riscix "$(tdir_riscix)"
escoreelf.c: $(srcdir)/emulparams/scoreelf.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/scoreelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} scoreelf "$(tdir_scoreelf)"
escore3_elf.c: $(srcdir)/emulparams/scoreelf.sh \
$(ELF_DEPS) $(srcdir)/emultempl/scoreelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} score3_elf "$(tdir_score3_elf)" scoreelf
escore7_elf.c: $(srcdir)/emulparams/scoreelf.sh \
$(ELF_DEPS) $(srcdir)/emultempl/scoreelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} score7_elf "$(tdir_score7_elf)" scoreelf
esh.c: $(srcdir)/emulparams/sh.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/sh.sc ${GEN_DEPENDS}
${GENSCRIPTS} sh "$(tdir_sh)"

2
ld/NEWS
View File

@ -13,6 +13,8 @@
* Add a new command line option, -Ttext-segment ADDR, for ELF targets
to set the address of the first byte of the text segment.
* Add support for Sunplus score architecture.
* Add new option --use-nul-prefixed-import-tables to ld for PE targets to
allow fallback to old import table generation with null element prefix.

3
ld/configure.tgt
View File

@ -506,7 +506,8 @@ s390-*-linux*) targ_emul=elf_s390
targ64_extra_libpath=elf64_s390
tdir_elf64_s390=`echo ${targ_alias} | sed -e 's/s390/s390x/'`
;;
score-*-elf) targ_emul=scoreelf ;;
score-*-elf) targ_emul=score7_elf
targ_extra_emuls=score3_elf ;;
sh-*-linux*) targ_emul=shlelf_linux
targ_extra_emuls=shelf_linux
targ_extra_libpath=shelf_linux ;;

15
ld/emulparams/scoreelf.sh
View File

@ -1,6 +1,7 @@
MACHINE=
SCRIPT_NAME=elf
TEMPLATE_NAME=elf32
EXTRA_EM_FILE=scoreelf
OUTPUT_FORMAT="elf32-bigscore"
BIG_OUTPUT_FORMAT="elf32-bigscore"
LITTLE_OUTPUT_FORMAT="elf32-littlescore"
@ -8,10 +9,8 @@ NO_RELA_RELOCS=yes
GROUP="-lm -lc -lglsim -lgcc -lstdc++"
TEXT_START_ADDR=0x00000000
case ${LD_FLAG} in
n|N) TEXT_START_ADDR=0x0400000 ;;
esac
MAXPAGESIZE=256
NONPAGED_TEXT_START_ADDR=0x0400000
SHLIB_TEXT_START_ADDR=0x5ffe0000
OTHER_GOT_SYMBOLS='
_gp = ALIGN(16) + 0x3ff0;
@ -27,7 +26,15 @@ OTHER_BSS_SYMBOLS='
# This sets the stack to the top of the simulator memory (2^19 bytes).
STACK_ADDR=0x8000000
ARCH=score
SCORE_NAME=${EMULATION_NAME}
if [ "${SCORE_NAME}" = "score3_elf" ] ; then
ARCH=score3
fi
if [ "${SCORE_NAME}" = "score7_elf" ] ; then
ARCH=score7
fi
MACHINE=
ENTRY=_start
EMBEDDED=yes

21
ld/emultempl/scoreelf.em
View File

@ -1,6 +1,7 @@
# This shell script emits a C file. -*- C -*-
# Copyright 2006, 2007, 2008 Free Software Foundation, Inc.
# Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
# Contributed by:
# Brain.lin (brain.lin@sunplusct.com)
# Mei Ligang (ligang@sunnorth.com.cn)
# Pei-Lin Tsai (pltsai@sunplus.com)
@ -27,14 +28,16 @@
#
fragment <<EOF
#include "elf32-score.h"
static void
gld${EMULATION_NAME}_before_parse ()
{
#ifndef TARGET_ /* I.e., if not generic. */
ldfile_set_output_arch ("`echo ${ARCH}`");
ldfile_set_output_arch ("`echo ${ARCH}`", bfd_arch_unknown);
#endif /* not TARGET_ */
config.dynamic_link = ${DYNAMIC_LINK-true};
config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo true ; else echo false ; fi`;
config.dynamic_link = ${DYNAMIC_LINK-TRUE};
config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo TRUE ; else echo FALSE ; fi`;
}
static void
@ -56,9 +59,19 @@ score_elf_after_open (void)
EOF
# Define some shell vars to insert bits of code into the standard elf
# parse_args and list_options functions.
#
PARSE_AND_LIST_PROLOGUE=''
PARSE_AND_LIST_SHORTOPTS=
PARSE_AND_LIST_LONGOPTS=''
PARSE_AND_LIST_OPTIONS=''
PARSE_AND_LIST_ARGS_CASES=''
# We have our own after_open and before_allocation functions, but they call
# the standard routines, so give them a different name.
LDEMUL_AFTER_OPEN=score_elf_after_open
# Replace the elf before_parse function with our own.
LDEMUL_BEFORE_PARSE=gld"${EMULATION_NAME}"_before_parse

10
opcodes/ChangeLog
View File

@ -1,3 +1,13 @@
2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
* score7-dis.c: New file.
* Makefile.am: Add dependencies for score7-dis.c.
* Makefile.in: Regenerate.
* configure.in: Add score7-dis to score files.
* configure: Regenerate.
* score-dis.c: Add support for score7 architecture.
* score-opc.h: Likewise.
2009-03-01 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* configure: Regenerate.

7
opcodes/Makefile.am
View File

@ -189,6 +189,7 @@ CFILES = \
s390-opc.c \
s390-dis.c \
score-dis.c \
score7-dis.c \
sh-dis.c \
sh64-dis.c \
sh64-opc.c \
@ -337,6 +338,7 @@ ALL_MACHINES = \
s390-dis.lo \
s390-opc.lo \
score-dis.lo \
score7-dis.lo \
sh-dis.lo \
sh64-dis.lo \
sh64-opc.lo \
@ -1125,6 +1127,11 @@ score-dis.lo: score-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/bfdlink.h \
$(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h
score7-dis.lo: score7-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h score-opc.h \
opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/bfdlink.h \
$(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h
sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
sh-opc.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/dis-asm.h
sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \

7
opcodes/Makefile.in
View File

@ -427,6 +427,7 @@ CFILES = \
s390-opc.c \
s390-dis.c \
score-dis.c \
score7-dis.c \
sh-dis.c \
sh64-dis.c \
sh64-opc.c \
@ -575,6 +576,7 @@ ALL_MACHINES = \
s390-dis.lo \
s390-opc.lo \
score-dis.lo \
score7-dis.lo \
sh-dis.lo \
sh64-dis.lo \
sh64-opc.lo \
@ -1689,6 +1691,11 @@ score-dis.lo: score-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/bfdlink.h \
$(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h
score7-dis.lo: score7-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h score-opc.h \
opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/bfdlink.h \
$(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h
sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
sh-opc.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/dis-asm.h
sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \

2
opcodes/configure vendored
View File

@ -12558,7 +12558,7 @@ if test x${all_targets} = xfalse ; then
bfd_romp_arch) ;;
bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;;
bfd_score_arch) ta="$ta score-dis.lo" ;;
bfd_score_arch) ta="$ta score-dis.lo score7-dis.lo" ;;
bfd_sh_arch)
# We can't decide what we want just from the CPU family.
# We want SH5 support unless a specific version of sh is

2
opcodes/configure.in
View File

@ -231,7 +231,7 @@ if test x${all_targets} = xfalse ; then
bfd_romp_arch) ;;
bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;;
bfd_score_arch) ta="$ta score-dis.lo" ;;
bfd_score_arch) ta="$ta score-dis.lo score7-dis.lo" ;;
bfd_sh_arch)
# We can't decide what we want just from the CPU family.
# We want SH5 support unless a specific version of sh is

890
opcodes/score-dis.c
View File

File diff suppressed because it is too large Load Diff

460
opcodes/score-opc.h
View File

@ -19,9 +19,9 @@
struct score_opcode
{
unsigned long value;
unsigned long mask; /* Recognise instruction if (op & mask) == value. */
char *assembler; /* Disassembly string. */
bfd_vma value;
bfd_vma mask; /* Recognise instruction if (op & mask) == value. */
char *assembler; /* Disassembly string. */
};
/* Note: There is a partial ordering in this table - it must be searched from
@ -31,7 +31,7 @@ static struct score_opcode score_opcodes[] =
{
/* Score Instructions. */
{0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"},
{0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
{0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
{0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"},
{0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"},
{0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"},
@ -43,139 +43,110 @@ static struct score_opcode score_opcodes[] =
{0x0a000001, 0x3e0e0001, "addis.c\t\t%20-24r, %1-16d(0x%1-16x)"},
{0x10000000, 0x3e000001, "addri\t\t%20-24r, %15-19r, %1-14i"},
{0x10000001, 0x3e000001, "addri.c\t\t%20-24r, %15-19r, %1-14i"},
{0x00000009, 0x0000700f, "addc!\t\t%8-11r, %4-7r"},
{0x00002000, 0x0000700f, "add!\t\t%8-11r, %4-7r"},
{0x00006000, 0x00007087, "addei!\t\t%8-11r, %3-6d"},
{0x00004800, 0x00007f00, "add!\t\t%4-7r, %0-3r"},
{0x00005c00, 0x00007c00, "addi!\t\t%6-9r, %0-5i"},
{0x00000020, 0x3e0003ff, "and\t\t%20-24r, %15-19r, %10-14r"},
{0x00000021, 0x3e0003ff, "and.c\t\t%20-24r, %15-19r, %10-14r"},
{0x040000000000LL, 0x1c0000000003LL, "andri48\t\t%38-41r,%34-37r, 0x%2-33x"},
{0x040000000001LL, 0x1c0000000003LL, "andri48.c\t\t%38-41r,%34-37r, 0x%2-33x"},
{0x02080000, 0x3e0e0001, "andi\t\t%20-24r, 0x%1-16x"},
{0x02080001, 0x3e0e0001, "andi.c\t\t%20-24r, 0x%1-16x"},
{0x0a080000, 0x3e0e0001, "andis\t\t%20-24r, 0x%1-16x"},
{0x0a080001, 0x3e0e0001, "andis.c\t\t%20-24r, 0x%1-16x"},
{0x18000000, 0x3e000001, "andri\t\t%20-24r, %15-19r, 0x%1-14x"},
{0x18000001, 0x3e000001, "andri.c\t\t%20-24r, %15-19r,0x%1-14x"},
{0x00002004, 0x0000700f, "and!\t\t%8-11r, %4-7r"},
{0x08000000, 0x3e007c01, "bcs\t\t%b" },
{0x08000400, 0x3e007c01, "bcc\t\t%b" },
{0x08003800, 0x3e007c01, "bcnz\t\t%b" },
{0x08000001, 0x3e007c01, "bcsl\t\t%b" },
{0x08000401, 0x3e007c01, "bccl\t\t%b" },
{0x08003801, 0x3e007c01, "bcnzl\t\t%b" },
{0x00004000, 0x00007f00, "bcs!\t\t%b" },
{0x00004100, 0x00007f00, "bcc!\t\t%b" },
{0x00004e00, 0x00007f00, "bcnz!\t\t%b" },
{0x08001000, 0x3e007c01, "beq\t\t%b" },
{0x08001001, 0x3e007c01, "beql\t\t%b" },
{0x00004400, 0x00007f00, "beq!\t\t%b" },
{0x08000800, 0x3e007c01, "bgtu\t\t%b" },
{0x08001800, 0x3e007c01, "bgt\t\t%b" },
{0x08002000, 0x3e007c01, "bge\t\t%b" },
{0x08000801, 0x3e007c01, "bgtul\t\t%b" },
{0x08001801, 0x3e007c01, "bgtl\t\t%b" },
{0x08002001, 0x3e007c01, "bgel\t\t%b" },
{0x00004200, 0x00007f00, "bgtu!\t\t%b" },
{0x00004600, 0x00007f00, "bgt!\t\t%b" },
{0x00004800, 0x00007f00, "bge!\t\t%b" },
{0x00004b00, 0x00007f00, "and!\t\t%4-7r, %0-3r"},
{0x08000000, 0x3e007c01, "bcs\t\t%b"},
{0x08000400, 0x3e007c01, "bcc\t\t%b"},
{0x08003800, 0x3e007c01, "bcnz\t\t%b"},
{0x08000001, 0x3e007c01, "bcsl\t\t%b"},
{0x08000401, 0x3e007c01, "bccl\t\t%b"},
{0x08003801, 0x3e007c01, "bcnzl\t\t%b"},
{0x0000004c, 0x3e00007e, "bcmpeqz\t\t%15-19r, %z"},
{0x0000004c, 0x3e00007e, "bcmpeq\t\t%15-19r, %z"},
{0x0000004e, 0x3e00007e, "bcmpnez\t\t%15-19r, %z"},
{0x0000004e, 0x3e00007e, "bcmpne\t\t%15-19r, %z"},
{0x00003200, 0x00007e00, "bcnz!\t\t%b"},
{0x08001000, 0x3e007c01, "beq\t\t%b"},
{0x08001001, 0x3e007c01, "beql\t\t%b"},
{0x00003800, 0x00007e00, "beq!\t\t%b"},
{0x08000800, 0x3e007c01, "bgtu\t\t%b"},
{0x08001800, 0x3e007c01, "bgt\t\t%b"},
{0x08002000, 0x3e007c01, "bge\t\t%b"},
{0x08000801, 0x3e007c01, "bgtul\t\t%b"},
{0x08001801, 0x3e007c01, "bgtl\t\t%b"},
{0x08002001, 0x3e007c01, "bgel\t\t%b"},
{0x00003400, 0x00007e00, "bgtu!\t\t%b"},
{0x00003c00, 0x00007e00, "bgt!\t\t%b"},
{0x00000029, 0x3e0003ff, "bitclr.c\t%20-24r, %15-19r, 0x%10-14x"},
{0x00000028, 0x3e0003ff, "bitclr\t%20-24r, %15-19r, 0x%10-14x"},
{0x0000002b, 0x3e0003ff, "bitset.c\t%20-24r, %15-19r, 0x%10-14x"},
{0x0000002a, 0x3e0003ff, "bitset\t%20-24r, %15-19r, 0x%10-14x"},
{0x0000002d, 0x3e0003ff, "bittst.c\t%15-19r, 0x%10-14x"},
{0x0000002f, 0x3e0003ff, "bittgl.c\t%20-24r, %15-19r, 0x%10-14x"},
{0x00006004, 0x00007007, "bitclr!\t\t%8-11r, 0x%3-7x"},
{0x0000002e, 0x3e0003ff, "bittgl\t%20-24r, %15-19r, 0x%10-14x"},
{0x00005000, 0x00007e00, "bitclr!\t\t%5-8r, 0x%0-4x"},
{0x3800000c, 0x3e0003ff, "bitrev\t\t%20-24r, %15-19r,%10-14r"},
{0x00006005, 0x00007007, "bitset!\t\t%8-11r, 0x%3-7x"},
{0x00006006, 0x00007007, "bittst!\t\t%8-11r, 0x%3-7x"},
{0x00006007, 0x00007007, "bittgl!\t\t%8-11r, 0x%3-7x"},
{0x08000c00, 0x3e007c01, "bleu\t\t%b" },
{0x08001c00, 0x3e007c01, "ble\t\t%b" },
{0x08002400, 0x3e007c01, "blt\t\t%b" },
{0x08000c01, 0x3e007c01, "bleul\t\t%b" },
{0x08001c01, 0x3e007c01, "blel\t\t%b" },
{0x08002401, 0x3e007c01, "bltl\t\t%b" },
{0x08003c01, 0x3e007c01, "bl\t\t%b" },
{0x00004300, 0x00007f00, "bleu!\t\t%b" },
{0x00004700, 0x00007f00, "ble!\t\t%b" },
{0x00004900, 0x00007f00, "blt!\t\t%b" },
{0x08002800, 0x3e007c01, "bmi\t\t%b" },
{0x08002801, 0x3e007c01, "bmil\t\t%b" },
{0x00004a00, 0x00007f00, "bmi!\t\t%b" },
{0x08001400, 0x3e007c01, "bne\t\t%b" },
{0x08001401, 0x3e007c01, "bnel\t\t%b" },
{0x00004500, 0x00007f00, "bne!\t\t%b" },
{0x08002c00, 0x3e007c01, "bpl\t\t%b" },
{0x08002c01, 0x3e007c01, "bpll\t\t%b" },
{0x00004b00, 0x00007f00, "bpl!\t\t%b" },
{0x00000008, 0x3e007fff, "brcs\t\t%15-19r" },
{0x00000408, 0x3e007fff, "brcc\t\t%15-19r" },
{0x00000808, 0x3e007fff, "brgtu\t\t%15-19r" },
{0x00000c08, 0x3e007fff, "brleu\t\t%15-19r" },
{0x00001008, 0x3e007fff, "breq\t\t%15-19r" },
{0x00001408, 0x3e007fff, "brne\t\t%15-19r" },
{0x00001808, 0x3e007fff, "brgt\t\t%15-19r" },
{0x00001c08, 0x3e007fff, "brle\t\t%15-19r" },
{0x00002008, 0x3e007fff, "brge\t\t%15-19r" },
{0x00002408, 0x3e007fff, "brlt\t\t%15-19r" },
{0x00002808, 0x3e007fff, "brmi\t\t%15-19r" },
{0x00002c08, 0x3e007fff, "brpl\t\t%15-19r" },
{0x00003008, 0x3e007fff, "brvs\t\t%15-19r" },
{0x00003408, 0x3e007fff, "brvc\t\t%15-19r" },
{0x00003808, 0x3e007fff, "brcnz\t\t%15-19r" },
{0x00003c08, 0x3e007fff, "br\t\t%15-19r" },
{0x00000009, 0x3e007fff, "brcsl\t\t%15-19r" },
{0x00000409, 0x3e007fff, "brccl\t\t%15-19r" },
{0x00000809, 0x3e007fff, "brgtul\t\t%15-19r" },
{0x00000c09, 0x3e007fff, "brleul\t\t%15-19r" },
{0x00001009, 0x3e007fff, "breql\t\t%15-19r" },
{0x00001409, 0x3e007fff, "brnel\t\t%15-19r" },
{0x00001809, 0x3e007fff, "brgtl\t\t%15-19r" },
{0x00001c09, 0x3e007fff, "brlel\t\t%15-19r" },
{0x00002009, 0x3e007fff, "brgel\t\t%15-19r" },
{0x00002409, 0x3e007fff, "brltl\t\t%15-19r" },
{0x00002809, 0x3e007fff, "brmil\t\t%15-19r" },
{0x00002c09, 0x3e007fff, "brpll\t\t%15-19r" },
{0x00003009, 0x3e007fff, "brvsl\t\t%15-19r" },
{0x00003409, 0x3e007fff, "brvcl\t\t%15-19r" },
{0x00003809, 0x3e007fff, "brcnzl\t\t%15-19r" },
{0x00003c09, 0x3e007fff, "brl\t\t%15-19r" },
{0x00000004, 0x00007f0f, "brcs!\t\t%4-7r" },
{0x00000104, 0x00007f0f, "brcc!\t\t%4-7r" },
{0x00000204, 0x00007f0f, "brgtu!\t\t%4-7r" },
{0x00000304, 0x00007f0f, "brleu!\t\t%4-7r" },
{0x00000404, 0x00007f0f, "breq!\t\t%4-7r" },
{0x00000504, 0x00007f0f, "brne!\t\t%4-7r" },
{0x00000604, 0x00007f0f, "brgt!\t\t%4-7r" },
{0x00000704, 0x00007f0f, "brle!\t\t%4-7r" },
{0x00000804, 0x00007f0f, "brge!\t\t%4-7r" },
{0x00000904, 0x00007f0f, "brlt!\t\t%4-7r" },
{0x00000a04, 0x00007f0f, "brmi!\t\t%4-7r" },
{0x00000b04, 0x00007f0f, "brpl!\t\t%4-7r" },
{0x00000c04, 0x00007f0f, "brvs!\t\t%4-7r" },
{0x00000d04, 0x00007f0f, "brvc!\t\t%4-7r" },
{0x00000e04, 0x00007f0f, "brcnz!\t\t%4-7r" },
{0x00000f04, 0x00007f0f, "br!\t\t%4-7r" },
{0x0000000c, 0x00007f0f, "brcsl!\t\t%4-7r" },
{0x0000010c, 0x00007f0f, "brccl!\t\t%4-7r" },
{0x0000020c, 0x00007f0f, "brgtul!\t\t%4-7r" },
{0x0000030c, 0x00007f0f, "brleul!\t\t%4-7r" },
{0x0000040c, 0x00007f0f, "breql!\t\t%4-7r" },
{0x0000050c, 0x00007f0f, "brnel!\t\t%4-7r" },
{0x0000060c, 0x00007f0f, "brgtl!\t\t%4-7r" },
{0x0000070c, 0x00007f0f, "brlel!\t\t%4-7r" },
{0x0000080c, 0x00007f0f, "brgel!\t\t%4-7r" },
{0x0000090c, 0x00007f0f, "brltl!\t\t%4-7r" },
{0x00000a0c, 0x00007f0f, "brmil!\t\t%4-7r" },
{0x00000b0c, 0x00007f0f, "brpll!\t\t%4-7r" },
{0x00000c0c, 0x00007f0f, "brvsl!\t\t%4-7r" },
{0x00000d0c, 0x00007f0f, "brvcl!\t\t%4-7r" },
{0x00000e0c, 0x00007f0f, "brcnzl!\t\t%4-7r" },
{0x00000f0c, 0x00007f0f, "brl!\t\t%4-7r" },
{0x08003000, 0x3e007c01, "bvs\t\t%b" },
{0x08003400, 0x3e007c01, "bvc\t\t%b" },
{0x08003001, 0x3e007c01, "bvsl\t\t%b" },
{0x08003401, 0x3e007c01, "bvcl\t\t%b" },
{0x00004c00, 0x00007f00, "bvs!\t\t%b" },
{0x00004d00, 0x00007f00, "bvc!\t\t%b" },
{0x00004f00, 0x00007f00, "b!\t\t%b" },
{0x08003c00, 0x3e007c01, "b\t\t%b" },
{0x00005200, 0x00007e00, "bitset!\t\t%5-8r, 0x%0-4x"},
{0x00005400, 0x00007e00, "bittst!\t\t%5-8r, 0x%0-4x"},
{0x00005600, 0x00007e00, "bittgl!\t\t%5-8r, 0x%0-4x"},
{0x08000c00, 0x3e007c01, "bleu\t\t%b"},
{0x08001c00, 0x3e007c01, "ble\t\t%b"},
{0x08002400, 0x3e007c01, "blt\t\t%b"},
{0x08000c01, 0x3e007c01, "bleul\t\t%b"},
{0x08001c01, 0x3e007c01, "blel\t\t%b"},
{0x08002401, 0x3e007c01, "bltl\t\t%b"},
{0x08003c01, 0x3e007c01, "bl\t\t%b"},
{0x00003600, 0x00007e00, "bleu!\t\t%b"},
{0x00003e00, 0x00007e00, "ble!\t\t%b"},
{0x08002800, 0x3e007c01, "bmi\t\t%b"},
{0x08002801, 0x3e007c01, "bmil\t\t%b"},
{0x08001400, 0x3e007c01, "bne\t\t%b"},
{0x08001401, 0x3e007c01, "bnel\t\t%b"},
{0x00003a00, 0x00007e00, "bne!\t\t%b"},
{0x08002c00, 0x3e007c01, "bpl\t\t%b"},
{0x08002c01, 0x3e007c01, "bpll\t\t%b"},
{0x00000008, 0x3e007fff, "brcs\t\t%15-19r"},
{0x00000408, 0x3e007fff, "brcc\t\t%15-19r"},
{0x00000808, 0x3e007fff, "brgtu\t\t%15-19r"},
{0x00000c08, 0x3e007fff, "brleu\t\t%15-19r"},
{0x00001008, 0x3e007fff, "breq\t\t%15-19r"},
{0x00001408, 0x3e007fff, "brne\t\t%15-19r"},
{0x00001808, 0x3e007fff, "brgt\t\t%15-19r"},
{0x00001c08, 0x3e007fff, "brle\t\t%15-19r"},
{0x00002008, 0x3e007fff, "brge\t\t%15-19r"},
{0x00002408, 0x3e007fff, "brlt\t\t%15-19r"},
{0x00002808, 0x3e007fff, "brmi\t\t%15-19r"},
{0x00002c08, 0x3e007fff, "brpl\t\t%15-19r"},
{0x00003008, 0x3e007fff, "brvs\t\t%15-19r"},
{0x00003408, 0x3e007fff, "brvc\t\t%15-19r"},
{0x00003808, 0x3e007fff, "brcnz\t\t%15-19r"},
{0x00003c08, 0x3e007fff, "br\t\t%15-19r"},
{0x00000009, 0x3e007fff, "brcsl\t\t%15-19r"},
{0x00000409, 0x3e007fff, "brccl\t\t%15-19r"},
{0x00000809, 0x3e007fff, "brgtul\t\t%15-19r"},
{0x00000c09, 0x3e007fff, "brleul\t\t%15-19r"},
{0x00001009, 0x3e007fff, "breql\t\t%15-19r"},
{0x00001409, 0x3e007fff, "brnel\t\t%15-19r"},
{0x00001809, 0x3e007fff, "brgtl\t\t%15-19r"},
{0x00001c09, 0x3e007fff, "brlel\t\t%15-19r"},
{0x00002009, 0x3e007fff, "brgel\t\t%15-19r"},
{0x00002409, 0x3e007fff, "brltl\t\t%15-19r"},
{0x00002809, 0x3e007fff, "brmil\t\t%15-19r"},
{0x00002c09, 0x3e007fff, "brpll\t\t%15-19r"},
{0x00003009, 0x3e007fff, "brvsl\t\t%15-19r"},
{0x00003409, 0x3e007fff, "brvcl\t\t%15-19r"},
{0x00003809, 0x3e007fff, "brcnzl\t\t%15-19r"},
{0x00003c09, 0x3e007fff, "brl\t\t%15-19r"},
{0x00000080, 0x00007fe0, "br!\t\t%0-4r"},
{0x000000a0, 0x00007fe0, "brl!\t\t%0-4r"},
{0x000000c0, 0x00007fe0, "brr!\t\t%0-4r"},
{0x08003000, 0x3e007c01, "bvs\t\t%b"},
{0x08003400, 0x3e007c01, "bvc\t\t%b"},
{0x08003001, 0x3e007c01, "bvsl\t\t%b"},
{0x08003401, 0x3e007c01, "bvcl\t\t%b"},
{0x00003000, 0x00007e00, "b!\t\t%b"},
{0x08003c00, 0x3e007c01, "b\t\t%b"},
{0x30000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30200000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
@ -198,32 +169,36 @@ static struct score_opcode score_opcodes[] =
{0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"},
{0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
{0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
{0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"},
{0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
{0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
{0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"},
{0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"},
{0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
{0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
{0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
{0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
{0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
{0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
{0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
{0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
{0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
{0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
{0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
{0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
{0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
{0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
{0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
{0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
{0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
{0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
{0x00000064, 0x3e00007e, "mbitclr\t\t[%15-19r, %m], %10-14d"},
{0x0000006c, 0x3e00007e, "mbitset\t\t[%20-24r, %m], %10-14d"},
{0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"},
{0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
{0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
{0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
{0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
{0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
{0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
{0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"},
{0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
{0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
{0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
{0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
{0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
{0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
{0x3800000d, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
{0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
{0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
{0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
{0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
{0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
{0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
{0x0000001c, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
{0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"},
{0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"},
{0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"},
@ -232,13 +207,22 @@ static struct score_opcode score_opcodes[] =
{0x0010001b, 0x3ff07fff, "cmpztmi.c\t%15-19r"},
{0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"},
{0x02040001, 0x3e0e0001, "cmpi.c\t\t%20-24r, %1-16i"},
{0x00002003, 0x0000700f, "cmp!\t\t%8-11r, %4-7r"},
{0x00004400, 0x00007c00, "cmp!\t\t%5-9r, %0-4r"},
{0x00006000, 0x00007c00, "cmpi!\t\t%5-9r, %0-4i"},
{0x0c00000c, 0x3e00001f, "cop1\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
{0x0c000014, 0x3e00001f, "cop2\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
{0x0c00001c, 0x3e00001f, "cop3\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
{0x00000044, 0x3e0003ff, "div\t\t%15-19r, %10-14r"},
{0x00000144, 0x3e0003ff, "divr.q\t\t%20-24r,%15-19r, %10-14r"},
{0x00000244, 0x3e0003ff, "divr.r\t\t%20-24r,%15-19r, %10-14r"},
{0x00000344, 0x3e0003ff, "divr\t\t%20-24r,%15-19r, %10-14r"},
{0x00000046, 0x3e0003ff, "divu\t\t%15-19r, %10-14r"},
{0x0c0000a4, 0x3e0003ff, "drte" },
{0x00000146, 0x3e0003ff, "divur.q\t\t%20-24r,%15-19r, %10-14r"},
{0x00000246, 0x3e0003ff, "divur.r\t\t%20-24r,%15-19r, %10-14r"},
{0x00000346, 0x3e0003ff, "divur\t\t%20-24r,%15-19r, %10-14r"},
{0x0c0000a4, 0x3e0003ff, "drte"},
{0x00e0, 0xffe1, "disint!"},
{0x00e1, 0xffe1, "enint!"},
{0x00000058, 0x3e0003ff, "extsb\t\t%20-24r, %15-19r"},
{0x00000059, 0x3e0003ff, "extsb.c\t\t%20-24r, %15-19r"},
{0x0000005a, 0x3e0003ff, "extsh\t\t%20-24r, %15-19r"},
@ -248,8 +232,6 @@ static struct score_opcode score_opcodes[] =
{0x0000005e, 0x3e0003ff, "extzh\t\t%20-24r, %15-19r"},
{0x0000005f, 0x3e0003ff, "extzh.c\t\t%20-24r, %15-19r"},
{0x04000001, 0x3e000001, "jl\t\t%j"},
{0x00003001, 0x00007001, "jl!\t\t%j" },
{0x00003000, 0x00007001, "j!\t\t%j" },
{0x04000000, 0x3e000001, "j\t\t%j"},
{0x26000000, 0x3e000000, "lb\t\t%20-24r, [%15-19r, %0-14i]"},
{0x2c000000, 0x3e000000, "lbu\t\t%20-24r, [%15-19r, %0-14i]"},
@ -257,41 +239,41 @@ static struct score_opcode score_opcodes[] =
{0x06000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0e000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200b, 0x0000700f, "lbu!\t\t%8-11r, [%4-7r]"},
{0x00007003, 0x00007007, "lbup!\t\t%8-11r, %3-7d"},
{0x00000060, 0x3e0003ff, "lcb\t\t[%15-19r]+"},
{0x00000062, 0x3e0003ff, "lcw\t\t%20-24r, [%15-19r]+"},
{0x00000066, 0x3e0003ff, "lce\t\t%20-24r, [%15-19r]+"},
{0x0c00000a, 0x3e00001f, "ldc1\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c000012, 0x3e00001f, "ldc2\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c00001a, 0x3e00001f, "ldc3\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x000000000001LL, 0x1c000000001fLL, "ldi48\t\t%37-41r, %5-36i"},
{0x22000000, 0x3e000000, "lh\t\t%20-24r, [%15-19r, %0-14i]"},
{0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x00002009, 0x0000700f, "lh!\t\t%8-11r, [%4-7r]"},
{0x00007001, 0x00007007, "lhp!\t\t%8-11r, %3-7d1"},
{0x020c0000, 0x3e0e0000, "ldi\t\t%20-24r, 0x%1-16x(%1-16i)"},
{0x0a0c0000, 0x3e0e0000, "ldis\t\t%20-24r, 0x%1-16x(%1-16i)"},
{0x00005000, 0x00007000, "ldiu!\t\t%8-11r, %0-7d"},
{0x00006400, 0x00007c00, "ldiu!\t\t%5-9r, %0-4d"},
{0x00000032, 0x3e0003ff, "ltbw\t\t%20-24r, [%15-19r, %10-14r]"},
{0x00000132, 0x3e0003ff, "ltbh\t\t%20-24r, [%15-19r, %10-14r]"},
{0x00000332, 0x3e0003ff, "ltbb\t\t%20-24r, [%15-19r, %10-14r]"},
{0x0000000c, 0x3e0003ff, "alw\t\t%20-24r, [%15-19r]"},
{0x20000000, 0x3e000000, "lw\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x00002008, 0x0000700f, "lw!\t\t%8-11r, [%4-7r]"},
{0x00007000, 0x00007007, "lwp!\t\t%8-11r, %3-7d2"},
{0x0000100b, 0x0000700f, "madh.fs!\t\t%8-11r, %4-7r"},
{0x0000100a, 0x0000700f, "madl.fs!\t\t%8-11r, %4-7r"},
{0x00001005, 0x0000700f, "madu!\t\t%8-11r, %4-7r"},
{0x00001004, 0x0000700f, "mad.f!\t\t%8-11r, %4-7r"},
{0x00001009, 0x0000700f, "mazh.f!\t\t%8-11r, %4-7r"},
{0x00001008, 0x0000700f, "mazl.f!\t\t%8-11r, %4-7r"},
{0x00001000, 0x00007000, "lw!\t\t%8-11r, [%5-7r,%0-4d2]"},
{0x000000000002LL, 0x1c000000001fLL, "lw48\t\t%37-41r,[0x%7-36w]"},
{0x00007b00, 0x00007f00, "madh.fs!\t\t%8-11r, %4-7r"},
{0x00007a00, 0x00007f00, "madl.fs!\t\t%8-11r, %4-7r"},
{0x00007500, 0x00007f00, "madu!\t\t%8-11r, %4-7r"},
{0x00007400, 0x00007f00, "mad.f!\t\t%8-11r, %4-7r"},
{0x00007900, 0x00007f00, "mazh.f!\t\t%8-11r, %4-7r"},
{0x00007800, 0x00007f00, "mazl.f!\t\t%8-11r, %4-7r"},
{0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"},
{0x00001001, 0x00007f0f, "mfcel!\t\t%4-7r"},
{0x00007100, 0x00007ff0, "mfcel!\t\t%4-7r"},
{0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"},
{0x00001101, 0x00007f0f, "mfceh!\t\t%4-7r"},
{0x00007110, 0x00007ff0, "mfceh!\t\t%4-7r"},
{0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"},
{0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"},
{0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"},
@ -302,18 +284,21 @@ static struct score_opcode score_opcodes[] =
{0x0c00000f, 0x3e00001f, "mfcc1\t\t%20-24r, c%15-19r"},
{0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"},
{0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"},
{0x00000002, 0x0000700f, "mhfl!\t\t%8-11R, %4-7r"},
{0x00000001, 0x0000700f, "mlfh!\t\t%8-11r, %4-7R"},
{0x00001006, 0x0000700f, "msb.f!\t\t%8-11r, %4-7r"},
{0x0000100f, 0x0000700f, "msbh.fs!\t\t%8-11r, %4-7r"},
{0x0000100e, 0x0000700f, "msbl.fs!\t\t%8-11r, %4-7r"},
{0x00001007, 0x0000700f, "msbu!\t\t%8-11r, %4-7r"},
{0x0000100d, 0x0000700f, "mszh.f!\t\t%8-11r, %4-7r"},
{0x0000100c, 0x0000700f, "mszl.f!\t\t%8-11r, %4-7r"},
/* confilct: push! mhfl!. */
{0x00000040, 0x00007fe0, "pop!\t\t%0-4r"},
{0x00000060, 0x00007fe0, "push!\t\t%0-4r"},
{0x00006800, 0x00007c00, "rpop!\t\t%5-9r, %0-4d"},
{0x00006c00, 0x00007c00, "rpush!\t\t%5-9r, %0-4d"},
{0x00007600, 0x00007f00, "msb.f!\t\t%8-11r, %4-7r"},
{0x00007f00, 0x00007f00, "msbh.fs!\t\t%8-11r, %4-7r"},
{0x00007e00, 0x00007f00, "msbl.fs!\t\t%8-11r, %4-7r"},
{0x00007700, 0x00007f00, "msbu!\t\t%8-11r, %4-7r"},
{0x00007d00, 0x00007f00, "mszh.f!\t\t%8-11r, %4-7r"},
{0x00007c00, 0x00007f00, "mszl.f!\t\t%8-11r, %4-7r"},
{0x0000044a, 0x3e007fff, "mtcel\t\t%20-24r"},
{0x00001000, 0x00007f0f, "mtcel!\t\t%4-7r"},
{0x00007000, 0x00007ff0, "mtcel!\t\t%4-7r"},
{0x0000084a, 0x3e007fff, "mtceh\t\t%20-24r"},
{0x00001100, 0x00007f0f, "mtceh!\t\t%4-7r"},
{0x00007010, 0x00007ff0, "mtceh!\t\t%4-7r"},
{0x00000c4a, 0x3e007fff, "mtcehl\t\t%20-24r, %15-19r"},
{0x0000004a, 0x3e0003ff, "mtce\t\t%20-24r, er%10-14d"},
{0x00000052, 0x3e0003ff, "mtsr\t\t%15-19r, sr%10-14d"},
@ -325,13 +310,22 @@ static struct score_opcode score_opcodes[] =
{0x0c000016, 0x3e00001f, "mtcc2\t\t%20-24r, c%15-19r"},
{0x0c00001e, 0x3e00001f, "mtcc3\t\t%20-24r, c%15-19r"},
{0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"},
{0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"},
{0x00000140, 0x3e0003ff, "mulr.l\t\t%20-24r,%15-19r, %10-14r"},
{0x00000240, 0x3e0003ff, "mulr.h\t\t%20-24r,%15-19r, %10-14r"},
{0x00000340, 0x3e0003ff, "mulr\t\t%20-24r,%15-19r, %10-14r"},
{0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"},
{0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
{0x00001002, 0x0000700f, "mul.f!\t\t%8-11r, %4-7r"},
{0x00000141, 0x3e0003ff, "mulr.lf\t\t%20-24r,%15-19r, %10-14r"},
{0x00000241, 0x3e0003ff, "mulr.hf\t\t%20-24r,%15-19r, %10-14r"},
{0x00000341, 0x3e0003ff, "mulr.f\t\t%20-24r,%15-19r, %10-14r"},
{0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"},
{0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
{0x00007200, 0x00007f00, "mul.f!\t\t%8-11r, %4-7r"},
{0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"},
{0x00000142, 0x3e0003ff, "mulur.l\t\t%20-24r,%15-19r, %10-14r"},
{0x00000242, 0x3e0003ff, "mulur.h\t\t%20-24r,%15-19r, %10-14r"},
{0x00000342, 0x3e0003ff, "mulur\t\t%20-24r,%15-19r, %10-14r"},
{0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"},
{0x00001003, 0x0000700f, "mulu!\t\t%8-11r, %4-7r"},
{0x00007300, 0x00007f00, "mulu!\t\t%8-11r, %4-7r"},
{0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"},
{0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"},
{0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"},
@ -347,29 +341,25 @@ static struct score_opcode score_opcodes[] =
{0x00003056, 0x3e007fff, "mvvs\t\t%20-24r, %15-19r"},
{0x00003456, 0x3e007fff, "mvvc\t\t%20-24r, %15-19r"},
{0x00003c56, 0x3e007fff, "mv\t\t%20-24r, %15-19r"},
{0x00000003, 0x0000700f, "mv!\t\t%8-11r, %4-7r"},
{0x0000001e, 0x3e0003ff, "neg\t\t%20-24r, %10-14r" },
{0x0000001f, 0x3e0003ff, "neg.c\t\t%20-24r, %10-14r" },
{0x00002002, 0x0000700f, "neg!\t\t%8-11r, %4-7r"},
{0x00000000, 0x3e0003ff, "nop" },
{0x00000024, 0x3e0003ff, "not\t\t%20-24r, %15-19r" },
{0x00000025, 0x3e0003ff, "not.c\t\t%20-24r, %15-19r" },
{0x00000000, 0x0000700f, "nop!" },
{0x00002006, 0x0000700f, "not!\t\t%8-11r, %4-7r"},
{0x00004000, 0x00007c00, "mv!\t\t%5-9r, %0-4r"},
{0x0000001e, 0x3e0003ff, "neg\t\t%20-24r, %10-14r"},
{0x0000001f, 0x3e0003ff, "neg.c\t\t%20-24r, %10-14r"},
{0x00000000, 0x3e0003ff, "nop"},
{0x00000024, 0x3e0003ff, "not\t\t%20-24r, %15-19r"},
{0x00000025, 0x3e0003ff, "not.c\t\t%20-24r, %15-19r"},
{0x00000000, 0x00007fff, "nop!"},
{0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"},
{0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"},
{0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
{0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
{0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
{0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
{0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"},
{0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"},
{0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"},
{0x1a000001, 0x3e000001, "orri.c\t\t%20-24r, %15-19r, 0x%1-14x"},
{0x00002005, 0x0000700f, "or!\t\t%8-11r, %4-7r"},
{0x00004a00, 0x00007f00, "or!\t\t%4-7r, %0-3r"},
{0x040000000002LL, 0x1c0000000003LL, "orri48\t\t%38-41r,%34-37r, 0x%2-33x"},
{0x040000000003LL, 0x1c0000000003LL, "orri48.c\t\t%38-41r,%34-37r, 0x%2-33x"},
{0x0000000a, 0x3e0003ff, "pflush"},
{0x0000208a, 0x0000708f, "pop!\t\t%8-11R, [%4-6r]"},
{0x0000200a, 0x0000700f, "pop!\t\t%8-11r, [%4-7r]"},
{0x0000208e, 0x0000708f, "push!\t\t%8-11R, [%4-6r]"},
{0x0000200e, 0x0000700f, "push!\t\t%8-11r, [%4-7r]"},
{0x00000038, 0x3e0003ff, "ror\t\t%20-24r, %15-19r, %10-14r"},
{0x00000039, 0x3e0003ff, "ror.c\t\t%20-24r, %15-19r, %10-14r"},
{0x0000003b, 0x3e0003ff, "rorc.c\t\t%20-24r, %15-19r, %10-14r"},
@ -382,30 +372,26 @@ static struct score_opcode score_opcodes[] =
{0x0000007c, 0x3e0003ff, "roli\t\t%20-24r, %15-19r, %10-14d"},
{0x0000007d, 0x3e0003ff, "roli.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0000007f, 0x3e0003ff, "rolic.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0c000084, 0x3e0003ff, "rte" },
{0x0c000084, 0x3e0003ff, "rte"},
{0x2e000000, 0x3e000000, "sb\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200f, 0x0000700f, "sb!\t\t%8-11r, [%4-7r]"},
{0x00007007, 0x00007007, "sbp!\t\t%8-11r, %3-7d"},
{0x0000000e, 0x3e0003ff, "asw\t\t%20-24r, [%15-19r]"},
{0x00000068, 0x3e0003ff, "scb\t\t%20-24r, [%15-19r]+"},
{0x0000006a, 0x3e0003ff, "scw\t\t%20-24r, [%15-19r]+"},
{0x0000006e, 0x3e0003ff, "sce\t\t[%15-19r]+"},
{0x00000006, 0x3e0003ff, "sdbbp\t\t%15-19d"},
{0x00006002, 0x00007007, "sdbbp!\t\t%3-7d"},
{0x00000020, 0x00007fe0, "sdbbp!\t\t%0-4d"},
{0x000000000000LL, 0x1c000000001fLL, "sdbbp48\t\t%5-9d"},
{0x2a000000, 0x3e000000, "sh\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200d, 0x0000700f, "sh!\t\t%8-11r, [%4-7r]"},
{0x00007005, 0x00007007, "shp!\t\t%8-11r, %3-7d1"},
{0x0c0000c4, 0x3e0003ff, "sleep" },
{0x0c0000c4, 0x3e0003ff, "sleep"},
{0x00000030, 0x3e0003ff, "sll\t\t%20-24r, %15-19r, %10-14r"},
{0x00000031, 0x3e0003ff, "sll.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000070, 0x3e0003ff, "slli\t\t%20-24r, %15-19r, %10-14d"},
{0x00000071, 0x3e0003ff, "slli.c\t\t%20-24r, %15-19r, %10-14d"},
{0x00000008, 0x0000700f, "sll!\t\t%8-11r, %4-7r"},
{0x00006001, 0x00007007, "slli!\t\t%8-11r, %3-7d"},
{0x00005800, 0x00007e00, "slli!\t\t%5-8r, %0-4d"},
{0x00000034, 0x3e0003ff, "srl\t\t%20-24r, %15-19r, %10-14r"},
{0x00000035, 0x3e0003ff, "srl.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000036, 0x3e0003ff, "sra\t\t%20-24r, %15-19r, %10-14r"},
@ -414,9 +400,7 @@ static struct score_opcode score_opcodes[] =
{0x00000075, 0x3e0003ff, "srli.c\t\t%20-24r, %15-19r, %10-14d"},
{0x00000076, 0x3e0003ff, "srai\t\t%20-24r, %15-19r, %10-14d"},
{0x00000077, 0x3e0003ff, "srai.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0000000a, 0x0000700f, "srl!\t\t%8-11r, %4-7r"},
{0x00006003, 0x00007007, "srli!\t\t%8-11r, %3-7d"},
{0x0000000b, 0x0000700f, "sra!\t\t%8-11r, %4-7r"},
{0x00005a00, 0x00007e00, "srli!\t\t%5-8r, %0-4d"},
{0x0c00000b, 0x3e00001f, "stc1\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c000013, 0x3e00001f, "stc2\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c00001b, 0x3e00001f, "stc3\t\tc%15-19r, [%20-24r, %5-14i]"},
@ -424,44 +408,30 @@ static struct score_opcode score_opcodes[] =
{0x00000015, 0x3e0003ff, "sub.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000016, 0x3e0003ff, "subc\t\t%20-24r, %15-19r, %10-14r"},
{0x00000017, 0x3e0003ff, "subc.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00002001, 0x0000700f, "sub!\t\t%8-11r, %4-7r"},
{0x00006080, 0x00007087, "subei!\t\t%8-11r, %3-6d"},
{0x00004900, 0x00007f00, "sub!\t\t%4-7r, %0-3r"},
{0x28000000, 0x3e000000, "sw\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200c, 0x0000700f, "sw!\t\t%8-11r, [%4-7r]"},
{0x00007004, 0x00007007, "swp!\t\t%8-11r, %3-7d2"},
{0x00002000, 0x00007000, "sw!\t\t%8-11r, [%5-7r,%0-4d2]"},
{0x000000000003LL, 0x1c000000001fLL, "sw48\t\t%37-41r, [0x%7-36w]"},
{0x00000002, 0x3e0003ff, "syscall\t\t%10-24d"},
{0x00000054, 0x3e007fff, "tcs" },
{0x00000454, 0x3e007fff, "tcc" },
{0x00003854, 0x3e007fff, "tcnz" },
{0x00000005, 0x00007f0f, "tcs!" },
{0x00000105, 0x00007f0f, "tcc!" },
{0x00000e05, 0x00007f0f, "tcnz!" },
{0x00001054, 0x3e007fff, "teq" },
{0x00000405, 0x00007f0f, "teq!" },
{0x00000854, 0x3e007fff, "tgtu" },
{0x00001854, 0x3e007fff, "tgt" },
{0x00002054, 0x3e007fff, "tge" },
{0x00000205, 0x00007f0f, "tgtu!" },
{0x00000605, 0x00007f0f, "tgt!" },
{0x00000805, 0x00007f0f, "tge!" },
{0x00000c54, 0x3e007fff, "tleu" },
{0x00001c54, 0x3e007fff, "tle" },
{0x00002454, 0x3e007fff, "tlt" },
{0x0c000004, 0x3e0003ff, "stlb" },
{0x0c000024, 0x3e0003ff, "mftlb" },
{0x0c000044, 0x3e0003ff, "mtptlb" },
{0x0c000064, 0x3e0003ff, "mtrtlb" },
{0x00000305, 0x00007f0f, "tleu!" },
{0x00000705, 0x00007f0f, "tle!" },
{0x00000905, 0x00007f0f, "tlt!" },
{0x00002854, 0x3e007fff, "tmi" },
{0x00000a05, 0x00007f0f, "tmi!" },
{0x00001454, 0x3e007fff, "tne" },
{0x00000505, 0x00007f0f, "tne!" },
{0x00002c54, 0x3e007fff, "tpl" },
{0x00000b05, 0x00007f0f, "tpl!" },
{0x00000054, 0x3e007fff, "tcs"},
{0x00000454, 0x3e007fff, "tcc"},
{0x00003854, 0x3e007fff, "tcnz"},
{0x00001054, 0x3e007fff, "teq"},
{0x00000854, 0x3e007fff, "tgtu"},
{0x00001854, 0x3e007fff, "tgt"},
{0x00002054, 0x3e007fff, "tge"},
{0x00000c54, 0x3e007fff, "tleu"},
{0x00001c54, 0x3e007fff, "tle"},
{0x00002454, 0x3e007fff, "tlt"},
{0x0c000004, 0x3e0003ff, "stlb"},
{0x0c000024, 0x3e0003ff, "mftlb"},
{0x0c000044, 0x3e0003ff, "mtptlb"},
{0x0c000064, 0x3e0003ff, "mtrtlb"},
{0x00002854, 0x3e007fff, "tmi"},
{0x00001454, 0x3e007fff, "tne"},
{0x00002c54, 0x3e007fff, "tpl"},
{0x00000004, 0x3e007fff, "trapcs\t\t%15-19d"},
{0x00000404, 0x3e007fff, "trapcc\t\t%15-19d"},
{0x00000804, 0x3e007fff, "trapgtu\t\t%15-19d"},
@ -477,13 +447,9 @@ static struct score_opcode score_opcodes[] =
{0x00003004, 0x3e007fff, "trapvs\t\t%15-19d"},
{0x00003404, 0x3e007fff, "trapvc\t\t%15-19d"},
{0x00003c04, 0x3e007fff, "trap\t\t%15-19d"},
{0x00003c54, 0x3e007fff, "tset" },
{0x00000f05, 0x00007f0f, "tset!" },
{0x00003054, 0x3e007fff, "tvs" },
{0x00003454, 0x3e007fff, "tvc" },
{0x00000c05, 0x00007f0f, "tvs!" },
{0x00000d05, 0x00007f0f, "tvc!" },
{0x00003c54, 0x3e007fff, "tset"},
{0x00003054, 0x3e007fff, "tvs"},
{0x00003454, 0x3e007fff, "tvc"},
{0x00000026, 0x3e0003ff, "xor\t\t%20-24r, %15-19r, %10-14r"},
{0x00000027, 0x3e0003ff, "xor.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00002007, 0x0000700f, "xor!\t\t%8-11r, %4-7r"}
};

972
opcodes/score7-dis.c Normal file
View File

@ -0,0 +1,972 @@
/* Instruction printing code for Score
Copyright 2009 Free Software Foundation, Inc.
Contributed by:
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
#define DEFINE_TABLE
#include "opintl.h"
#include "bfd.h"
/* FIXME: This shouldn't be done here. */
#include "elf-bfd.h"
#include "elf/internal.h"
#include "elf/score.h"
#ifndef streq
#define streq(a,b) (strcmp ((a), (b)) == 0)
#endif
#ifndef strneq
#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
#endif
#ifndef NUM_ELEM
#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
#endif
struct score_opcode
{
unsigned long value;
unsigned long mask; /* Recognise instruction if (op & mask) == value. */
char *assembler; /* Disassembly string. */
};
/* Note: There is a partial ordering in this table - it must be searched from
the top to obtain a correct match. */
static struct score_opcode score_opcodes[] =
{
/* Score Instructions. */
{0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"},
{0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
{0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"},
{0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"},
{0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"},
{0x00000012, 0x3e0003ff, "addc\t\t%20-24r, %15-19r, %10-14r"},
{0x00000013, 0x3e0003ff, "addc.c\t\t%20-24r, %15-19r, %10-14r"},
{0x02000000, 0x3e0e0001, "addi\t\t%20-24r, %1-16i"},
{0x02000001, 0x3e0e0001, "addi.c\t\t%20-24r, %1-16i"},
{0x0a000000, 0x3e0e0001, "addis\t\t%20-24r, %1-16d(0x%1-16x)"},
{0x0a000001, 0x3e0e0001, "addis.c\t\t%20-24r, %1-16d(0x%1-16x)"},
{0x10000000, 0x3e000001, "addri\t\t%20-24r, %15-19r, %1-14i"},
{0x10000001, 0x3e000001, "addri.c\t\t%20-24r, %15-19r, %1-14i"},
{0x00000009, 0x0000700f, "addc!\t\t%8-11r, %4-7r"},
{0x00002000, 0x0000700f, "add!\t\t%8-11r, %4-7r"},
{0x00006000, 0x00007087, "addei!\t\t%8-11r, %3-6d"},
{0x00000020, 0x3e0003ff, "and\t\t%20-24r, %15-19r, %10-14r"},
{0x00000021, 0x3e0003ff, "and.c\t\t%20-24r, %15-19r, %10-14r"},
{0x02080000, 0x3e0e0001, "andi\t\t%20-24r, 0x%1-16x"},
{0x02080001, 0x3e0e0001, "andi.c\t\t%20-24r, 0x%1-16x"},
{0x0a080000, 0x3e0e0001, "andis\t\t%20-24r, 0x%1-16x"},
{0x0a080001, 0x3e0e0001, "andis.c\t\t%20-24r, 0x%1-16x"},
{0x18000000, 0x3e000001, "andri\t\t%20-24r, %15-19r, 0x%1-14x"},
{0x18000001, 0x3e000001, "andri.c\t\t%20-24r, %15-19r,0x%1-14x"},
{0x00002004, 0x0000700f, "and!\t\t%8-11r, %4-7r"},
{0x08000000, 0x3e007c01, "bcs\t\t%b"},
{0x08000400, 0x3e007c01, "bcc\t\t%b"},
{0x08003800, 0x3e007c01, "bcnz\t\t%b"},
{0x08000001, 0x3e007c01, "bcsl\t\t%b"},
{0x08000401, 0x3e007c01, "bccl\t\t%b"},
{0x08003801, 0x3e007c01, "bcnzl\t\t%b"},
{0x00004000, 0x00007f00, "bcs!\t\t%b"},
{0x00004100, 0x00007f00, "bcc!\t\t%b"},
{0x00004e00, 0x00007f00, "bcnz!\t\t%b"},
{0x08001000, 0x3e007c01, "beq\t\t%b"},
{0x08001001, 0x3e007c01, "beql\t\t%b"},
{0x00004400, 0x00007f00, "beq!\t\t%b"},
{0x08000800, 0x3e007c01, "bgtu\t\t%b"},
{0x08001800, 0x3e007c01, "bgt\t\t%b"},
{0x08002000, 0x3e007c01, "bge\t\t%b"},
{0x08000801, 0x3e007c01, "bgtul\t\t%b"},
{0x08001801, 0x3e007c01, "bgtl\t\t%b"},
{0x08002001, 0x3e007c01, "bgel\t\t%b"},
{0x00004200, 0x00007f00, "bgtu!\t\t%b"},
{0x00004600, 0x00007f00, "bgt!\t\t%b"},
{0x00004800, 0x00007f00, "bge!\t\t%b"},
{0x00000029, 0x3e0003ff, "bitclr.c\t%20-24r, %15-19r, 0x%10-14x"},
{0x0000002b, 0x3e0003ff, "bitset.c\t%20-24r, %15-19r, 0x%10-14x"},
{0x0000002d, 0x3e0003ff, "bittst.c\t%15-19r, 0x%10-14x"},
{0x0000002f, 0x3e0003ff, "bittgl.c\t%20-24r, %15-19r, 0x%10-14x"},
{0x00006004, 0x00007007, "bitclr!\t\t%8-11r, 0x%3-7x"},
{0x3800000c, 0x3e0003ff, "bitrev\t\t%20-24r, %15-19r,%10-14r"},
{0x00006005, 0x00007007, "bitset!\t\t%8-11r, 0x%3-7x"},
{0x00006006, 0x00007007, "bittst!\t\t%8-11r, 0x%3-7x"},
{0x00006007, 0x00007007, "bittgl!\t\t%8-11r, 0x%3-7x"},
{0x08000c00, 0x3e007c01, "bleu\t\t%b"},
{0x08001c00, 0x3e007c01, "ble\t\t%b"},
{0x08002400, 0x3e007c01, "blt\t\t%b"},
{0x08000c01, 0x3e007c01, "bleul\t\t%b"},
{0x08001c01, 0x3e007c01, "blel\t\t%b"},
{0x08002401, 0x3e007c01, "bltl\t\t%b"},
{0x08003c01, 0x3e007c01, "bl\t\t%b"},
{0x00004300, 0x00007f00, "bleu!\t\t%b"},
{0x00004700, 0x00007f00, "ble!\t\t%b"},
{0x00004900, 0x00007f00, "blt!\t\t%b"},
{0x08002800, 0x3e007c01, "bmi\t\t%b"},
{0x08002801, 0x3e007c01, "bmil\t\t%b"},
{0x00004a00, 0x00007f00, "bmi!\t\t%b"},
{0x08001400, 0x3e007c01, "bne\t\t%b"},
{0x08001401, 0x3e007c01, "bnel\t\t%b"},
{0x00004500, 0x00007f00, "bne!\t\t%b"},
{0x08002c00, 0x3e007c01, "bpl\t\t%b"},
{0x08002c01, 0x3e007c01, "bpll\t\t%b"},
{0x00004b00, 0x00007f00, "bpl!\t\t%b"},
{0x00000008, 0x3e007fff, "brcs\t\t%15-19r"},
{0x00000408, 0x3e007fff, "brcc\t\t%15-19r"},
{0x00000808, 0x3e007fff, "brgtu\t\t%15-19r"},
{0x00000c08, 0x3e007fff, "brleu\t\t%15-19r"},
{0x00001008, 0x3e007fff, "breq\t\t%15-19r"},
{0x00001408, 0x3e007fff, "brne\t\t%15-19r"},
{0x00001808, 0x3e007fff, "brgt\t\t%15-19r"},
{0x00001c08, 0x3e007fff, "brle\t\t%15-19r"},
{0x00002008, 0x3e007fff, "brge\t\t%15-19r"},
{0x00002408, 0x3e007fff, "brlt\t\t%15-19r"},
{0x00002808, 0x3e007fff, "brmi\t\t%15-19r"},
{0x00002c08, 0x3e007fff, "brpl\t\t%15-19r"},
{0x00003008, 0x3e007fff, "brvs\t\t%15-19r"},
{0x00003408, 0x3e007fff, "brvc\t\t%15-19r"},
{0x00003808, 0x3e007fff, "brcnz\t\t%15-19r"},
{0x00003c08, 0x3e007fff, "br\t\t%15-19r"},
{0x00000009, 0x3e007fff, "brcsl\t\t%15-19r"},
{0x00000409, 0x3e007fff, "brccl\t\t%15-19r"},
{0x00000809, 0x3e007fff, "brgtul\t\t%15-19r"},
{0x00000c09, 0x3e007fff, "brleul\t\t%15-19r"},
{0x00001009, 0x3e007fff, "breql\t\t%15-19r"},
{0x00001409, 0x3e007fff, "brnel\t\t%15-19r"},
{0x00001809, 0x3e007fff, "brgtl\t\t%15-19r"},
{0x00001c09, 0x3e007fff, "brlel\t\t%15-19r"},
{0x00002009, 0x3e007fff, "brgel\t\t%15-19r"},
{0x00002409, 0x3e007fff, "brltl\t\t%15-19r"},
{0x00002809, 0x3e007fff, "brmil\t\t%15-19r"},
{0x00002c09, 0x3e007fff, "brpll\t\t%15-19r"},
{0x00003009, 0x3e007fff, "brvsl\t\t%15-19r"},
{0x00003409, 0x3e007fff, "brvcl\t\t%15-19r"},
{0x00003809, 0x3e007fff, "brcnzl\t\t%15-19r"},
{0x00003c09, 0x3e007fff, "brl\t\t%15-19r"},
{0x00000004, 0x00007f0f, "brcs!\t\t%4-7r"},
{0x00000104, 0x00007f0f, "brcc!\t\t%4-7r"},
{0x00000204, 0x00007f0f, "brgtu!\t\t%4-7r"},
{0x00000304, 0x00007f0f, "brleu!\t\t%4-7r"},
{0x00000404, 0x00007f0f, "breq!\t\t%4-7r"},
{0x00000504, 0x00007f0f, "brne!\t\t%4-7r"},
{0x00000604, 0x00007f0f, "brgt!\t\t%4-7r"},
{0x00000704, 0x00007f0f, "brle!\t\t%4-7r"},
{0x00000804, 0x00007f0f, "brge!\t\t%4-7r"},
{0x00000904, 0x00007f0f, "brlt!\t\t%4-7r"},
{0x00000a04, 0x00007f0f, "brmi!\t\t%4-7r"},
{0x00000b04, 0x00007f0f, "brpl!\t\t%4-7r"},
{0x00000c04, 0x00007f0f, "brvs!\t\t%4-7r"},
{0x00000d04, 0x00007f0f, "brvc!\t\t%4-7r"},
{0x00000e04, 0x00007f0f, "brcnz!\t\t%4-7r"},
{0x00000f04, 0x00007f0f, "br!\t\t%4-7r"},
{0x0000000c, 0x00007f0f, "brcsl!\t\t%4-7r"},
{0x0000010c, 0x00007f0f, "brccl!\t\t%4-7r"},
{0x0000020c, 0x00007f0f, "brgtul!\t\t%4-7r"},
{0x0000030c, 0x00007f0f, "brleul!\t\t%4-7r"},
{0x0000040c, 0x00007f0f, "breql!\t\t%4-7r"},
{0x0000050c, 0x00007f0f, "brnel!\t\t%4-7r"},
{0x0000060c, 0x00007f0f, "brgtl!\t\t%4-7r"},
{0x0000070c, 0x00007f0f, "brlel!\t\t%4-7r"},
{0x0000080c, 0x00007f0f, "brgel!\t\t%4-7r"},
{0x0000090c, 0x00007f0f, "brltl!\t\t%4-7r"},
{0x00000a0c, 0x00007f0f, "brmil!\t\t%4-7r"},
{0x00000b0c, 0x00007f0f, "brpll!\t\t%4-7r"},
{0x00000c0c, 0x00007f0f, "brvsl!\t\t%4-7r"},
{0x00000d0c, 0x00007f0f, "brvcl!\t\t%4-7r"},
{0x00000e0c, 0x00007f0f, "brcnzl!\t\t%4-7r"},
{0x00000f0c, 0x00007f0f, "brl!\t\t%4-7r"},
{0x08003000, 0x3e007c01, "bvs\t\t%b"},
{0x08003400, 0x3e007c01, "bvc\t\t%b"},
{0x08003001, 0x3e007c01, "bvsl\t\t%b"},
{0x08003401, 0x3e007c01, "bvcl\t\t%b"},
{0x00004c00, 0x00007f00, "bvs!\t\t%b"},
{0x00004d00, 0x00007f00, "bvc!\t\t%b"},
{0x00004f00, 0x00007f00, "b!\t\t%b"},
{0x08003c00, 0x3e007c01, "b\t\t%b"},
{0x30000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30200000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30300000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30400000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30900000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"},
{0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
{0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"},
{0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
{0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"},
{0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"},
{0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
{0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
{0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
{0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
{0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
{0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
{0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
{0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
{0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
{0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"},
{0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
{0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
{0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
{0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"},
{0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
{0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
{0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
{0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
{0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
{0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
{0x3800000d, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
{0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"},
{0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"},
{0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"},
{0x00300019, 0x3ff003ff, "cmp.c\t\t%15-19r, %10-14r"},
{0x0000001b, 0x3ff07fff, "cmpzteq.c\t%15-19r"},
{0x0010001b, 0x3ff07fff, "cmpztmi.c\t%15-19r"},
{0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"},
{0x02040001, 0x3e0e0001, "cmpi.c\t\t%20-24r, %1-16i"},
{0x00002003, 0x0000700f, "cmp!\t\t%8-11r, %4-7r"},
{0x0c00000c, 0x3e00001f, "cop1\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
{0x0c000014, 0x3e00001f, "cop2\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
{0x0c00001c, 0x3e00001f, "cop3\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
{0x00000044, 0x3e0003ff, "div\t\t%15-19r, %10-14r"},
{0x00000046, 0x3e0003ff, "divu\t\t%15-19r, %10-14r"},
{0x0c0000a4, 0x3e0003ff, "drte"},
{0x00000058, 0x3e0003ff, "extsb\t\t%20-24r, %15-19r"},
{0x00000059, 0x3e0003ff, "extsb.c\t\t%20-24r, %15-19r"},
{0x0000005a, 0x3e0003ff, "extsh\t\t%20-24r, %15-19r"},
{0x0000005b, 0x3e0003ff, "extsh.c\t\t%20-24r, %15-19r"},
{0x0000005c, 0x3e0003ff, "extzb\t\t%20-24r, %15-19r"},
{0x0000005d, 0x3e0003ff, "extzb.c\t\t%20-24r, %15-19r"},
{0x0000005e, 0x3e0003ff, "extzh\t\t%20-24r, %15-19r"},
{0x0000005f, 0x3e0003ff, "extzh.c\t\t%20-24r, %15-19r"},
{0x04000001, 0x3e000001, "jl\t\t%j"},
{0x00003001, 0x00007001, "jl!\t\t%j"},
{0x00003000, 0x00007001, "j!\t\t%j"},
{0x04000000, 0x3e000001, "j\t\t%j"},
{0x26000000, 0x3e000000, "lb\t\t%20-24r, [%15-19r, %0-14i]"},
{0x2c000000, 0x3e000000, "lbu\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x06000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0e000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200b, 0x0000700f, "lbu!\t\t%8-11r, [%4-7r]"},
{0x00007003, 0x00007007, "lbup!\t\t%8-11r, %3-7d"},
{0x00000060, 0x3e0003ff, "lcb\t\t[%15-19r]+"},
{0x00000062, 0x3e0003ff, "lcw\t\t%20-24r, [%15-19r]+"},
{0x00000066, 0x3e0003ff, "lce\t\t%20-24r, [%15-19r]+"},
{0x0c00000a, 0x3e00001f, "ldc1\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c000012, 0x3e00001f, "ldc2\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c00001a, 0x3e00001f, "ldc3\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x22000000, 0x3e000000, "lh\t\t%20-24r, [%15-19r, %0-14i]"},
{0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x00002009, 0x0000700f, "lh!\t\t%8-11r, [%4-7r]"},
{0x00007001, 0x00007007, "lhp!\t\t%8-11r, %3-7d1"},
{0x020c0000, 0x3e0e0000, "ldi\t\t%20-24r, 0x%1-16x(%1-16i)"},
{0x0a0c0000, 0x3e0e0000, "ldis\t\t%20-24r, 0x%1-16x(%1-16i)"},
{0x00005000, 0x00007000, "ldiu!\t\t%8-11r, %0-7d"},
{0x0000000c, 0x3e0003ff, "alw\t\t%20-24r, [%15-19r]"},
{0x20000000, 0x3e000000, "lw\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x00002008, 0x0000700f, "lw!\t\t%8-11r, [%4-7r]"},
{0x00007000, 0x00007007, "lwp!\t\t%8-11r, %3-7d2"},
{0x0000100b, 0x0000700f, "madh.fs!\t\t%8-11r, %4-7r"},
{0x0000100a, 0x0000700f, "madl.fs!\t\t%8-11r, %4-7r"},
{0x00001005, 0x0000700f, "madu!\t\t%8-11r, %4-7r"},
{0x00001004, 0x0000700f, "mad.f!\t\t%8-11r, %4-7r"},
{0x00001009, 0x0000700f, "mazh.f!\t\t%8-11r, %4-7r"},
{0x00001008, 0x0000700f, "mazl.f!\t\t%8-11r, %4-7r"},
{0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"},
{0x00001001, 0x00007f0f, "mfcel!\t\t%4-7r"},
{0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"},
{0x00001101, 0x00007f0f, "mfceh!\t\t%4-7r"},
{0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"},
{0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"},
{0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"},
{0x0c000001, 0x3e00001f, "mfcr\t\t%20-24r, c%15-19r"},
{0x0c000009, 0x3e00001f, "mfc1\t\t%20-24r, c%15-19r"},
{0x0c000011, 0x3e00001f, "mfc2\t\t%20-24r, c%15-19r"},
{0x0c000019, 0x3e00001f, "mfc3\t\t%20-24r, c%15-19r"},
{0x0c00000f, 0x3e00001f, "mfcc1\t\t%20-24r, c%15-19r"},
{0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"},
{0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"},
{0x00000002, 0x0000700f, "mhfl!\t\t%8-11R, %4-7r"},
{0x00000001, 0x0000700f, "mlfh!\t\t%8-11r, %4-7R"},
{0x00001006, 0x0000700f, "msb.f!\t\t%8-11r, %4-7r"},
{0x0000100f, 0x0000700f, "msbh.fs!\t\t%8-11r, %4-7r"},
{0x0000100e, 0x0000700f, "msbl.fs!\t\t%8-11r, %4-7r"},
{0x00001007, 0x0000700f, "msbu!\t\t%8-11r, %4-7r"},
{0x0000100d, 0x0000700f, "mszh.f!\t\t%8-11r, %4-7r"},
{0x0000100c, 0x0000700f, "mszl.f!\t\t%8-11r, %4-7r"},
{0x0000044a, 0x3e007fff, "mtcel\t\t%20-24r"},
{0x00001000, 0x00007f0f, "mtcel!\t\t%4-7r"},
{0x0000084a, 0x3e007fff, "mtceh\t\t%20-24r"},
{0x00001100, 0x00007f0f, "mtceh!\t\t%4-7r"},
{0x00000c4a, 0x3e007fff, "mtcehl\t\t%20-24r, %15-19r"},
{0x0000004a, 0x3e0003ff, "mtce\t\t%20-24r, er%10-14d"},
{0x00000052, 0x3e0003ff, "mtsr\t\t%15-19r, sr%10-14d"},
{0x0c000000, 0x3e00001f, "mtcr\t\t%20-24r, c%15-19r"},
{0x0c000008, 0x3e00001f, "mtc1\t\t%20-24r, c%15-19r"},
{0x0c000010, 0x3e00001f, "mtc2\t\t%20-24r, c%15-19r"},
{0x0c000018, 0x3e00001f, "mtc3\t\t%20-24r, c%15-19r"},
{0x0c00000e, 0x3e00001f, "mtcc1\t\t%20-24r, c%15-19r"},
{0x0c000016, 0x3e00001f, "mtcc2\t\t%20-24r, c%15-19r"},
{0x0c00001e, 0x3e00001f, "mtcc3\t\t%20-24r, c%15-19r"},
{0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"},
{0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"},
{0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"},
{0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
{0x00001002, 0x0000700f, "mul.f!\t\t%8-11r, %4-7r"},
{0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"},
{0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"},
{0x00001003, 0x0000700f, "mulu!\t\t%8-11r, %4-7r"},
{0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"},
{0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"},
{0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"},
{0x00000c56, 0x3e007fff, "mvleu\t\t%20-24r, %15-19r"},
{0x00001056, 0x3e007fff, "mveq\t\t%20-24r, %15-19r"},
{0x00001456, 0x3e007fff, "mvne\t\t%20-24r, %15-19r"},
{0x00001856, 0x3e007fff, "mvgt\t\t%20-24r, %15-19r"},
{0x00001c56, 0x3e007fff, "mvle\t\t%20-24r, %15-19r"},
{0x00002056, 0x3e007fff, "mvge\t\t%20-24r, %15-19r"},
{0x00002456, 0x3e007fff, "mvlt\t\t%20-24r, %15-19r"},
{0x00002856, 0x3e007fff, "mvmi\t\t%20-24r, %15-19r"},
{0x00002c56, 0x3e007fff, "mvpl\t\t%20-24r, %15-19r"},
{0x00003056, 0x3e007fff, "mvvs\t\t%20-24r, %15-19r"},
{0x00003456, 0x3e007fff, "mvvc\t\t%20-24r, %15-19r"},
{0x00003c56, 0x3e007fff, "mv\t\t%20-24r, %15-19r"},
{0x00000003, 0x0000700f, "mv!\t\t%8-11r, %4-7r"},
{0x0000001e, 0x3e0003ff, "neg\t\t%20-24r, %10-14r"},
{0x0000001f, 0x3e0003ff, "neg.c\t\t%20-24r, %10-14r"},
{0x00002002, 0x0000700f, "neg!\t\t%8-11r, %4-7r"},
{0x00000000, 0x3e0003ff, "nop"},
{0x00000024, 0x3e0003ff, "not\t\t%20-24r, %15-19r"},
{0x00000025, 0x3e0003ff, "not.c\t\t%20-24r, %15-19r"},
{0x00000000, 0x0000700f, "nop!"},
{0x00002006, 0x0000700f, "not!\t\t%8-11r, %4-7r"},
{0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"},
{0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"},
{0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
{0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
{0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"},
{0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"},
{0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"},
{0x1a000001, 0x3e000001, "orri.c\t\t%20-24r, %15-19r, 0x%1-14x"},
{0x00002005, 0x0000700f, "or!\t\t%8-11r, %4-7r"},
{0x0000000a, 0x3e0003ff, "pflush"},
{0x0000208a, 0x0000708f, "pop!\t\t%8-11R, [%4-6r]"},
{0x0000200a, 0x0000700f, "pop!\t\t%8-11r, [%4-7r]"},
{0x0000208e, 0x0000708f, "push!\t\t%8-11R, [%4-6r]"},
{0x0000200e, 0x0000700f, "push!\t\t%8-11r, [%4-7r]"},
{0x00000038, 0x3e0003ff, "ror\t\t%20-24r, %15-19r, %10-14r"},
{0x00000039, 0x3e0003ff, "ror.c\t\t%20-24r, %15-19r, %10-14r"},
{0x0000003b, 0x3e0003ff, "rorc.c\t\t%20-24r, %15-19r, %10-14r"},
{0x0000003c, 0x3e0003ff, "rol\t\t%20-24r, %15-19r, %10-14r"},
{0x0000003d, 0x3e0003ff, "rol.c\t\t%20-24r, %15-19r, %10-14r"},
{0x0000003f, 0x3e0003ff, "rolc.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000078, 0x3e0003ff, "rori\t\t%20-24r, %15-19r, %10-14d"},
{0x00000079, 0x3e0003ff, "rori.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0000007b, 0x3e0003ff, "roric.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0000007c, 0x3e0003ff, "roli\t\t%20-24r, %15-19r, %10-14d"},
{0x0000007d, 0x3e0003ff, "roli.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0000007f, 0x3e0003ff, "rolic.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0c000084, 0x3e0003ff, "rte"},
{0x2e000000, 0x3e000000, "sb\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200f, 0x0000700f, "sb!\t\t%8-11r, [%4-7r]"},
{0x00007007, 0x00007007, "sbp!\t\t%8-11r, %3-7d"},
{0x0000000e, 0x3e0003ff, "asw\t\t%20-24r, [%15-19r]"},
{0x00000068, 0x3e0003ff, "scb\t\t%20-24r, [%15-19r]+"},
{0x0000006a, 0x3e0003ff, "scw\t\t%20-24r, [%15-19r]+"},
{0x0000006e, 0x3e0003ff, "sce\t\t[%15-19r]+"},
{0x00000006, 0x3e0003ff, "sdbbp\t\t%15-19d"},
{0x00006002, 0x00007007, "sdbbp!\t\t%3-7d"},
{0x2a000000, 0x3e000000, "sh\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200d, 0x0000700f, "sh!\t\t%8-11r, [%4-7r]"},
{0x00007005, 0x00007007, "shp!\t\t%8-11r, %3-7d1"},
{0x0c0000c4, 0x3e0003ff, "sleep"},
{0x00000030, 0x3e0003ff, "sll\t\t%20-24r, %15-19r, %10-14r"},
{0x00000031, 0x3e0003ff, "sll.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000070, 0x3e0003ff, "slli\t\t%20-24r, %15-19r, %10-14d"},
{0x00000071, 0x3e0003ff, "slli.c\t\t%20-24r, %15-19r, %10-14d"},
{0x00000008, 0x0000700f, "sll!\t\t%8-11r, %4-7r"},
{0x00006001, 0x00007007, "slli!\t\t%8-11r, %3-7d"},
{0x00000034, 0x3e0003ff, "srl\t\t%20-24r, %15-19r, %10-14r"},
{0x00000035, 0x3e0003ff, "srl.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000036, 0x3e0003ff, "sra\t\t%20-24r, %15-19r, %10-14r"},
{0x00000037, 0x3e0003ff, "sra.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000074, 0x3e0003ff, "srli\t\t%20-24r, %15-19r, %10-14d"},
{0x00000075, 0x3e0003ff, "srli.c\t\t%20-24r, %15-19r, %10-14d"},
{0x00000076, 0x3e0003ff, "srai\t\t%20-24r, %15-19r, %10-14d"},
{0x00000077, 0x3e0003ff, "srai.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0000000a, 0x0000700f, "srl!\t\t%8-11r, %4-7r"},
{0x00006003, 0x00007007, "srli!\t\t%8-11r, %3-7d"},
{0x0000000b, 0x0000700f, "sra!\t\t%8-11r, %4-7r"},
{0x0c00000b, 0x3e00001f, "stc1\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c000013, 0x3e00001f, "stc2\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c00001b, 0x3e00001f, "stc3\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x00000014, 0x3e0003ff, "sub\t\t%20-24r, %15-19r, %10-14r"},
{0x00000015, 0x3e0003ff, "sub.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000016, 0x3e0003ff, "subc\t\t%20-24r, %15-19r, %10-14r"},
{0x00000017, 0x3e0003ff, "subc.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00002001, 0x0000700f, "sub!\t\t%8-11r, %4-7r"},
{0x00006080, 0x00007087, "subei!\t\t%8-11r, %3-6d"},
{0x28000000, 0x3e000000, "sw\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200c, 0x0000700f, "sw!\t\t%8-11r, [%4-7r]"},
{0x00007004, 0x00007007, "swp!\t\t%8-11r, %3-7d2"},
{0x00000002, 0x3e0003ff, "syscall\t\t%10-24d"},
{0x00000054, 0x3e007fff, "tcs"},
{0x00000454, 0x3e007fff, "tcc"},
{0x00003854, 0x3e007fff, "tcnz"},
{0x00000005, 0x00007f0f, "tcs!"},
{0x00000105, 0x00007f0f, "tcc!"},
{0x00000e05, 0x00007f0f, "tcnz!"},
{0x00001054, 0x3e007fff, "teq"},
{0x00000405, 0x00007f0f, "teq!"},
{0x00000854, 0x3e007fff, "tgtu"},
{0x00001854, 0x3e007fff, "tgt"},
{0x00002054, 0x3e007fff, "tge"},
{0x00000205, 0x00007f0f, "tgtu!"},
{0x00000605, 0x00007f0f, "tgt!"},
{0x00000805, 0x00007f0f, "tge!"},
{0x00000c54, 0x3e007fff, "tleu"},
{0x00001c54, 0x3e007fff, "tle"},
{0x00002454, 0x3e007fff, "tlt"},
{0x0c000004, 0x3e0003ff, "stlb"},
{0x0c000024, 0x3e0003ff, "mftlb"},
{0x0c000044, 0x3e0003ff, "mtptlb"},
{0x0c000064, 0x3e0003ff, "mtrtlb"},
{0x00000305, 0x00007f0f, "tleu!"},
{0x00000705, 0x00007f0f, "tle!"},
{0x00000905, 0x00007f0f, "tlt!"},
{0x00002854, 0x3e007fff, "tmi"},
{0x00000a05, 0x00007f0f, "tmi!"},
{0x00001454, 0x3e007fff, "tne"},
{0x00000505, 0x00007f0f, "tne!"},
{0x00002c54, 0x3e007fff, "tpl"},
{0x00000b05, 0x00007f0f, "tpl!"},
{0x00000004, 0x3e007fff, "trapcs\t\t%15-19d"},
{0x00000404, 0x3e007fff, "trapcc\t\t%15-19d"},
{0x00000804, 0x3e007fff, "trapgtu\t\t%15-19d"},
{0x00000c04, 0x3e007fff, "trapleu\t\t%15-19d"},
{0x00001004, 0x3e007fff, "trapeq\t\t%15-19d"},
{0x00001404, 0x3e007fff, "trapne\t\t%15-19d"},
{0x00001804, 0x3e007fff, "trapgt\t\t%15-19d"},
{0x00001c04, 0x3e007fff, "traple\t\t%15-19d"},
{0x00002004, 0x3e007fff, "trapge\t\t%15-19d"},
{0x00002404, 0x3e007fff, "traplt\t\t%15-19d"},
{0x00002804, 0x3e007fff, "trapmi\t\t%15-19d"},
{0x00002c04, 0x3e007fff, "trappl\t\t%15-19d"},
{0x00003004, 0x3e007fff, "trapvs\t\t%15-19d"},
{0x00003404, 0x3e007fff, "trapvc\t\t%15-19d"},
{0x00003c04, 0x3e007fff, "trap\t\t%15-19d"},
{0x00003c54, 0x3e007fff, "tset"},
{0x00000f05, 0x00007f0f, "tset!"},
{0x00003054, 0x3e007fff, "tvs"},
{0x00003454, 0x3e007fff, "tvc"},
{0x00000c05, 0x00007f0f, "tvs!"},
{0x00000d05, 0x00007f0f, "tvc!"},
{0x00000026, 0x3e0003ff, "xor\t\t%20-24r, %15-19r, %10-14r"},
{0x00000027, 0x3e0003ff, "xor.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00002007, 0x0000700f, "xor!\t\t%8-11r, %4-7r"}
};
typedef struct
{
const char *name;
const char *description;
const char *reg_names[32];
} score_regname;
static score_regname regnames[] =
{
{"gcc", "Select register names used by GCC",
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
"r21", "r22", "r23", "r24", "r25", "r26", "r27", "gp", "r29", "r30", "r31"}},
};
static unsigned int regname_selected = 0;
#define NUM_SCORE_REGNAMES NUM_ELEM (regnames)
#define score_regnames regnames[regname_selected].reg_names
/* s3_s7: opcodes and export prototypes. */
int
s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little);
/* Print one instruction from PC on INFO->STREAM.
Return the size of the instruction. */
static int
print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given)
{
struct score_opcode *insn;
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
for (insn = score_opcodes; insn->assembler; insn++)
{
if ((insn->mask & 0xffff0000) && (given & insn->mask) == insn->value)
{
char *c;
for (c = insn->assembler; *c; c++)
{
if (*c == '%')
{
switch (*++c)
{
case 'j':
{
int target;
if (info->flags & INSN_HAS_RELOC)
pc = 0;
target = (pc & 0xfe000000) | (given & 0x01fffffe);
(*info->print_address_func) (target, info);
}
break;
case 'b':
{
/* Sign-extend a 20-bit number. */
#define SEXT20(x) ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000)
int disp = ((given & 0x01ff8000) >> 5) | (given & 0x3fe);
int target = (pc + SEXT20 (disp));
(*info->print_address_func) (target, info);
}
break;
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
int bitstart = *c++ - '0';
int bitend = 0;
while (*c >= '0' && *c <= '9')
bitstart = (bitstart * 10) + *c++ - '0';
switch (*c)
{
case '-':
c++;
while (*c >= '0' && *c <= '9')
bitend = (bitend * 10) + *c++ - '0';
if (!bitend)
abort ();
switch (*c)
{
case 'r':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
func (stream, "%s", score_regnames[reg]);
}
break;
case 'd':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
func (stream, "%ld", reg);
}
break;
case 'i':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
reg = ((reg ^ (1 << (bitend - bitstart))) -
(1 << (bitend - bitstart)));
if (((given & insn->mask) == 0x0c00000a) /* ldc1 */
|| ((given & insn->mask) == 0x0c000012) /* ldc2 */
|| ((given & insn->mask) == 0x0c00001c) /* ldc3 */
|| ((given & insn->mask) == 0x0c00000b) /* stc1 */
|| ((given & insn->mask) == 0x0c000013) /* stc2 */
|| ((given & insn->mask) == 0x0c00001b)) /* stc3 */
reg <<= 2;
func (stream, "%ld", reg);
}
break;
case 'x':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
func (stream, "%lx", reg);
}
break;
default:
abort ();
}
break;
case '`':
c++;
if ((given & (1 << bitstart)) == 0)
func (stream, "%c", *c);
break;
case '\'':
c++;
if ((given & (1 << bitstart)) != 0)
func (stream, "%c", *c);
break;
default:
abort ();
}
break;
default:
abort ();
}
}
}
else
func (stream, "%c", *c);
}
return 4;
}
}
#if (SCORE_SIMULATOR_ACTIVE)
func (stream, _("<illegal instruction>"));
return 4;
#endif
abort ();
}
static void
print_insn_parallel_sym (struct disassemble_info *info)
{
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
/* 10: 0000 nop!
4 space + 1 colon + 1 space + 1 tab + 8 opcode + 2 space + 1 tab.
FIXME: the space number is not accurate. */
func (stream, "%s", " ||\n \t \t");
}
/* Print one instruction from PC on INFO->STREAM.
Return the size of the instruction. */
static int
print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given)
{
struct score_opcode *insn;
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
given &= 0xffff;
for (insn = score_opcodes; insn->assembler; insn++)
{
if (!(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value)
{
char *c = insn->assembler;
info->bytes_per_chunk = 2;
info->bytes_per_line = 4;
given &= 0xffff;
for (; *c; c++)
{
if (*c == '%')
{
switch (*++c)
{
case 'j':
{
int target;
if (info->flags & INSN_HAS_RELOC)
pc = 0;
target = (pc & 0xfffff000) | (given & 0x00000ffe);
(*info->print_address_func) (target, info);
}
break;
case 'b':
{
/* Sign-extend a 9-bit number. */
#define SEXT9(x) ((((x) & 0x1ff) ^ (~ 0xff)) + 0x100)
int disp = (given & 0xff) << 1;
int target = (pc + SEXT9 (disp));
(*info->print_address_func) (target, info);
}
break;
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
int bitstart = *c++ - '0';
int bitend = 0;
while (*c >= '0' && *c <= '9')
bitstart = (bitstart * 10) + *c++ - '0';
switch (*c)
{
case '-':
{
long reg;
c++;
while (*c >= '0' && *c <= '9')
bitend = (bitend * 10) + *c++ - '0';
if (!bitend)
abort ();
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
switch (*c)
{
case 'R':
func (stream, "%s", score_regnames[reg + 16]);
break;
case 'r':
func (stream, "%s", score_regnames[reg]);
break;
case 'd':
if (*(c + 1) == '\0')
func (stream, "%ld", reg);
else
{
c++;
if (*c == '1')
func (stream, "%ld", reg << 1);
else if (*c == '2')
func (stream, "%ld", reg << 2);
}
break;
case 'x':
if (*(c + 1) == '\0')
func (stream, "%lx", reg);
else
{
c++;
if (*c == '1')
func (stream, "%lx", reg << 1);
else if (*c == '2')
func (stream, "%lx", reg << 2);
}
break;
case 'i':
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
func (stream, "%ld", reg);
break;
default:
abort ();
}
}
break;
case '\'':
c++;
if ((given & (1 << bitstart)) != 0)
func (stream, "%c", *c);
break;
default:
abort ();
}
}
break;
default:
abort ();
}
}
else
func (stream, "%c", *c);
}
return 2;
}
}
#if (SCORE_SIMULATOR_ACTIVE)
func (stream, _("<illegal instruction>"));
return 2;
#endif
/* No match. */
abort ();
}
/*****************************************************************************/
/* s3_s7: exported functions. */
/* NOTE: There are no checks in these routines that
the relevant number of data bytes exist. */
int
s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
{
unsigned char b[4];
long given;
long ridparity;
int status;
bfd_boolean insn_pce_p = FALSE;
bfd_boolean insn_16_p = FALSE;
info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
if (pc & 0x2)
{
info->bytes_per_chunk = 2;
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
b[3] = b[2] = 0;
insn_16_p = TRUE;
}
else
{
info->bytes_per_chunk = 4;
status = info->read_memory_func (pc, (bfd_byte *) & b[0], 4, info);
if (status != 0)
{
info->bytes_per_chunk = 2;
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
b[3] = b[2] = 0;
insn_16_p = TRUE;
}
}
if (status != 0)
{
info->memory_error_func (status, pc, info);
return -1;
}
if (little)
{
given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
}
else
{
given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
}
if ((given & 0x80008000) == 0x80008000)
{
insn_pce_p = FALSE;
insn_16_p = FALSE;
}
else if ((given & 0x8000) == 0x8000)
{
insn_pce_p = TRUE;
}
else
{
insn_16_p = TRUE;
}
/* 16 bit instruction. */
if (insn_16_p)
{
if (little)
{
given = b[0] | (b[1] << 8);
}
else
{
given = (b[0] << 8) | b[1];
}
status = print_insn_score16 (pc, info, given);
}
/* pce instruction. */
else if (insn_pce_p)
{
long other;
other = given & 0xFFFF;
given = (given & 0xFFFF0000) >> 16;
status = print_insn_score16 (pc, info, given);
print_insn_parallel_sym (info);
status += print_insn_score16 (pc, info, other);
/* disassemble_bytes() will output 4 byte per chunk for pce instructio. */
info->bytes_per_chunk = 4;
}
/* 32 bit instruction. */
else
{
/* Get rid of parity. */
ridparity = (given & 0x7FFF);
ridparity |= (given & 0x7FFF0000) >> 1;
given = ridparity;
status = print_insn_score32 (pc, info, given);
}
return status;
}
/*****************************************************************************/