c80 simulator fixes.
This commit is contained in:
Andrew Cagney
parent
e05e76e8a4
commit
c445af5a2b
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@ -1,3 +1,16 @@
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Mon May 12 14:49:05 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-core.c (sim_core_find_mapping): Call engine_error not
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sim_io_error when possible.
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Mon May 12 08:55:07 1997 Andrew Cagney <cagney@b2.cygnus.com>
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* sim-endian.h (V1_H2): Add macro's to insert a word into a
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high/low double word.
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* sim-trace.h: Remove definition of attribute - defined in
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sim_basics.h.
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Mon May 12 08:55:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-options.h (struct OPTION): Add doc_opt as the documenting
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@ -42,14 +42,11 @@
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#endif
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/* Some versions of GCC include an attribute operator, define it */
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#if !defined (__attribute__)
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#if (!defined(__GNUC__) \
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|| (__GNUC__ < 2) \
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|| (__GNUC__ == 2 && __GNUC_MINOR__ < 6))
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#if (!defined(__GNUC__) || (__GNUC__ < 2) || (__GNUC__ == 2 && __GNUC_MINOR__ < 6))
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#define __attribute__(arg)
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#endif
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#endif
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@ -64,15 +61,19 @@ void *zalloc (unsigned long size);
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void zfree(void*);
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/* Turn VALUE into a string with commas. */
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char *sim_add_commas (char *, int, unsigned long);
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/* Utilities for elapsed time reporting. */
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/* Opaque type, known only inside sim_elapsed_time_foo fns. */
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typedef unsigned long SIM_ELAPSED_TIME;
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/* Get reference point for future call to sim_time_elapsed. */
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SIM_ELAPSED_TIME sim_elapsed_time_get (void);
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/* Elapsed time in milliseconds since START. */
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unsigned long sim_elapsed_time_since (SIM_ELAPSED_TIME start);
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@ -117,16 +118,14 @@ typedef enum _attach_type {
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#include "sim-config.h"
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#include "sim-module.h"
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#include "sim-trace.h"
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#include "sim-profile.h"
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#include "sim-model.h"
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#include "sim-base.h"
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#include "sim-inline.h"
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#include "sim-types.h"
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#include "sim-bits.h"
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#include "sim-endian.h"
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/* Note: Only the simpler interfaces are defined here. More heavy
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weight objects, such as core and events, are defined in the more
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serious sim-base.h header. */
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#endif /* _SIM_BASICS_H_ */
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@ -312,7 +312,7 @@ sim_core_find_mapping(sim_core *core,
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if (cpu == NULL)
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sim_io_error (NULL, "sim_core_find_map - internal error - can not abort without a processor");
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else
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sim_io_error (CPU_STATE (cpu),
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engine_error (CPU_STATE (cpu), cpu, cia,
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"access to unmaped address 0x%lx (%d bytes)\n",
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(unsigned long) addr, nr_bytes);
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}
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@ -23,84 +23,178 @@
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#define _SIM_EVENTS_H_
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typedef void event_handler(void *data);
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/* Notes:
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typedef struct _event_entry event_entry;
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struct _event_entry {
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When scheduling an event, the a delta of zero/one refers to the
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timeline as follows:
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epoch 0|1 1|2 2|3 3|
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**queue**|--insn--|*queue*|--insn--|*queue*|--insn--|*queue*|
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| ^ ^ | ^ ^
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`- +0 ------------ +1 --.. `----- +0 ------------- +1 --..
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When the queue is initialized, the time is set to zero with a
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number of initialization events scheduled. Consequently, as also
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illustrated above, the event queue should be processed before the
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first instruction. That instruction being executed during tick 1.
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The event queue is processed using:
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if (sim_events_tick (sd)) {
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sim_events_process (sd);
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}
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*/
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typedef void sim_event_handler(void *data);
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typedef struct _sim_event sim_event;
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struct _sim_event {
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void *data;
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event_handler *handler;
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sim_event_handler *handler;
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signed64 time_of_event;
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event_entry *next;
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sim_event *next;
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};
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typedef struct _event_queue event_queue;
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struct _event_queue {
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typedef struct _sim_events sim_events;
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struct _sim_events {
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int processing;
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event_entry *queue;
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event_entry *volatile held;
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event_entry *volatile *volatile held_end;
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sim_event *queue;
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sim_event *volatile held;
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sim_event *volatile *volatile held_end;
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signed64 time_of_event;
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signed64 time_from_event;
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int time_from_event;
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void *path_to_halt_or_restart;
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int trace;
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};
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typedef struct event_entry *event_entry_tag;
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/* Initialization */
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INLINE_SIM_EVENTS\
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(void) event_queue_init
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(engine *system);
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(void) sim_events_init
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(SIM_DESC sd);
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/* Tracing level */
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/* Set Tracing Level */
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INLINE_SIM_EVENTS\
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(void) event_queue_trace
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(engine *system,
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(void) sim_events_set_trace
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(SIM_DESC sd,
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int level);
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/* (de)Schedule things to happen in the future. */
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/* Schedule an event DELTA_TIME ticks into the future */
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INLINE_SIM_EVENTS\
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(event_entry_tag) event_queue_schedule
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(engine *system,
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(sim_event *) sim_events_schedule
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(SIM_DESC sd,
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signed64 delta_time,
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event_handler *handler,
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sim_event_handler *handler,
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void *data);
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INLINE_SIM_EVENTS\
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(event_entry_tag) event_queue_schedule_after_signal
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(engine *system,
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(sim_event *) sim_events_schedule_after_signal
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(SIM_DESC sd,
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signed64 delta_time,
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event_handler *handler,
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sim_event_handler *handler,
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void *data);
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/* Schedule an event WALLCLOCK milli-seconds from the start of the
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simulation. The exact interpretation of wallclock is host
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dependant. */
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INLINE_SIM_EVENTS\
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(void) event_queue_deschedule
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(engine *system,
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event_entry_tag event_to_remove);
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(void) sim_events_wallclock_schedule
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(SIM_DESC sd,
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signed64 wallclock_ms_time,
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sim_event_handler *handler,
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void *data);
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#if 0
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/* Schedule an event when the value at ADDR lies between LB..UB */
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typedef enum {
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/* value host byte ordered */
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watch_host_1,
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watch_host_2,
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watch_host_4,
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watch_host_8,
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/* value target byte ordered */
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watch_targ_1,
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watch_targ_2,
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watch_targ_4,
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watch_targ_8,
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/* value big-endian */
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watch_bend_1,
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watch_bend_2,
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watch_bend_4,
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watch_bend_8,
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/* value little-endian */
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watch_lend_1,
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watch_lend_2,
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watch_lend_4,
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watch_lend_8,
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} sim_watchpoint;
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INLINE_SIM_EVENTS\
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(void) sim_events_watchpoint_schedule
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(SIM_DESC sd,
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sim_watchpoint type,
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void *addr,
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unsigned64 lb,
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unsigned64 ub,
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sim_event_handler *handler,
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void *data);
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#endif
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#if 0
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/* Schedule an event when the value in CORE lies between LB..UB */
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INLINE_SIM_EVENTS\
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(void) sim_events_watchcore_schedule
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(SIM_DESC sd,
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sim_watchpoint type,
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address_word addr,
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sim_core_maps map,
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unsigned64 lb,
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unsigned64 ub,
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sim_event_handler *handler,
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void *data);
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#endif
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/* Deschedule the specified event */
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INLINE_SIM_EVENTS\
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(void) sim_events_deschedule
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(SIM_DESC sd,
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sim_event *event_to_remove);
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/* progress time. Broken into two parts so that if something is
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pending, the caller has a chance to save any cached state */
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INLINE_SIM_EVENTS\
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(int) event_queue_tick
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(engine *system);
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(int) sim_events_tick
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(SIM_DESC sd);
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INLINE_SIM_EVENTS\
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(void) event_queue_process
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(engine *system);
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(void) sim_events_process
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(SIM_DESC sd);
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/* local concept of time */
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INLINE_SIM_EVENTS\
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(signed64) event_queue_time
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(engine *system);
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(signed64) sim_events_time
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(SIM_DESC sd);
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#endif
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@ -1,3 +1,27 @@
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Mon May 12 11:12:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
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rDest + 1. Also done by Michael Meissner <meissner@cygnus.com>
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(do_st): Converse for store.
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* misc.c (tic80_trace_fpu2i): Correct printf format for int type.
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Sun May 11 11:02:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
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was cleared.
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* interp.c (engine_step): New function. Single step the simulator
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taking care of cntrl-c during a step.
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* sim-calls.c (sim_resume): Differentiate between stepping and
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running so that a cntrl-c during a step is reported.
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Sun May 11 10:54:31 1997 Mark Alexander <marka@cygnus.com>
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* sim-calls.c (sim_fetch_register): Use correct reg base.
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(sim_store_register): Ditto.
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Sun May 11 10:25:14 1997 Michael Meissner <meissner@cygnus.com>
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* cpu.h (tic80_trace_shift): Add declaration.
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@ -633,7 +633,6 @@ instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink,
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// ld[{.b.h.d}]
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void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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unsigned32 addr;
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unsigned64 u64;
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switch (sz)
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{
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case 0:
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@ -655,15 +654,18 @@ void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int
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GPR(Dest) = MEM (signed, addr, 4);
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break;
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case 3:
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if (Dest & 0x1)
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engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
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cia.ip, Dest);
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addr = Base + (S ? (Offset << 3) : Offset);
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if (m)
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*rBase = addr;
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u64 = MEM (signed, addr, 8);
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GPR(Dest) = (unsigned32) u64;
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GPR(Dest+1) = (unsigned32) (u64 >> 32);
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{
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signed64 val;
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if (Dest & 0x1)
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engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
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cia.ip, Dest);
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addr = Base + (S ? (Offset << 3) : Offset);
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if (m)
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*rBase = addr;
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val = MEM (signed, addr, 8);
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GPR(Dest + 1) = VH4_8 (val);
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GPR(Dest + 0) = VL4_8 (val);
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}
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break;
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default:
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addr = -1;
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@ -898,7 +900,6 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
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// st[{.b|.h|.d}]
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void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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unsigned32 addr;
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unsigned64 u64;
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switch (sz)
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{
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case 0:
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@ -914,13 +915,16 @@ void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , in
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STORE (addr, 4, GPR(Source));
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break;
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case 3:
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if (Source & 0x1)
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engine_error (SD, CPU, cia, "0x%lx: st.d with odd source register %d",
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cia.ip, Source);
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addr = Base + (S ? (Offset << 3) : Offset);
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u64 = GPR (Source);
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u64 |= (((unsigned64) GPR (Source+1)) << 32);
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STORE (addr, 8, u64);
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{
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signed64 val;
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if (Source & 0x1)
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engine_error (SD, CPU, cia,
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"0x%lx: st.d with odd source register %d",
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cia.ip, Source);
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addr = Base + (S ? (Offset << 3) : Offset);
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val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
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STORE (addr, 8, val);
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}
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break;
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default:
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addr = -1;
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@ -129,3 +129,30 @@ engine_run_until_stop (SIM_DESC sd,
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engine_halt (sd, cpu, cia, sim_stopped, SIGINT);
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}
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}
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void
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engine_step (SIM_DESC sd)
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{
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if (!setjmp (sd->path_to_halt))
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{
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instruction_address cia;
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sim_cpu *cpu = STATE_CPU (sd, 0);
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sd->halt_ok = 1;
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setjmp (sd->path_to_restart);
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sd->restart_ok = 1;
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cia = cpu->cia;
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if (cia.ip == -1)
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{
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/* anulled instruction */
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cia.ip = cia.dp;
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cia.dp = cia.dp + sizeof (instruction_word);
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}
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else
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{
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instruction_word insn = IMEM (cia.ip);
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cia = idecode_issue (sd, insn, cia);
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}
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engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP);
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}
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}
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@ -282,7 +282,7 @@ tic80_trace_fpu2i (SIM_DESC sd,
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trace_one_insn (sd, cpu, cia.ip, 1,
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itable[indx].file, itable[indx].line_nr, "fpu",
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"%-*s %*f %*f => 0x%.*lx %-*s",
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"%-*s %*f %*f => 0x%.*lx %-*ld",
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tic80_size_name, itable[indx].name,
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SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input1),
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SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input2),
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@ -178,7 +178,7 @@ void
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sim_fetch_register (SIM_DESC sd, int regnr, unsigned char *buf)
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{
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if (regnr >= R0_REGNUM && regnr <= Rn_REGNUM)
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*(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->reg[regnr - A0_REGNUM]);
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*(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM]);
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else if (regnr == PC_REGNUM)
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*(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->cia.ip);
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else if (regnr == NPC_REGNUM)
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@ -195,7 +195,7 @@ void
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sim_store_register (SIM_DESC sd, int regnr, unsigned char *buf)
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{
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if (regnr >= R0_REGNUM && regnr <= Rn_REGNUM)
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STATE_CPU (sd, 0)->reg[regnr - A0_REGNUM] = T2H_4 (*(unsigned32*)buf);
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STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM] = T2H_4 (*(unsigned32*)buf);
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else if (regnr == PC_REGNUM)
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STATE_CPU (sd, 0)->cia.ip = T2H_4 (*(unsigned32*)buf);
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else if (regnr == NPC_REGNUM)
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@ -233,9 +233,17 @@ volatile int keep_running = 1;
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void
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sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
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{
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*reason = simulation.reason;
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*sigrc = simulation.siggnal;
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keep_running = 1; /* ready for next run */
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if (!keep_running)
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{
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*reason = sim_stopped;
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*sigrc = SIGINT;
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keep_running = 0;
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}
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else
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{
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*reason = simulation.reason;
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*sigrc = simulation.siggnal;
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}
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}
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@ -251,8 +259,9 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
|
|||
{
|
||||
/* keep_running = 1 - in sim_stop_reason */
|
||||
if (step)
|
||||
keep_running = 0;
|
||||
engine_run_until_stop(sd, &keep_running);
|
||||
engine_step (sd);
|
||||
else
|
||||
engine_run_until_stop (sd, &keep_running);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
|||
|
|
@ -101,5 +101,7 @@ extern void engine_run_until_stop
|
|||
(SIM_DESC sd,
|
||||
volatile int *keep_running);
|
||||
|
||||
extern void engine_step
|
||||
(SIM_DESC sd);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue