Thu Jul 8 14:41:43 1993 Mark Eichin (eichin@cygnus.com)
* config/tc-i960.c (md_create_short_jump, md_create_long_jump, md_number_to_chars, md_section_align): Adjusted to use valueT, addressT, to match tc.h.
This commit is contained in:
Mark Eichin
parent
ff4cac3854
commit
c47d388b75
@ -81,7 +81,6 @@
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#include <ctype.h>
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#include "as.h"
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#include "read.h"
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#include "obstack.h"
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@ -92,9 +91,9 @@ extern struct hash_control *po_hash;
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extern char *next_object_file_charP;
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#ifdef OBJ_COFF
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int md_reloc_size = sizeof (struct reloc);
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const int md_reloc_size = sizeof (struct reloc);
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#else /* OBJ_COFF */
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int md_reloc_size = sizeof (struct relocation_info);
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const int md_reloc_size = sizeof (struct relocation_info);
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#endif /* OBJ_COFF */
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/***************************
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@ -150,9 +149,9 @@ const char comment_chars[] = "#";
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/* Also note that comments started like this one will always work. */
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const char line_comment_chars[] = "";
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const char line_comment_chars[1];
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const char line_separator_chars[] = "";
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const char line_separator_chars[1];
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/* Chars that can be used to separate mant from exp in floating point nums */
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const char EXP_CHARS[] = "eE";
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@ -247,17 +246,20 @@ const pseudo_typeS md_pseudo_table[] =
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#define D_BIT 0x2000
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/* Mask for the only mode bit in a MEMA instruction (if set, abase reg is used) */
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/* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
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used). */
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#define MEMA_ABASE 0x2000
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/* Info from which a MEMA or MEMB format instruction can be generated */
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typedef struct
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{
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long opcode; /* (First) 32 bits of instruction */
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int disp; /* 0-(none), 12- or, 32-bit displacement needed */
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char *e; /* The expression in the source instruction from
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* which the displacement should be determined
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*/
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/* (First) 32 bits of instruction */
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long opcode;
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/* 0-(none), 12- or, 32-bit displacement needed */
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int disp;
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/* The expression in the source instruction from which the
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displacement should be determined. */
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char *e;
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}
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memS;
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@ -422,9 +424,9 @@ aregs[] =
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/* Hash tables */
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static struct hash_control *op_hash = NULL; /* Opcode mnemonics */
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static struct hash_control *reg_hash = NULL; /* Register name hash table */
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static struct hash_control *areg_hash = NULL; /* Abase register hash table */
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static struct hash_control *op_hash; /* Opcode mnemonics */
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static struct hash_control *reg_hash; /* Register name hash table */
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static struct hash_control *areg_hash; /* Abase register hash table */
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/* Architecture for which we are assembling */
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@ -434,7 +436,7 @@ static struct hash_control *areg_hash = NULL; /* Abase register hash table */
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#define ARCH_MC 3
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#define ARCH_CA 4
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int architecture = ARCH_ANY; /* Architecture requested on invocation line */
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int iclasses_seen = 0; /* OR of instruction classes (I_* constants)
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int iclasses_seen; /* OR of instruction classes (I_* constants)
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* for which we've actually assembled
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* instructions.
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*/
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@ -476,7 +478,7 @@ int iclasses_seen = 0; /* OR of instruction classes (I_* constants)
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* list of such tables.
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*/
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static int br_cnt = 0; /* Number of branches instrumented so far.
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static int br_cnt; /* Number of branches instrumented so far.
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* Also used to generate unique local labels
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* for each instrumented branch
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*/
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@ -517,10 +519,9 @@ md_begin ()
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as_fatal ("virtual memory exceeded");
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}
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retval = ""; /* For some reason, the base assembler uses an empty
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* string for "no error message", instead of a NULL
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* pointer.
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*/
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/* For some reason, the base assembler uses an empty string for "no
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error message", instead of a NULL pointer. */
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retval = "";
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for (oP = i960_opcodes; oP->name && !*retval; oP++)
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{
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@ -570,23 +571,27 @@ void
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md_assemble (textP)
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char *textP; /* Source text of instruction */
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{
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char *args[4]; /* Parsed instruction text, containing NO whitespace:
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* arg[0]->opcode mnemonic
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* arg[1-3]->operands, with char constants
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* replaced by decimal numbers
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*/
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/* Parsed instruction text, containing NO whitespace:
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* arg[0]->opcode mnemonic
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* arg[1-3]->operands, with char constants
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* replaced by decimal numbers
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*/
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char *args[4];
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int n_ops; /* Number of instruction operands */
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int callx;
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struct i960_opcode *oP;
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/* Pointer to instruction description */
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int branch_predict;
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struct i960_opcode *oP;
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/* TRUE iff opcode mnemonic included branch-prediction
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* suffix (".f" or ".t")
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*/
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long bp_bits; /* Setting of branch-prediction bit(s) to be OR'd
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* into instruction opcode of CTRL/COBR format
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* instructions.
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*/
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* suffix (".f" or ".t")
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*/
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int branch_predict;
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/* Setting of branch-prediction bit(s) to be OR'd
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* into instruction opcode of CTRL/COBR format
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* instructions.
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*/
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long bp_bits;
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int n; /* Offset of last character in opcode mnemonic */
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static const char bp_error_msg[] = "branch prediction invalid on this opcode";
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@ -619,18 +624,18 @@ md_assemble (textP)
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if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
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{
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/* We could check here to see if the target architecture
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* supports branch prediction, but why bother? The bit
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* will just be ignored by processors that don't use it.
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*/
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* supports branch prediction, but why bother? The bit
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* will just be ignored by processors that don't use it.
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*/
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branch_predict = 1;
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bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
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args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
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}
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/* Look up opcode mnemonic in table and check number of operands.
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* Check that opcode is legal for the target architecture.
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* If all looks good, assemble instruction.
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*/
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* Check that opcode is legal for the target architecture.
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* If all looks good, assemble instruction.
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*/
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oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
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if (!oP || !targ_has_iclass (oP->iclass))
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{
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@ -639,8 +644,8 @@ md_assemble (textP)
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}
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else if (n_ops != oP->num_ops)
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{
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as_bad ("improper number of operands. expecting %d, got %d", oP->num_ops, n_ops);
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as_bad ("improper number of operands. expecting %d, got %d",
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oP->num_ops, n_ops);
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}
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else
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{
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@ -712,7 +717,7 @@ md_assemble (textP)
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void
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md_number_to_chars (buf, value, n)
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char *buf; /* Put output here */
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long value; /* The integer to be converted */
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valueT value; /* The integer to be converted */
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int n; /* Number of bytes to output (significant bytes
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* in 'value')
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*/
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@ -1130,8 +1135,8 @@ int md_long_jump_size = 0;
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void
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md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
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char *ptr;
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long from_addr;
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long to_addr;
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addressT from_addr;
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addressT to_addr;
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fragS *frag;
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symbolS *to_symbol;
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{
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@ -1141,7 +1146,7 @@ md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
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void
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md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
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char *ptr;
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long from_addr, to_addr;
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addressT from_addr, to_addr;
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fragS *frag;
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symbolS *to_symbol;
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{
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@ -1469,21 +1474,27 @@ get_args (p, args)
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* o an address fixup to be done when all symbol values are known, or
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* o a varying length code fragment, with address fixup info. This
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* will be done for cobr instructions that may have to be relaxed
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* in to compare/branch instructions (8 bytes) if the final address
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* displacement is greater than 13 bits.
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* in to compare/branch instructions (8 bytes) if the final
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* address displacement is greater than 13 bits.
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*
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**************************************************************************** */
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*****************************************************************************/
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static
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void
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get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
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char *dispP; /*->displacement as specified in source instruction */
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char *ifmtP; /*->"COBR" or "CTRL" (for use in error message) */
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long instr; /* Instruction needing the displacement */
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int numbits; /* # bits of displacement (13 for COBR, 24 for CTRL) */
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int var_frag; /* 1 if varying length code fragment should be emitted;
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* 0 if an address fix should be emitted.
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*/
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int callj; /* 1 if callj relocation should be done; else 0 */
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/* displacement as specified in source instruction */
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char *dispP;
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/* "COBR" or "CTRL" (for use in error message) */
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char *ifmtP;
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/* Instruction needing the displacement */
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long instr;
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/* # bits of displacement (13 for COBR, 24 for CTRL) */
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int numbits;
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/* 1 if varying length code fragment should be emitted;
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* 0 if an address fix should be emitted.
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*/
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int var_frag;
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/* 1 if callj relocation should be done; else 0 */
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int callj;
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{
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expressionS e; /* Parsed expression */
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fixS *fixP; /* Structure describing needed address fix */
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@ -1510,8 +1521,8 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
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else
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{
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/* Set up a new fix structure, so address can be updated
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* when all symbol values are known.
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*/
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* when all symbol values are known.
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*/
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outP = emit (instr);
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fixP = fix_new (frag_now,
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outP - frag_now->fr_literal,
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@ -1525,10 +1536,10 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
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fixP->fx_callj = callj;
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/* We want to modify a bit field when the address is
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* known. But we don't need all the garbage in the
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* bit_fix structure. So we're going to lie and store
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* the number of bits affected instead of a pointer.
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*/
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* known. But we don't need all the garbage in the
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* bit_fix structure. So we're going to lie and store
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* the number of bits affected instead of a pointer.
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*/
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fixP->fx_bit_fixP = (bit_fixS *) numbits;
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}
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break;
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@ -1754,15 +1765,15 @@ mem_fmt (args, oP, callx)
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if (instr.disp == 12)
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{
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/* Displacement is dependent on a symbol, whose value
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* may change at link time. We HAVE to reserve 32 bits.
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* Convert already-output opcode to MEMB format.
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*/
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* may change at link time. We HAVE to reserve 32 bits.
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* Convert already-output opcode to MEMB format.
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*/
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mema_to_memb (outP);
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}
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/* Output 0 displacement and set up address fixup for when
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* this symbol's value becomes known.
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*/
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* this symbol's value becomes known.
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*/
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outP = emit ((long) 0);
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fixP = fix_new (frag_now,
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outP - frag_now->fr_literal,
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@ -2025,10 +2036,10 @@ parse_memop (memP, argP, optype)
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int *intP; /* Pointer to register number */
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/* The following table contains the default scale factors for each
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* type of memory instruction. It is accessed using (optype-MEM1)
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* as an index -- thus it assumes the 'optype' constants are assigned
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* consecutive values, in the order they appear in this table
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*/
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* type of memory instruction. It is accessed using (optype-MEM1)
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* as an index -- thus it assumes the 'optype' constants are assigned
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* consecutive values, in the order they appear in this table
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*/
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static int def_scale[] =
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{
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1, /* MEM1 */
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@ -2492,9 +2503,9 @@ static
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void
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relax_cobr (fragP)
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register fragS *fragP; /* fragP->fr_opcode is assumed to point to
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* the cobr instruction, which comes at the
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* end of the code fragment.
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*/
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* the cobr instruction, which comes at the
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* end of the code fragment.
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*/
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{
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int opcode, src1, src2, m1, s2;
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/* Bit fields from cobr instruction */
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@ -2880,15 +2891,18 @@ md_apply_fix (fixP, val)
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break;
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case 1:
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md_number_to_disp (place,
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fixP->fx_pcrel ? val + fixP->fx_pcrel_adjust : val,
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(fixP->fx_pcrel
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? val + fixP->fx_pcrel_adjust
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: val),
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fixP->fx_size);
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break;
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case 2: /* fix requested for .long .word etc */
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md_number_to_chars (place, val, fixP->fx_size);
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break;
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default:
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as_fatal ("Internal error in md_apply_fix() in file \"%s\"", __FILE__);
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} /* OVE: maybe one ought to put _imm _disp _chars in one md-func */
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as_fatal ("Internal error in md_apply_fix() in file \"%s\"",
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__FILE__);
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}
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}
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else
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{
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@ -2970,10 +2984,10 @@ tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
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/* Align an address by rounding it up to the specified boundary.
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*/
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long
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valueT
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md_section_align (seg, addr)
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segT seg;
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long addr; /* Address to be rounded up */
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valueT addr; /* Address to be rounded up */
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{
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return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
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} /* md_section_align() */
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@ -3204,11 +3218,4 @@ i960_handle_align (fragp)
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(int) fragp->fr_type);
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}
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/*
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* Local Variables:
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* comment-column: 0
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* fill-column: 131
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* End:
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*/
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/* end of tc-i960.c */
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