From c49ec3da04e9d80d89cbc70863e4c4c1366dbd58 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Sun, 19 Sep 1999 19:43:06 +0000 Subject: [PATCH] * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. --- include/opcode/ChangeLog | 2 ++ include/opcode/hppa.h | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 0aa1d79472..62ed206011 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,5 +1,7 @@ Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) + * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. + * hppa.h (pa_opcodes): Add long offset double word load/store instructions. diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h index da914e558a..2e5beea126 100644 --- a/include/opcode/hppa.h +++ b/include/opcode/hppa.h @@ -227,6 +227,7 @@ Floating point registers all have 'f' as a prefix: fb operand 2 register at 15 fB operand 2 register with L/R halves at 15 fC operand 3 register with L/R halves at 16:18,21:23 + fe Like fT, but encoding is different. Float registers for fmpyadd and fmpysub: @@ -626,6 +627,10 @@ static const struct pa_opcode pa_opcodes[] = { "fldw", 0x24000000, 0xfc001f80, "cxx(b),fT", pa10, FLAG_STRICT}, { "fldw", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, FLAG_STRICT}, { "fldw", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000004, "cJd(s,b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000004, "cJd(b),fe", pa20, FLAG_STRICT}, { "fldd", 0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10, FLAG_STRICT}, { "fldd", 0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10, FLAG_STRICT}, { "fldd", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, FLAG_STRICT}, @@ -636,6 +641,10 @@ static const struct pa_opcode pa_opcodes[] = { "fstw", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, FLAG_STRICT}, { "fstw", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, FLAG_STRICT}, { "fstw", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000004, "fe,d(s,b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "cJfe,d(s,b)", pa20, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "cJfe,d(b)", pa20, FLAG_STRICT}, { "fstd", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, FLAG_STRICT}, { "fstd", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10, FLAG_STRICT}, { "fstd", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, FLAG_STRICT},