This is for PR 628.
Wed Aug 19 11:20:59 1992 Ian Lance Taylor (ian@cygnus.com) * tc-m68k.c, tc-m68kmote.c: the cas2 instruction is supposed to be written with indirection on the last two operands, which can be either data or address registers. Added a new operand type 'r' which accepts either register type. Added '(' to notend stuff in tc-m68kmote.c to accept (a0):(a2) in cas2 instruction.
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Ian Lance Taylor
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@ -1,3 +1,11 @@
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Wed Aug 19 11:20:59 1992 Ian Lance Taylor (ian@cygnus.com)
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* tc-m68k.c, tc-m68kmote.c: the cas2 instruction is supposed to be
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written with indirection on the last two operands, which can be
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either data or address registers. Added a new operand type 'r'
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which accepts either register type. Added '(' to notend stuff in
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tc-m68kmote.c to accept (a0):(a2) in cas2 instruction.
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Tue Aug 11 12:58:14 1992 Ken Raeburn (raeburn@cygnus.com)
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* sparc.mt: New file.
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@ -12,7 +20,6 @@ Thu Aug 6 12:08:42 1992 Steve Chamberlain (sac@thepub.cygnus.com)
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* config/tc-h8300.c: if a :8 is seen after an operand, fill top
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two bytes of any constant with 0xff:
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Wed Aug 5 01:54:34 1992 John Gilmore (gnu at cygnus.com)
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* tc-m68k.c (try_index): Error if index scaling specified and
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@ -117,6 +117,7 @@ static struct obstack robyn;
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*** MSCR otherreg --> Magic
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With -l option
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5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
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?.? DINDR dreg@ --> (dreg) -- cas2 only
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examples:
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#foo #0x35 #12
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@ -151,6 +152,7 @@ enum operand_type {
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ABSL,
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MSCR,
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REGLST,
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DINDR
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};
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@ -665,7 +667,9 @@ register struct m68k_op *opP;
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return OK;
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}
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if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) { /* Can't indirect off non address regs */
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/* Can't indirect off non address regs, but Dx@ is OK for cas2 */
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if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL
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&& (str[1] != '\0' || i<DATA+0 || i>DATA+7)) {
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opP->error="Invalid indirect register";
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return FAIL;
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}
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@ -674,7 +678,10 @@ register struct m68k_op *opP;
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str++;
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switch(*str) {
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case '\0':
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opP->mode=AINDR;
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if (i < DATA + 0 || i > DATA + 7)
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opP->mode=AINDR;
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else
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opP->mode=DINDR;
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return OK;
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case '-':
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opP->mode=ADEC;
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@ -1294,6 +1301,11 @@ void m68k_ip (instring)
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losing++;
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break;
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case 'r':
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if (opP->mode!=AINDR && opP->mode!=DINDR)
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losing++;
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break;
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case 's':
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if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
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losing++;
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@ -1809,6 +1821,9 @@ void m68k_ip (instring)
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break;
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}
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break;
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case DINDR:
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as_bad("invalid indirect register");
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break;
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case MSCR:
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default:
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as_bad("unknown/incorrect operand");
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@ -2090,6 +2105,7 @@ void m68k_ip (instring)
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break;
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case 'R':
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case 'r':
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/* This depends on the fact that ADDR registers are
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eight more than their corresponding DATA regs, so
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the result will have the ADDR_REG bit set */
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@ -123,6 +123,7 @@ static struct obstack robyn;
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*** MSCR otherreg --> Magic
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With -l option
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5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
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?.? DINDR dreg@ --> (dreg) -- cas2 only
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examples:
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#foo #0x35 #12
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@ -157,6 +158,7 @@ enum operand_type {
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ABSL,
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MSCR,
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REGLST,
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DINDR
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};
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@ -933,8 +935,10 @@ register struct m68k_op *opP;
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if(*str=='(') {
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str++;
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i=m68k_reg_parse(&str);
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if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) {
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/* Can't indirect off non address regs */
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if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL
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&& (*str != ')' || str[1] != '\0' || i<DATA+0 || i>DATA+7)) {
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/* Can't indirect off non address regs,
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but (dx) is OK for cas2. */
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opP->error="Invalid indirect register";
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return FAIL;
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}
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@ -943,8 +947,12 @@ register struct m68k_op *opP;
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if(*str==')') {
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str++;
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if(*str=='\0') {
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/* "(An)" Address Register Indirect mode */
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opP->mode=AINDR;
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/* "(An)" Address Register Indirect mode
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or "(Dn)" for cas2 instruction. */
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if (i < DATA + 0 || i > DATA + 7)
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opP->mode=AINDR;
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else
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opP->mode=DINDR;
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return OK;
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}
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if(*str=='+') {
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@ -1209,7 +1217,9 @@ register struct m68k_op *opP;
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return OK;
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}
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if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) { /* Can't indirect off non address regs */
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/* Can't indirect off non address regs, but Dx@ is OK for cas2 */
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if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL
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&& (str[1] != '\0' || i<DATA+0 || i>DATA+7)) {
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opP->error="Invalid indirect register";
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return FAIL;
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}
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@ -1218,7 +1228,10 @@ register struct m68k_op *opP;
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str++;
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switch(*str) {
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case '\0':
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opP->mode=AINDR;
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if (i < DATA + 0 || i > DATA + 7)
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opP->mode=AINDR;
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else
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opP->mode=DINDR;
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return OK;
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case '-':
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opP->mode=ADEC;
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@ -1863,6 +1876,11 @@ char *instring;
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losing++;
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break;
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case 'r':
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if(opP->mode!=AINDR && opP->mode!=DINDR)
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losing++;
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break;
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case 's':
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if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
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losing++;
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@ -2327,6 +2345,9 @@ char *instring;
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break;
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}
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break;
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case DINDR:
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as_bad("invalid indirect register");
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break;
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case MSCR:
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default:
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as_bad("unknown/incorrect operand");
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@ -2608,6 +2629,7 @@ char *instring;
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break;
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case 'R':
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case 'r':
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/* This depends on the fact that ADDR registers are
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eight more than their corresponding DATA regs, so
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the result will have the ADDR_REG bit set */
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@ -3015,7 +3037,7 @@ char *s;
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return 0;
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if(*s!=':') return 1;
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/* This kludge here is for the division cmd, which is a kludge */
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if(index("aAdD#",s[1])) return 0;
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if(index("aAdD#(",s[1])) return 0;
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return 1;
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}
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#endif
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@ -3296,6 +3318,7 @@ void
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alt_notend_table['#'] = 1;
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alt_notend_table['f'] = 1;
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alt_notend_table['F'] = 1;
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alt_notend_table['('] = 1;
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#ifdef REGISTER_PREFIX
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alt_notend_table[REGISTER_PREFIX] = 1;
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@ -3306,7 +3329,7 @@ void
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#if 0
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#define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
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|| (*s == ':' && strchr("aAdD#", s[1]))) \
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|| (*s == ':' && strchr("aAdD#(", s[1]))) \
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? 0 : 1)
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#endif
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