2011-06-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (do_ldrd): Warn in unpredictable cases. 2011-06-09 James Greenhalgh <james.greenhalgh@arm.com> * gas/arm/ldrd-unpredicatble.d: New testcase. * gas/arm/ldrd-unpredicatble.s: Likewise. * gas/arm/ldrd-unpredicatble.l: Likewise.
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2011-06-09 James Greenhalgh <james.greenhalgh@arm.com>
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* config/tc-arm.c (do_ldrd): Warn in unpredictable cases.
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2011-06-03 Arnaud Patard <arnaud.patard@rtp-net.org>
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PR gas/12698
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@ -7798,18 +7798,16 @@ static void
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do_ldrd (void)
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{
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constraint (inst.operands[0].reg % 2 != 0,
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_("first destination register must be even"));
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_("first transfer register must be even"));
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constraint (inst.operands[1].present
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&& inst.operands[1].reg != inst.operands[0].reg + 1,
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_("can only load two consecutive registers"));
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_("can only transfer two consecutive registers"));
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constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
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constraint (!inst.operands[2].isreg, _("'[' expected"));
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if (!inst.operands[1].present)
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inst.operands[1].reg = inst.operands[0].reg + 1;
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if (inst.instruction & LOAD_BIT)
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{
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/* encode_arm_addr_mode_3 will diagnose overlap between the base
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register and the first register written; we have to diagnose
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overlap between the base and the second register written here. */
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@ -7817,16 +7815,17 @@ do_ldrd (void)
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if (inst.operands[2].reg == inst.operands[1].reg
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&& (inst.operands[2].writeback || inst.operands[2].postind))
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as_warn (_("base register written back, and overlaps "
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"second destination register"));
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"second transfer register"));
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if (!(inst.instruction & V4_STR_BIT))
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{
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/* For an index-register load, the index register must not overlap the
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destination (even if not write-back). */
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else if (inst.operands[2].immisreg
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if (inst.operands[2].immisreg
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&& ((unsigned) inst.operands[2].imm == inst.operands[0].reg
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|| (unsigned) inst.operands[2].imm == inst.operands[1].reg))
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as_warn (_("index register overlaps destination register"));
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as_warn (_("index register overlaps transfer register"));
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}
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inst.instruction |= inst.operands[0].reg << 12;
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encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
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}
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@ -1,3 +1,9 @@
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2011-06-09 James Greenhalgh <james.greenhalgh@arm.com>
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* gas/arm/ldrd-unpredicatble.d: New testcase.
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* gas/arm/ldrd-unpredicatble.s: Likewise.
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* gas/arm/ldrd-unpredicatble.l: Likewise.
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2011-06-02 Jie Zhang <jie@codesourcery.com>
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Nathan Sidwell <nathan@codesourcery.com>
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@ -0,0 +1,2 @@
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# name: Unpredictable LDRD and STRD instructions. - ARM
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# error-output: ldrd-unpredictable.l
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@ -0,0 +1,7 @@
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[^:]*: Assembler messages:
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[^:]*:6: Warning: index register overlaps transfer register
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[^:]*:7: Warning: index register overlaps transfer register
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[^:]*:8: Warning: source register same as write-back base
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[^:]*:9: Warning: base register written back, and overlaps second transfer register
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[^:]*:13: Warning: source register same as write-back base
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[^:]*:14: Warning: base register written back, and overlaps second transfer register
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@ -0,0 +1,14 @@
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.syntax unified
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.arm
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@ LDRD
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ldrd r0,r1,[r0,r1] @ unpredictable
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ldrd r0,r1,[r1,r0] @ ditto
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ldrd r0,r1,[r0,r2]! @ ditto
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ldrd r0,r1,[r1,r2]! @ ditto
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@ STRD
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strd r0,r1,[r0,r2]! @ ditto
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strd r0,r1,[r1,r2]! @ ditto
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