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binutils-gdb
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Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 

* d10v-opc.c (d10v_operands): Added 2 accumulator sub instructions.
	Changed subi operand type to treat 0 as 16.
This commit is contained in:
Martin Hunt 1996-08-03 00:49:00 +00:00
parent 4c38885c86
commit c5e1996f55
2 changed files with 11 additions and 2 deletions
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7
opcodes/ChangeLog
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@ -1,3 +1,10 @@
start-sanitize-d10v
Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_operands): Added 2 accumulator sub instructions.
Changed subi operand type to treat 0 as 16.
end-sanitize-d10v
Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com>
* m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose

6
opcodes/d10v-opc.c
View File

@ -90,7 +90,7 @@ const struct d10v_operand d10v_operands[] =
{ 4, 1, OPERAND_NUM|OPERAND_SIGNED },
#define UNUM4 (NUM4 + 1)
{ 4, 1, OPERAND_NUM },
#define UNUM4S (UNUM4 + 1) /* slli, srai, srli */
#define UNUM4S (UNUM4 + 1) /* slli, srai, srli, subi */
{ 4, 1, OPERAND_NUM|OPERAND_SHIFT },
#define UNUM8 (UNUM4S + 1) /* repi */
{ 8, 16, OPERAND_NUM },
@ -281,12 +281,14 @@ const struct d10v_opcode d10v_opcodes[] = {
{ "stb", SHORT_2, 1, MU, PAR, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
{ "stop", SHORT_2, 1, MU, PAR, 0x5fe0, 0x7fff, { 0 } },
{ "sub", SHORT_2, 1, EITHER, PAR, 0x0, 0x7e01, { RDST, RSRC } },
{ "sub", SHORT_2, 1, IU, PAR, 0x1001, 0x7ee3, { ADST, RSRC } },
{ "sub", SHORT_2, 1, IU, PAR, 0x1003, 0x7eef, { ADST, ASRC } },
{ "sub2w", SHORT_2, 1, IU, PAR, 0x1000, 0x7e23, { RDSTE, RSRCE } },
{ "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
{ "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
{ "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
{ "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
{ "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4 } },
{ "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4S } },
{ "trap", SHORT_2, 5, MU, PAR, 0x5f00, 0x7fe1, { UNUM4 } },
{ "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } },
{ "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } },