Add support for v850e1 instructions
This commit is contained in:
Nick Clifton
parent
d508790742
commit
c5ea1d538f
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@ -1,3 +1,15 @@
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2003-09-05 Andrew Cagney <cagney@redhat.com>
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Nick Clifton <nickc@redhat.com>
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* interp.c (sim_open): Accept bfd_mach_v850e1.
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* v850-dc: Add entry for v850e1.
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* v850.igen: Add support for v850e1.
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Add code for DBTRAP and DBRET instructions.
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(dbtrap): Create a separate v850e1 specific instruction.
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Only generate a trap if the target is not the v850e1.
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Otherwise treat it as a special kind of branch.
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(break): Mark as v850/v850e specific.
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2003-05-16 Ian Lance Taylor <ian@airs.com>
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* Makefile.in (SHELL): Make sure this is defined.
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@ -277,6 +277,7 @@ sim_open (kind, cb, abfd, argv)
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{
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case bfd_mach_v850:
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case bfd_mach_v850e:
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case bfd_mach_v850e1:
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STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT
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| PSW_CY | PSW_OV | PSW_S | PSW_Z);
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break;
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@ -11,6 +11,7 @@
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switch,combine : 4 : 0 : : : : 1 : V,VII :
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switch,combine : 4 : 0 : : : : 1 : V,XIII : v850e
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switch,combine : 4 : 0 : : : : 1 : V,XIII : v850e1
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# for opcode 63, 127, 1087 et.al.
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@ -12,6 +12,8 @@
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:option:::multi-sim:true
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:model:::v850e:v850e:
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:option:::multi-sim:true
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:model:::v850e1:v850e1:
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// Cache macros
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@ -156,6 +158,7 @@ ddddd,1011,ddd,cccc:III:::Bcond
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// BSH
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rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
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*v850e
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*v850e1
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"bsh r<reg2>, r<reg3>"
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{
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unsigned32 value;
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@ -178,6 +181,7 @@ rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
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// BSW
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rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
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*v850e
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*v850e1
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"bsw r<reg2>, r<reg3>"
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{
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#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
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@ -203,6 +207,7 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
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// CALLT
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0000001000,iiiiii:II:::callt
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*v850e
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*v850e1
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"callt <imm6>"
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{
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unsigned32 adr;
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@ -225,6 +230,7 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
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rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
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*v850e
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*v850e1
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"clr1 r<reg2>, [r<reg1>]"
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{
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COMPAT_2 (OP_E407E0 ());
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@ -234,6 +240,7 @@ rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
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// CTRET
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0000011111100000 + 0000000101000100:X:::ctret
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*v850e
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*v850e1
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"ctret"
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{
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nia = (CTPC & ~1);
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@ -244,6 +251,7 @@ rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
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// CMOV
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rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
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*v850e
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*v850e1
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"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
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{
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int cond = condition_met (cccc);
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@ -254,6 +262,7 @@ rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
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rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
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*v850e
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*v850e1
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"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
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{
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int cond = condition_met (cccc);
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@ -291,6 +300,7 @@ rrrrr,010011,iiiii:II:::cmp
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// "dispose <imm5>, <list12>"
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0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
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*v850e
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*v850e1
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"dispose <imm5>, <list12>":RRRRR == 0
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"dispose <imm5>, <list12>, [reg1]"
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{
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@ -322,6 +332,7 @@ rrrrr,010011,iiiii:II:::cmp
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// DIV
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rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
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*v850e
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*v850e1
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"div r<reg1>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_2C007E0 ());
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@ -378,6 +389,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh
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rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
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*v850e
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*v850e1
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"divh r<reg1>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_28007E0 ());
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@ -387,6 +399,7 @@ rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
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// DIVHU
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rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
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*v850e
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*v850e1
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"divhu r<reg1>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_28207E0 ());
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@ -396,6 +409,7 @@ rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
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// DIVU
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rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
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*v850e
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*v850e1
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"divu r<reg1>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_2C207E0 ());
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@ -423,6 +437,7 @@ rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
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// HSW
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rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
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*v850e
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*v850e1
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"hsw r<reg2>, r<reg3>"
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{
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unsigned32 value;
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@ -497,6 +512,7 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
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rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
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*v850e
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*v850e1
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"ld.bu <disp16>[r<reg1>], r<reg2>"
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{
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COMPAT_2 (OP_10780 ());
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@ -504,6 +520,7 @@ rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
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rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
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*v850e
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*v850e1
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"ld.hu <disp16>[r<reg1>], r<reg2>"
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{
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COMPAT_2 (OP_107E0 ());
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@ -544,6 +561,7 @@ rrrrr!0,010000,iiiii:II:::mov
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00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
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*v850e
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*v850e1
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"mov <imm32>, r<reg1>"
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{
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SAVE_2;
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@ -577,6 +595,7 @@ rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
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// MUL
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rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
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*v850e
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*v850e1
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"mul r<reg1>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_22007E0 ());
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@ -584,6 +603,7 @@ rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
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rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
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*v850e
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*v850e1
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"mul <imm9>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_24007E0 ());
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@ -617,6 +637,7 @@ rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
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// MULU
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rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
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*v850e
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*v850e1
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"mulu r<reg1>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_22207E0 ());
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@ -624,6 +645,7 @@ rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
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rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
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*v850e
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*v850e1
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"mulu <imm9>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_24207E0 ());
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@ -658,6 +680,7 @@ rrrrr,000001,RRRRR:I:::not
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rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
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*v850e
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*v850e1
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"not1 r<reg2>, r<reg1>"
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{
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COMPAT_2 (OP_E207E0 ());
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@ -686,6 +709,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
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// PREPARE
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0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
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*v850e
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*v850e1
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"prepare <list12>, <imm5>"
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{
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int i;
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@ -710,6 +734,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
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0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
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*v850e
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*v850e1
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"prepare <list12>, <imm5>, sp"
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{
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COMPAT_2 (OP_30780 ());
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@ -717,6 +742,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
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0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
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*v850e
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*v850e1
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"prepare <list12>, <imm5>, <uimm16>"
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{
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COMPAT_2 (OP_B0780 ());
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@ -724,6 +750,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
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0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
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*v850e
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*v850e1
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"prepare <list12>, <imm5>, <uimm16>"
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{
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COMPAT_2 (OP_130780 ());
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@ -731,6 +758,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
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0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
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*v850e
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*v850e1
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"prepare <list12>, <imm5>, <uimm32>"
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{
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COMPAT_2 (OP_1B0780 ());
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@ -780,6 +808,7 @@ rrrrr,010101,iiiii:II:::sar
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// SASF
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rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
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*v850e
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*v850e1
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"sasf %s<cccc>, r<reg2>"
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{
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COMPAT_2 (OP_20007E0 ());
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@ -848,6 +877,7 @@ rrrrr,1111110,cccc + 0000000000000000:IX:::setf
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rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
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*v850e
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*v850e1
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"set1 r<reg2>, [r<reg1>]"
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{
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COMPAT_2 (OP_E007E0 ());
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@ -935,6 +965,7 @@ rrrrr,1010,dddddd,0:IV:::sld.w
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rrrrr!0,0000110,dddd:IV:::sld.bu
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*v850e
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*v850e1
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"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
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"sld.bu <disp4>[ep], r<reg2>"
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{
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@ -955,6 +986,7 @@ rrrrr!0,0000110,dddd:IV:::sld.bu
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rrrrr!0,0000111,dddd:IV:::sld.hu
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*v850e
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*v850e1
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"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
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"sld.hu <disp5>[ep], r<reg2>"
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{
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@ -1037,6 +1069,7 @@ rrrrr,001100,RRRRR:I:::subr
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// SWITCH
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00000000010,RRRRR:I:::switch
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*v850e
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*v850e1
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"switch r<reg1>"
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{
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unsigned long adr;
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@ -1050,6 +1083,7 @@ rrrrr,001100,RRRRR:I:::subr
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// SXB
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00000000101,RRRRR:I:::sxb
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*v850e
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*v850e1
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"sxb r<reg1>"
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{
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TRACE_ALU_INPUT1 (GR[reg1]);
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@ -1060,6 +1094,7 @@ rrrrr,001100,RRRRR:I:::subr
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// SXH
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00000000111,RRRRR:I:::sxh
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*v850e
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*v850e1
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"sxh r<reg1>"
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{
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TRACE_ALU_INPUT1 (GR[reg1]);
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@ -1090,6 +1125,7 @@ rrrrr,001011,RRRRR:I:::tst
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rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
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*v850e
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*v850e1
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"tst1 r<reg2>, [r<reg1>]"
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{
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COMPAT_2 (OP_E607E0 ());
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@ -1112,6 +1148,7 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
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// ZXB
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00000000100,RRRRR:I:::zxb
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*v850e
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*v850e1
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"zxb r<reg1>"
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{
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TRACE_ALU_INPUT1 (GR[reg1]);
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@ -1122,6 +1159,7 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
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// ZXH
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00000000110,RRRRR:I:::zxh
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*v850e
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*v850e1
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"zxh r<reg1>"
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{
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TRACE_ALU_INPUT1 (GR[reg1]);
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@ -1132,12 +1170,36 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
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// Right field must be zero so that it doesn't clash with DIVH
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// Left field must be non-zero so that it doesn't clash with SWITCH
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11111,000010,00000:I:::break
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*v850
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*v850e
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{
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sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
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}
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11111,000010,00000:I:::dbtrap
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*v850e1
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"dbtrap"
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{
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DBPC = cia + 2;
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DBPSW = PSW;
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PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
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PC = 0x00000060;
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nia = 0x00000060;
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TRACE_BRANCH0 ();
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}
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// New breakpoint: 0x7E0 0x7E0
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00000,111111,00000 + 00000,11111,100000:X:::ilgop
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{
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sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
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}
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// Return from debug trap: 0x146007e0
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0000011111100000 + 0000000101000110:X:::dbret
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*v850e1
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"dbret"
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{
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nia = DBPC;
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PSW = DBPSW;
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TRACE_BRANCH1 (PSW);
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}
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