MIPS: Add Imagination interAptiv MR2 GAS test infrastructure
Define a new regular MIPS and MIPS16 interAptiv MR2 test architecture and adjust existing tests now run against these architectures accordingly. This change causes new test failures: FAIL: MIPS jal-svr4pic (interaptiv-mr2) FAIL: MIPS jal-svr4pic noreorder (interaptiv-mr2) with the `mips-sgi-irix5' and `mips-sgi-irix6' targets, which are consistent with the remaining architecture results for these cases, that do not take into account the lack of R_MIPS_JALR relocations produced by GAS for these targets. As a preexisting issue these failures are not addressed with this change. gas/ * testsuite/gas/mips/mips.exp (interaptiv-mr2): New architecture. (mips16e2-interaptiv-mr2): Likewise. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-asmacro.d: New test. * testsuite/gas/mips/interaptiv-mr2@mcu.d: New test. * testsuite/gas/mips/interaptiv-mr2@isa-override-1.d: New test. * testsuite/gas/mips/interaptiv-mr2@isa-override-2.d: New test. * testsuite/gas/mips/attr-gnu-4-5.d: Ignore any number of ASE flag lines present rather than just one. * testsuite/gas/mips/attr-gnu-4-6.d: Likewise. * testsuite/gas/mips/attr-gnu-4-7.d: Likewise. * testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d: Likewise. * testsuite/gas/mips/attr-none-o32-fp64.d: Likewise. * testsuite/gas/mips/attr-none-o32-fpxx.d: Likewise. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.l: New stderr output. * testsuite/gas/mips/interaptiv-mr2@isa-override-1.l: New stderr output. * testsuite/gas/mips/interaptiv-mr2@isa-override-2.l: New stderr output.
This commit is contained in:
Maciej W. Rozycki
parent
38bf472a15
commit
c7d289d129
@ -1,3 +1,60 @@
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2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/mips.exp (interaptiv-mr2): New architecture.
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(mips16e2-interaptiv-mr2): Likewise.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.d: New
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test.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.d:
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New test.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.d:
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New test.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.d:
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New test.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.d:
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New test.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64.d: New
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test.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.d: New
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test.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.d: New
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test.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.d:
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New test.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
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New test.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-asmacro.d:
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New test.
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* testsuite/gas/mips/interaptiv-mr2@mcu.d: New test.
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* testsuite/gas/mips/interaptiv-mr2@isa-override-1.d: New test.
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* testsuite/gas/mips/interaptiv-mr2@isa-override-2.d: New test.
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* testsuite/gas/mips/attr-gnu-4-5.d: Ignore any number of ASE
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flag lines present rather than just one.
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* testsuite/gas/mips/attr-gnu-4-6.d: Likewise.
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* testsuite/gas/mips/attr-gnu-4-7.d: Likewise.
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* testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d: Likewise.
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* testsuite/gas/mips/attr-none-o32-fp64.d: Likewise.
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* testsuite/gas/mips/attr-none-o32-fpxx.d: Likewise.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.l: New
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stderr output.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.l:
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New stderr output.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.l:
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New stderr output.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.l:
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New stderr output.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l:
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New stderr output.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.l: New
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stderr output.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.l: New
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stderr output.
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* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.l:
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New stderr output.
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* testsuite/gas/mips/interaptiv-mr2@isa-override-1.l: New stderr
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output.
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* testsuite/gas/mips/interaptiv-mr2@isa-override-2.l: New stderr
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output.
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2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
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Matthew Fortune <matthew.fortune@imgtec.com>
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@ -17,7 +17,7 @@ CPR2 size: 0
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FP ABI: Hard float \(32-bit CPU, Any FPU\)
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ISA Extension: .*
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ASEs:
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.*
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#...
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FLAGS 1: 0000000.
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FLAGS 2: 00000000
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@ -17,7 +17,7 @@ CPR2 size: 0
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FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
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ISA Extension: .*
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ASEs:
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.*
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#...
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FLAGS 1: 00000001
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FLAGS 2: 00000000
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@ -17,7 +17,7 @@ CPR2 size: 0
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FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\)
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ISA Extension: .*
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ASEs:
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.*
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#...
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FLAGS 1: 00000000
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FLAGS 2: 00000000
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@ -17,7 +17,7 @@ CPR2 size: 0
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FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\)
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ISA Extension: .*
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ASEs:
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.*
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#...
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FLAGS 1: 00000000
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FLAGS 2: 00000000
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@ -17,7 +17,7 @@ CPR2 size: 0
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FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
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ISA Extension: .*
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ASEs:
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.*
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#...
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FLAGS 1: 00000001
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FLAGS 2: 00000000
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@ -17,7 +17,7 @@ CPR2 size: 0
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FP ABI: Hard float \(32-bit CPU, Any FPU\)
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ISA Extension: .*
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ASEs:
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.*
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#...
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FLAGS 1: 0000000.
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FLAGS 2: 00000000
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6
gas/testsuite/gas/mips/interaptiv-mr2@isa-override-1.d
Normal file
6
gas/testsuite/gas/mips/interaptiv-mr2@isa-override-1.d
Normal file
@ -0,0 +1,6 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: MIPS ISA override code generation
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#as: -32
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#source: isa-override-1.s
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#stderr: interaptiv-mr2@isa-override-1.l
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#dump: mips32r2@isa-override-1.d
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5
gas/testsuite/gas/mips/interaptiv-mr2@isa-override-1.l
Normal file
5
gas/testsuite/gas/mips/interaptiv-mr2@isa-override-1.l
Normal file
@ -0,0 +1,5 @@
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.*: Assembler messages:
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.*:10: Warning: the `dsp' extension requires MIPS64 revision 2 or greater
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.*:10: Warning: the `eva' extension requires MIPS64 revision 2 or greater
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.*:10: Warning: the `mt' extension requires MIPS64 revision 2 or greater
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.*:10: Warning: the `mips16e2' extension requires MIPS64 revision 2 or greater
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4
gas/testsuite/gas/mips/interaptiv-mr2@isa-override-2.d
Normal file
4
gas/testsuite/gas/mips/interaptiv-mr2@isa-override-2.d
Normal file
@ -0,0 +1,4 @@
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#name: MIPS ISA override code generation 2
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#as: -32
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#source: isa-override-2.s
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#error-output: interaptiv-mr2@isa-override-2.l
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8
gas/testsuite/gas/mips/interaptiv-mr2@isa-override-2.l
Normal file
8
gas/testsuite/gas/mips/interaptiv-mr2@isa-override-2.l
Normal file
@ -0,0 +1,8 @@
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.*: Assembler messages:
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.*:5: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dli \$2,0x9000000080000000'
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.*:7: Warning: the `dsp' extension requires MIPS64 revision 2 or greater
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.*:7: Warning: the `eva' extension requires MIPS64 revision 2 or greater
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.*:7: Warning: the `mt' extension requires MIPS64 revision 2 or greater
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.*:7: Warning: the `mips16e2' extension requires MIPS64 revision 2 or greater
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.*:10: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dli \$2,0x9000000080000000'
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.*:13: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dli \$2,0x9000000080000000'
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110
gas/testsuite/gas/mips/interaptiv-mr2@mcu.d
Normal file
110
gas/testsuite/gas/mips/interaptiv-mr2@mcu.d
Normal file
@ -0,0 +1,110 @@
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#objdump: -dr --show-raw-insn
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#name: MCU for MIPS32r2
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#as: -32
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#source: mcu.s
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.*: +file format .*mips.*
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Disassembly of section \.text:
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[0-9a-f]+ <foo>:
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[ 0-9a-f]+: 42000038 c0 0x38
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[ 0-9a-f]+: 04070000 0x4070000
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[ 0-9a-f]+: 04070000 0x4070000
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[ 0-9a-f]+: 04070000 0x4070000
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[ 0-9a-f]+: 04071000 0x4071000
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[ 0-9a-f]+: 04072000 0x4072000
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[ 0-9a-f]+: 04073000 0x4073000
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[ 0-9a-f]+: 04074000 0x4074000
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[ 0-9a-f]+: 04075000 0x4075000
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[ 0-9a-f]+: 04076000 0x4076000
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[ 0-9a-f]+: 04077000 0x4077000
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[ 0-9a-f]+: 04477000 0x4477000
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[ 0-9a-f]+: 07e77000 0x7e77000
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[ 0-9a-f]+: 07e777ff 0x7e777ff
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[ 0-9a-f]+: 07e77800 0x7e77800
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[ 0-9a-f]+: 27e10800 addiu at,ra,2048
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[ 0-9a-f]+: 04277000 0x4277000
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[ 0-9a-f]+: 27e1f7ff addiu at,ra,-2049
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[ 0-9a-f]+: 04277000 0x4277000
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[ 0-9a-f]+: 27e17fff addiu at,ra,32767
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[ 0-9a-f]+: 04277000 0x4277000
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[ 0-9a-f]+: 27e18000 addiu at,ra,-32768
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[ 0-9a-f]+: 04277000 0x4277000
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[ 0-9a-f]+: 3c010001 lui at,0x1
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 04277fff 0x4277fff
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[ 0-9a-f]+: 3c010001 lui at,0x1
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 04277000 0x4277000
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[ 0-9a-f]+: 3c01ffff lui at,0xffff
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 04277000 0x4277000
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[ 0-9a-f]+: 24818000 addiu at,a0,-32768
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[ 0-9a-f]+: 04277000 0x4277000
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[ 0-9a-f]+: 3c01ffff lui at,0xffff
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 04277001 0x4277001
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[ 0-9a-f]+: 24818001 addiu at,a0,-32767
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[ 0-9a-f]+: 04277000 0x4277000
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[ 0-9a-f]+: 3c01f000 lui at,0xf000
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 04277000 0x4277000
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[ 0-9a-f]+: 04877fff 0x4877fff
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[ 0-9a-f]+: 3c011234 lui at,0x1234
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[ 0-9a-f]+: 34215000 ori at,at,0x5000
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 04277678 0x4277678
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[ 0-9a-f]+: 24610000 addiu at,v1,0
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[ ]*[0-9a-f]+: R_MIPS_LO16 foo
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[ 0-9a-f]+: 04271000 0x4271000
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[ 0-9a-f]+: 24610000 addiu at,v1,0
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[ ]*[0-9a-f]+: R_MIPS_LO16 foo
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[ 0-9a-f]+: 04279000 0x4279000
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[ 0-9a-f]+: 04078000 0x4078000
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[ 0-9a-f]+: 04078000 0x4078000
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[ 0-9a-f]+: 04078000 0x4078000
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[ 0-9a-f]+: 04079000 0x4079000
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[ 0-9a-f]+: 0407a000 0x407a000
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[ 0-9a-f]+: 0407b000 0x407b000
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[ 0-9a-f]+: 0407c000 0x407c000
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[ 0-9a-f]+: 0407d000 0x407d000
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[ 0-9a-f]+: 0407e000 0x407e000
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[ 0-9a-f]+: 0407f000 0x407f000
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[ 0-9a-f]+: 0447f000 0x447f000
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[ 0-9a-f]+: 07e7f000 0x7e7f000
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[ 0-9a-f]+: 07e7f7ff 0x7e7f7ff
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[ 0-9a-f]+: 07e7f800 0x7e7f800
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[ 0-9a-f]+: 27e10800 addiu at,ra,2048
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[ 0-9a-f]+: 0427f000 0x427f000
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[ 0-9a-f]+: 27e1f7ff addiu at,ra,-2049
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[ 0-9a-f]+: 0427f000 0x427f000
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[ 0-9a-f]+: 27e17fff addiu at,ra,32767
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[ 0-9a-f]+: 0427f000 0x427f000
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[ 0-9a-f]+: 27e18000 addiu at,ra,-32768
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[ 0-9a-f]+: 0427f000 0x427f000
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[ 0-9a-f]+: 3c010001 lui at,0x1
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 0427ffff 0x427ffff
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[ 0-9a-f]+: 3c010001 lui at,0x1
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 0427f000 0x427f000
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[ 0-9a-f]+: 3c01ffff lui at,0xffff
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 0427f000 0x427f000
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[ 0-9a-f]+: 24818000 addiu at,a0,-32768
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[ 0-9a-f]+: 0427f000 0x427f000
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[ 0-9a-f]+: 3c01ffff lui at,0xffff
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 0427f001 0x427f001
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[ 0-9a-f]+: 24818001 addiu at,a0,-32767
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[ 0-9a-f]+: 0427f000 0x427f000
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[ 0-9a-f]+: 3c01f000 lui at,0xf000
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 0427f000 0x427f000
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[ 0-9a-f]+: 0487ffff 0x487ffff
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[ 0-9a-f]+: 3c011234 lui at,0x1234
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[ 0-9a-f]+: 34215000 ori at,at,0x5000
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[ 0-9a-f]+: 00240821 addu at,at,a0
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[ 0-9a-f]+: 0427f678 0x427f678
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\.\.\.
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@ -513,6 +513,9 @@ mips_arch_create r4000 64 mips3 {} \
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{ -march=r4000 -mtune=r4000 } { -mmips:4000 }
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mips_arch_create vr5400 64 mips4 { ror } \
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{ -march=vr5400 -mtune=vr5400 } { -mmips:5400 }
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mips_arch_create interaptiv-mr2 32 mips32r3 {} \
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{ -march=interaptiv-mr2 -mtune=interaptiv-mr2 } \
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{ -mmips:interaptiv-mr2 }
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mips_arch_create sb1 64 mips64 { mips3d oddspreg } \
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{ -march=sb1 -mtune=sb1 } { -mmips:sb1 } \
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{ mipsisa64sb1-*-* mipsisa64sb1el-*-* }
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@ -533,6 +536,9 @@ mips_arch_create xlr 64 mips64 { oddspreg } \
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mips_arch_create r5900 64 mips3 { gpr_ilocks singlefloat nollsc } \
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{ -march=r5900 -mtune=r5900 } { -mmips:5900 } \
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{ mipsr5900el-*-* mips64r5900el-*-* }
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mips_arch_create mips16e2-interaptiv-mr2 32 mips16e2-32 {} \
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{ -march=interaptiv-mr2 -mips16 } \
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{ -mmips:interaptiv-mr2 }
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#
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# And now begin the actual tests! VxWorks uses RELA rather than REL
|
||||
|
||||
@ -0,0 +1,15 @@
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
#name: MIPS16 ASMACRO instruction
|
||||
#as: -32
|
||||
#source: mips16-asmacro.s
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
[0-9a-f]+ <[^>]*> f000 e000 ucopyw s0,s0,0,1
|
||||
[0-9a-f]+ <[^>]*> f0a4 e341 asmacro 0x0,0x1,0x2,0x3,0x4,0x5
|
||||
[0-9a-f]+ <[^>]*> f0e0 e71f asmacro 0x0,0x1f,0x0,0x7,0x0,0x7
|
||||
[0-9a-f]+ <[^>]*> f501 e264 asmacro 0x5,0x4,0x3,0x2,0x1,0x0
|
||||
[0-9a-f]+ <[^>]*> f71f e0e0 asmacro 0x7,0x0,0x7,0x0,0x1f,0x0
|
||||
[0-9a-f]+ <[^>]*> f7ff e7ff asmacro 0x7,0x1f,0x7,0x7,0x1f,0x7
|
||||
\.\.\.
|
||||
@ -0,0 +1,4 @@
|
||||
#as: -32
|
||||
#name: MIPS16 explicit extended instructions
|
||||
#error-output: mips16e2-interaptiv-mr2@mips16-insn-e.l
|
||||
#source: mips16-insn-e.s
|
||||
131
gas/testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l
Normal file
131
gas/testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l
Normal file
@ -0,0 +1,131 @@
|
||||
.*: Assembler messages:
|
||||
.*:4: Warning: extended operand requested but not required
|
||||
.*:5: Warning: extended operand requested but not required
|
||||
.*:8: Warning: extended operand requested but not required
|
||||
.*:9: Warning: extended operand requested but not required
|
||||
.*:23: Warning: extended operand requested but not required
|
||||
.*:24: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsll\.e \$16,\$16,8'
|
||||
.*:25: Warning: extended operand requested but not required
|
||||
.*:26: Warning: extended operand requested but not required
|
||||
.*:28: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.e \$16,0\(\$16\)'
|
||||
.*:30: Warning: extended operand requested but not required
|
||||
.*:31: Warning: extended operand requested but not required
|
||||
.*:32: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.e \$16,\$16,0'
|
||||
.*:33: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$16,\$16,0'
|
||||
.*:35: Warning: extended operand requested but not required
|
||||
.*:36: Warning: extended operand requested but not required
|
||||
.*:38: Warning: extended operand requested but not required
|
||||
.*:39: Warning: extended operand requested but not required
|
||||
.*:41: Warning: extended operand requested but not required
|
||||
.*:42: Warning: extended operand requested but not required
|
||||
.*:46: Warning: extended operand requested but not required
|
||||
.*:47: Warning: extended operand requested but not required
|
||||
.*:48: Warning: extended operand requested but not required
|
||||
.*:49: Warning: extended operand requested but not required
|
||||
.*:50: Warning: extended operand requested but not required
|
||||
.*:53: Error: unrecognized extended version of MIPS16 opcode `nop\.e '
|
||||
.*:54: Error: unrecognized extended version of MIPS16 opcode `move\.e \$0,\$16'
|
||||
.*:55: Error: unrecognized extended version of MIPS16 opcode `move\.e \$16,\$0'
|
||||
.*:57: Warning: extended operand requested but not required
|
||||
.*:59: Warning: extended operand requested but not required
|
||||
.*:60: Warning: extended operand requested but not required
|
||||
.*:62: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `sd\.e \$16,0\(\$16\)'
|
||||
.*:64: Warning: extended operand requested but not required
|
||||
.*:66: Warning: extended operand requested but not required
|
||||
.*:68: Warning: extended operand requested but not required
|
||||
.*:70: Warning: extended operand requested but not required
|
||||
.*:72: Warning: extended operand requested but not required
|
||||
.*:74: Warning: extended operand requested but not required
|
||||
.*:77: Warning: extended operand requested but not required
|
||||
.*:80: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `lwu\.e \$16,0\(\$16\)'
|
||||
.*:82: Warning: extended operand requested but not required
|
||||
.*:84: Warning: extended operand requested but not required
|
||||
.*:86: Warning: extended operand requested but not required
|
||||
.*:88: Warning: extended operand requested but not required
|
||||
.*:90: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$16,\$16,\$16'
|
||||
.*:91: Error: operand 3 must be an immediate expression `addu\.e \$16,\$16,\$16'
|
||||
.*:92: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.e \$16,\$16,\$16'
|
||||
.*:93: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$16,\$16,\$16'
|
||||
.*:95: Error: unrecognized extended version of MIPS16 opcode `jr\.e \$16'
|
||||
.*:97: Error: unrecognized extended version of MIPS16 opcode `j\.e \$16'
|
||||
.*:99: Error: unrecognized extended version of MIPS16 opcode `jr\.e \$31'
|
||||
.*:101: Error: unrecognized extended version of MIPS16 opcode `j\.e \$31'
|
||||
.*:103: Error: unrecognized extended version of MIPS16 opcode `jalr\.e \$16'
|
||||
.*:105: Error: unrecognized extended version of MIPS16 opcode `jalr\.e \$31,\$16'
|
||||
.*:107: Error: operand 1 must be an immediate expression `jal\.e \$16'
|
||||
.*:109: Error: operand 1 must be an immediate expression `jal\.e \$31,\$16'
|
||||
.*:111: Error: unrecognized extended version of MIPS16 opcode `jrc\.e \$16'
|
||||
.*:112: Error: unrecognized extended version of MIPS16 opcode `jrc\.e \$31'
|
||||
.*:113: Error: unrecognized extended version of MIPS16 opcode `jalrc\.e \$16'
|
||||
.*:114: Error: unrecognized extended version of MIPS16 opcode `jalrc\.e \$31,\$16'
|
||||
.*:115: Error: unrecognized extended version of MIPS16 opcode `sdbbp\.e 0'
|
||||
.*:116: Error: operand 2 must be an immediate expression `slt\.e \$16,\$16'
|
||||
.*:117: Error: operand 2 must be an immediate expression `sltu\.e \$16,\$16'
|
||||
.*:118: Error: unrecognized extended version of MIPS16 opcode `sllv\.e \$16,\$16'
|
||||
.*:119: Error: operand 2 must be an immediate expression `sll\.e \$16,\$16'
|
||||
.*:120: Error: unrecognized extended version of MIPS16 opcode `break\.e 0'
|
||||
.*:121: Error: unrecognized extended version of MIPS16 opcode `srlv\.e \$16,\$16'
|
||||
.*:122: Error: operand 2 must be an immediate expression `srl\.e \$16,\$16'
|
||||
.*:123: Error: unrecognized extended version of MIPS16 opcode `srav\.e \$16,\$16'
|
||||
.*:124: Error: operand 2 must be an immediate expression `sra\.e \$16,\$16'
|
||||
.*:125: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsrl\.e \$16,8'
|
||||
.*:126: Error: unrecognized extended version of MIPS16 opcode `entry\.e '
|
||||
.*:127: Error: unrecognized extended version of MIPS16 opcode `entry\.e \$31'
|
||||
.*:128: Error: unrecognized extended version of MIPS16 opcode `exit\.e \$f0'
|
||||
.*:129: Error: unrecognized extended version of MIPS16 opcode `exit\.e'
|
||||
.*:130: Error: operand 2 must be an immediate expression `cmp\.e \$16,\$16'
|
||||
.*:131: Error: unrecognized extended version of MIPS16 opcode `neg\.e \$16,\$16'
|
||||
.*:132: Error: unrecognized extended version of MIPS16 opcode `and\.e \$16,\$16'
|
||||
.*:133: Error: unrecognized extended version of MIPS16 opcode `or\.e \$16,\$16'
|
||||
.*:134: Error: unrecognized extended version of MIPS16 opcode `xor\.e \$16,\$16'
|
||||
.*:135: Error: unrecognized extended version of MIPS16 opcode `not\.e \$16,\$16'
|
||||
.*:136: Error: unrecognized extended version of MIPS16 opcode `mfhi\.e \$16'
|
||||
.*:137: Error: unrecognized extended version of MIPS16 opcode `zeb\.e \$16'
|
||||
.*:138: Error: unrecognized extended version of MIPS16 opcode `zeh\.e \$16'
|
||||
.*:139: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `zew\.e \$16'
|
||||
.*:140: Error: unrecognized extended version of MIPS16 opcode `seb\.e \$16'
|
||||
.*:141: Error: unrecognized extended version of MIPS16 opcode `seh\.e \$16'
|
||||
.*:142: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `sew\.e \$16'
|
||||
.*:143: Error: unrecognized extended version of MIPS16 opcode `mflo\.e \$16'
|
||||
.*:144: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsra\.e \$16,8'
|
||||
.*:145: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsllv\.e \$16,\$16'
|
||||
.*:146: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsll\.e \$16,\$16'
|
||||
.*:147: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsrlv\.e \$16,\$16'
|
||||
.*:148: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsrl\.e \$16,\$16'
|
||||
.*:149: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsrav\.e \$16,\$16'
|
||||
.*:150: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsra\.e \$16,\$16'
|
||||
.*:151: Error: unrecognized extended version of MIPS16 opcode `mult\.e \$16,\$16'
|
||||
.*:152: Error: unrecognized extended version of MIPS16 opcode `multu\.e \$16,\$16'
|
||||
.*:153: Error: unrecognized extended version of MIPS16 opcode `div\.e \$0,\$16,\$16'
|
||||
.*:154: Error: unrecognized extended version of MIPS16 opcode `rem\.e \$0,\$16,\$16'
|
||||
.*:155: Error: unrecognized extended version of MIPS16 opcode `divu\.e \$0,\$16,\$16'
|
||||
.*:156: Error: unrecognized extended version of MIPS16 opcode `remu\.e \$0,\$16,\$16'
|
||||
.*:157: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dmult\.e \$16,\$16'
|
||||
.*:158: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dmultu\.e \$16,\$16'
|
||||
.*:159: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ddiv\.e \$0,\$16,\$16'
|
||||
.*:160: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `drem\.e \$0,\$16,\$16'
|
||||
.*:161: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ddivu\.e \$0,\$16,\$16'
|
||||
.*:162: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dremu\.e \$0,\$16,\$16'
|
||||
.*:164: Error: unrecognized extended version of MIPS16 opcode `extend\.e 0'
|
||||
.*:166: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.e \$16,0\(\$29\)'
|
||||
.*:167: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `sd\.e \$16,0\(\$29\)'
|
||||
.*:168: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `sd\.e \$31,0\(\$29\)'
|
||||
.*:169: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.e \$29,0'
|
||||
.*:170: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.e \$29,\$29,0'
|
||||
.*:171: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$29,0'
|
||||
.*:172: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$29,\$29,0'
|
||||
.*:174: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.e \$16,0\(\$pc\)'
|
||||
.*:175: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.e \$16,\.-3'
|
||||
.*:176: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.e \$16,0'
|
||||
.*:177: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$16,0'
|
||||
.*:179: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.e \$16,\$pc,0'
|
||||
.*:180: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$16,\$pc,0'
|
||||
.*:181: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dla\.e \$16,\.-1'
|
||||
.*:182: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.e \$16,\$sp,0'
|
||||
.*:183: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$16,\$sp,0'
|
||||
.*:10: Warning: extended operand requested but not required
|
||||
.*:12: Warning: extended operand requested but not required
|
||||
.*:19: Warning: extended operand requested but not required
|
||||
.*:21: Warning: extended operand requested but not required
|
||||
.*:44: Warning: extended operand requested but not required
|
||||
.*:45: Warning: extended operand requested but not required
|
||||
@ -0,0 +1,4 @@
|
||||
#as: -32
|
||||
#name: MIPS16 explicit unextended instructions
|
||||
#error-output: mips16e2-interaptiv-mr2@mips16-insn-t.l
|
||||
#source: mips16-insn-t.s
|
||||
@ -0,0 +1,43 @@
|
||||
.*: Assembler messages:
|
||||
.*:14: Error: invalid operands `jal\.t 0'
|
||||
.*:16: Error: unrecognized unextended version of MIPS16 opcode `jalx\.t 0'
|
||||
.*:24: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsll\.t \$16,\$16,8'
|
||||
.*:28: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.t \$16,0\(\$16\)'
|
||||
.*:32: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.t \$16,\$16,0'
|
||||
.*:33: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$16,\$16,0'
|
||||
.*:62: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `sd\.t \$16,0\(\$16\)'
|
||||
.*:80: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `lwu\.t \$16,0\(\$16\)'
|
||||
.*:90: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$16,\$16,\$16'
|
||||
.*:92: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.t \$16,\$16,\$16'
|
||||
.*:125: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsrl\.t \$16,8'
|
||||
.*:139: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `zew\.t \$16'
|
||||
.*:142: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `sew\.t \$16'
|
||||
.*:144: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsra\.t \$16,8'
|
||||
.*:145: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsllv\.t \$16,\$16'
|
||||
.*:146: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsll\.t \$16,\$16'
|
||||
.*:147: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsrlv\.t \$16,\$16'
|
||||
.*:148: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsrl\.t \$16,\$16'
|
||||
.*:149: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsrav\.t \$16,\$16'
|
||||
.*:150: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsra\.t \$16,\$16'
|
||||
.*:157: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dmult\.t \$16,\$16'
|
||||
.*:158: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dmultu\.t \$16,\$16'
|
||||
.*:159: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ddiv\.t \$0,\$16,\$16'
|
||||
.*:160: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `drem\.t \$0,\$16,\$16'
|
||||
.*:161: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ddivu\.t \$0,\$16,\$16'
|
||||
.*:162: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dremu\.t \$0,\$16,\$16'
|
||||
.*:166: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.t \$16,0\(\$29\)'
|
||||
.*:167: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `sd\.t \$16,0\(\$29\)'
|
||||
.*:168: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `sd\.t \$31,0\(\$29\)'
|
||||
.*:169: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.t \$29,0'
|
||||
.*:170: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.t \$29,\$29,0'
|
||||
.*:171: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$29,0'
|
||||
.*:172: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$29,\$29,0'
|
||||
.*:174: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.t \$16,0\(\$pc\)'
|
||||
.*:175: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.t \$16,\.-3'
|
||||
.*:176: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.t \$16,0'
|
||||
.*:177: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$16,0'
|
||||
.*:179: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.t \$16,\$pc,0'
|
||||
.*:180: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$16,\$pc,0'
|
||||
.*:181: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dla\.t \$16,\.-1'
|
||||
.*:182: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.t \$16,\$sp,0'
|
||||
.*:183: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$16,\$sp,0'
|
||||
@ -0,0 +1,4 @@
|
||||
#as: -32
|
||||
#name: MIPS16 explicit extended macros
|
||||
#source: mips16-macro-e.s
|
||||
#error-output: mips16e2-interaptiv-mr2@mips16-macro-e.l
|
||||
@ -0,0 +1,56 @@
|
||||
.*: Assembler messages:
|
||||
.*:4: Error: unrecognized extended version of MIPS16 opcode `div\.e \$2,\$3,\$4'
|
||||
.*:5: Error: unrecognized extended version of MIPS16 opcode `divu\.e \$3,\$4,\$5'
|
||||
.*:6: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ddiv\.e \$4,\$5,\$6'
|
||||
.*:7: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ddivu\.e \$5,\$6,\$7'
|
||||
.*:8: Error: unrecognized extended version of MIPS16 opcode `rem\.e \$6,\$7,\$16'
|
||||
.*:9: Error: unrecognized extended version of MIPS16 opcode `remu\.e \$6,\$7,\$17'
|
||||
.*:10: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `drem\.e \$2,\$3,\$4'
|
||||
.*:11: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dremu\.e \$3,\$4,\$5'
|
||||
.*:12: Error: unrecognized extended version of MIPS16 opcode `mul\.e \$4,\$5,\$6'
|
||||
.*:13: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dmul\.e \$5,\$6,\$7'
|
||||
.*:14: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$2,-32767'
|
||||
.*:15: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$3,16'
|
||||
.*:16: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$4,32768'
|
||||
.*:17: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$3,\$7,-16383'
|
||||
.*:18: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$4,\$16,4'
|
||||
.*:19: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$5,\$17,16384'
|
||||
.*:20: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.e \$4,-32767'
|
||||
.*:21: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.e \$6,6'
|
||||
.*:22: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.e \$7,32768'
|
||||
.*:23: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.e \$2,\$4,-16383'
|
||||
.*:24: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.e \$3,\$7,8'
|
||||
.*:25: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.e \$4,\$5,16384'
|
||||
.*:26: Error: unrecognized extended version of MIPS16 opcode `beq\.e \$2,\$3,1b'
|
||||
.*:27: Error: unrecognized extended version of MIPS16 opcode `bne\.e \$4,\$5,1b'
|
||||
.*:28: Error: unrecognized extended version of MIPS16 opcode `blt\.e \$6,\$7,1b'
|
||||
.*:29: Error: unrecognized extended version of MIPS16 opcode `bltu\.e \$16,\$17,1b'
|
||||
.*:30: Error: unrecognized extended version of MIPS16 opcode `ble\.e \$4,\$7,1b'
|
||||
.*:31: Error: unrecognized extended version of MIPS16 opcode `bleu\.e \$5,\$6,1b'
|
||||
.*:32: Error: unrecognized extended version of MIPS16 opcode `bge\.e \$4,\$16,1b'
|
||||
.*:33: Error: unrecognized extended version of MIPS16 opcode `bgeu\.e \$5,\$17,1b'
|
||||
.*:34: Error: unrecognized extended version of MIPS16 opcode `bgt\.e \$4,\$6,1b'
|
||||
.*:35: Error: unrecognized extended version of MIPS16 opcode `bgtu\.e \$5,\$7,1b'
|
||||
.*:36: Error: unrecognized extended version of MIPS16 opcode `beq\.e \$2,1,1b'
|
||||
.*:37: Error: unrecognized extended version of MIPS16 opcode `beq\.e \$3,65535,1b'
|
||||
.*:38: Error: unrecognized extended version of MIPS16 opcode `bne\.e \$4,1,1b'
|
||||
.*:39: Error: unrecognized extended version of MIPS16 opcode `bne\.e \$5,65535,1b'
|
||||
.*:40: Error: unrecognized extended version of MIPS16 opcode `blt\.e \$6,-32768,1b'
|
||||
.*:41: Error: unrecognized extended version of MIPS16 opcode `blt\.e \$7,32767,1b'
|
||||
.*:42: Error: unrecognized extended version of MIPS16 opcode `bltu\.e \$16,-32768,1b'
|
||||
.*:43: Error: unrecognized extended version of MIPS16 opcode `bltu\.e \$17,32767,1b'
|
||||
.*:44: Error: unrecognized extended version of MIPS16 opcode `ble\.e \$2,-32769,1b'
|
||||
.*:45: Error: unrecognized extended version of MIPS16 opcode `ble\.e \$3,32766,1b'
|
||||
.*:46: Error: unrecognized extended version of MIPS16 opcode `bleu\.e \$4,-32769,1b'
|
||||
.*:47: Error: unrecognized extended version of MIPS16 opcode `bleu\.e \$5,32766,1b'
|
||||
.*:48: Error: unrecognized extended version of MIPS16 opcode `bge\.e \$6,-32768,1b'
|
||||
.*:49: Error: unrecognized extended version of MIPS16 opcode `bge\.e \$7,32766,1b'
|
||||
.*:50: Error: unrecognized extended version of MIPS16 opcode `bgeu\.e \$16,-32768,1b'
|
||||
.*:51: Error: unrecognized extended version of MIPS16 opcode `bgeu\.e \$17,32767,1b'
|
||||
.*:52: Error: unrecognized extended version of MIPS16 opcode `bgt\.e \$2,-32769,1b'
|
||||
.*:53: Error: unrecognized extended version of MIPS16 opcode `bgt\.e \$3,32766,1b'
|
||||
.*:54: Error: unrecognized extended version of MIPS16 opcode `bgtu\.e \$4,-32769,1b'
|
||||
.*:55: Error: unrecognized extended version of MIPS16 opcode `bgtu\.e \$5,32766,1b'
|
||||
.*:56: Error: unrecognized extended version of MIPS16 opcode `abs\.e \$2'
|
||||
.*:57: Error: unrecognized extended version of MIPS16 opcode `abs\.e \$3,\$3'
|
||||
.*:58: Error: unrecognized extended version of MIPS16 opcode `abs\.e \$4,\$5'
|
||||
@ -0,0 +1,4 @@
|
||||
#as: -32
|
||||
#name: MIPS16 explicit unextended macros
|
||||
#source: mips16-macro-t.s
|
||||
#error-output: mips16e2-interaptiv-mr2@mips16-macro-t.l
|
||||
@ -0,0 +1,56 @@
|
||||
.*: Assembler messages:
|
||||
.*:4: Error: invalid operands `div\.t \$2,\$3,\$4'
|
||||
.*:5: Error: invalid operands `divu\.t \$3,\$4,\$5'
|
||||
.*:6: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ddiv\.t \$4,\$5,\$6'
|
||||
.*:7: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ddivu\.t \$5,\$6,\$7'
|
||||
.*:8: Error: invalid operands `rem\.t \$6,\$7,\$16'
|
||||
.*:9: Error: invalid operands `remu\.t \$6,\$7,\$17'
|
||||
.*:10: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `drem\.t \$2,\$3,\$4'
|
||||
.*:11: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dremu\.t \$3,\$4,\$5'
|
||||
.*:12: Error: unrecognized unextended version of MIPS16 opcode `mul\.t \$4,\$5,\$6'
|
||||
.*:13: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dmul\.t \$5,\$6,\$7'
|
||||
.*:14: Error: invalid operands `subu\.t \$2,-32767'
|
||||
.*:15: Error: invalid operands `subu\.t \$3,16'
|
||||
.*:16: Error: invalid operands `subu\.t \$4,32768'
|
||||
.*:17: Error: invalid operands `subu\.t \$3,\$7,-16383'
|
||||
.*:18: Error: invalid operands `subu\.t \$4,\$16,4'
|
||||
.*:19: Error: invalid operands `subu\.t \$5,\$17,16384'
|
||||
.*:20: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.t \$4,-32767'
|
||||
.*:21: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.t \$6,6'
|
||||
.*:22: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.t \$7,32768'
|
||||
.*:23: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.t \$2,\$4,-16383'
|
||||
.*:24: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.t \$3,\$7,8'
|
||||
.*:25: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu\.t \$4,\$5,16384'
|
||||
.*:26: Error: unrecognized unextended version of MIPS16 opcode `beq\.t \$2,\$3,1b'
|
||||
.*:27: Error: unrecognized unextended version of MIPS16 opcode `bne\.t \$4,\$5,1b'
|
||||
.*:28: Error: unrecognized unextended version of MIPS16 opcode `blt\.t \$6,\$7,1b'
|
||||
.*:29: Error: unrecognized unextended version of MIPS16 opcode `bltu\.t \$16,\$17,1b'
|
||||
.*:30: Error: unrecognized unextended version of MIPS16 opcode `ble\.t \$4,\$7,1b'
|
||||
.*:31: Error: unrecognized unextended version of MIPS16 opcode `bleu\.t \$5,\$6,1b'
|
||||
.*:32: Error: unrecognized unextended version of MIPS16 opcode `bge\.t \$4,\$16,1b'
|
||||
.*:33: Error: unrecognized unextended version of MIPS16 opcode `bgeu\.t \$5,\$17,1b'
|
||||
.*:34: Error: unrecognized unextended version of MIPS16 opcode `bgt\.t \$4,\$6,1b'
|
||||
.*:35: Error: unrecognized unextended version of MIPS16 opcode `bgtu\.t \$5,\$7,1b'
|
||||
.*:36: Error: unrecognized unextended version of MIPS16 opcode `beq\.t \$2,1,1b'
|
||||
.*:37: Error: unrecognized unextended version of MIPS16 opcode `beq\.t \$3,65535,1b'
|
||||
.*:38: Error: unrecognized unextended version of MIPS16 opcode `bne\.t \$4,1,1b'
|
||||
.*:39: Error: unrecognized unextended version of MIPS16 opcode `bne\.t \$5,65535,1b'
|
||||
.*:40: Error: unrecognized unextended version of MIPS16 opcode `blt\.t \$6,-32768,1b'
|
||||
.*:41: Error: unrecognized unextended version of MIPS16 opcode `blt\.t \$7,32767,1b'
|
||||
.*:42: Error: unrecognized unextended version of MIPS16 opcode `bltu\.t \$16,-32768,1b'
|
||||
.*:43: Error: unrecognized unextended version of MIPS16 opcode `bltu\.t \$17,32767,1b'
|
||||
.*:44: Error: unrecognized unextended version of MIPS16 opcode `ble\.t \$2,-32769,1b'
|
||||
.*:45: Error: unrecognized unextended version of MIPS16 opcode `ble\.t \$3,32766,1b'
|
||||
.*:46: Error: unrecognized unextended version of MIPS16 opcode `bleu\.t \$4,-32769,1b'
|
||||
.*:47: Error: unrecognized unextended version of MIPS16 opcode `bleu\.t \$5,32766,1b'
|
||||
.*:48: Error: unrecognized unextended version of MIPS16 opcode `bge\.t \$6,-32768,1b'
|
||||
.*:49: Error: unrecognized unextended version of MIPS16 opcode `bge\.t \$7,32766,1b'
|
||||
.*:50: Error: unrecognized unextended version of MIPS16 opcode `bgeu\.t \$16,-32768,1b'
|
||||
.*:51: Error: unrecognized unextended version of MIPS16 opcode `bgeu\.t \$17,32767,1b'
|
||||
.*:52: Error: unrecognized unextended version of MIPS16 opcode `bgt\.t \$2,-32769,1b'
|
||||
.*:53: Error: unrecognized unextended version of MIPS16 opcode `bgt\.t \$3,32766,1b'
|
||||
.*:54: Error: unrecognized unextended version of MIPS16 opcode `bgtu\.t \$4,-32769,1b'
|
||||
.*:55: Error: unrecognized unextended version of MIPS16 opcode `bgtu\.t \$5,32766,1b'
|
||||
.*:56: Error: unrecognized unextended version of MIPS16 opcode `abs\.t \$2'
|
||||
.*:57: Error: unrecognized unextended version of MIPS16 opcode `abs\.t \$3,\$3'
|
||||
.*:58: Error: unrecognized unextended version of MIPS16 opcode `abs\.t \$4,\$5'
|
||||
@ -0,0 +1,5 @@
|
||||
#objdump: -dr -Mgpr-names=numeric
|
||||
#as: -32
|
||||
#name: MIPS16 macros
|
||||
#source: mips16-macro.s
|
||||
#error-output: mips16e2-interaptiv-mr2@mips16-macro.l
|
||||
@ -0,0 +1,12 @@
|
||||
.*: Assembler messages:
|
||||
.*:6: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ddiv \$4,\$5,\$6'
|
||||
.*:7: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ddivu \$5,\$6,\$7'
|
||||
.*:10: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `drem \$2,\$3,\$4'
|
||||
.*:11: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dremu \$3,\$4,\$5'
|
||||
.*:13: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dmul \$5,\$6,\$7'
|
||||
.*:20: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu \$4,-32767'
|
||||
.*:21: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu \$6,6'
|
||||
.*:22: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu \$7,32768'
|
||||
.*:23: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu \$2,\$4,-16383'
|
||||
.*:24: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu \$3,\$7,8'
|
||||
.*:25: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dsubu \$4,\$5,16384'
|
||||
@ -0,0 +1,6 @@
|
||||
#objdump: -dr --prefix-address --show-raw-insn
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: MIPS16 ISA subset disassembly
|
||||
#source: mips16-sub.s
|
||||
#stderr: mips16e2-interaptiv-mr2@mips16-sub.l
|
||||
#dump: mips16-32@mips16-sub.d
|
||||
@ -0,0 +1,4 @@
|
||||
.*: Assembler messages:
|
||||
.*:2: Warning: the `dsp' extension requires MIPS64 revision 2 or greater
|
||||
.*:2: Warning: the `eva' extension requires MIPS64 revision 2 or greater
|
||||
.*:2: Warning: the `mt' extension requires MIPS64 revision 2 or greater
|
||||
@ -0,0 +1,6 @@
|
||||
#objdump: -dr --prefix-address --show-raw-insn
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: MIPS16e 64-bit ISA subset disassembly
|
||||
#stderr: mips16e2-interaptiv-mr2@mips16e-64-sub.l
|
||||
#source: mips16e-64-sub.s
|
||||
#dump: mips16-32@mips16e-64-sub.d
|
||||
@ -0,0 +1,4 @@
|
||||
.*: Assembler messages:
|
||||
.*:2: Warning: the `dsp' extension requires MIPS64 revision 2 or greater
|
||||
.*:2: Warning: the `eva' extension requires MIPS64 revision 2 or greater
|
||||
.*:2: Warning: the `mt' extension requires MIPS64 revision 2 or greater
|
||||
@ -0,0 +1,4 @@
|
||||
#as: -32
|
||||
#name: MIPS16e-64
|
||||
#source: mips16e-64.s
|
||||
#error-output: mips16e-32@mips16e-64.l
|
||||
@ -0,0 +1,6 @@
|
||||
#objdump: -dr --prefix-address --show-raw-insn
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: MIPS16e ISA subset disassembly
|
||||
#stderr: mips16e2-interaptiv-mr2@mips16e-sub.l
|
||||
#source: mips16e-sub.s
|
||||
#dump: mips16e-sub.d
|
||||
@ -0,0 +1,4 @@
|
||||
.*: Assembler messages:
|
||||
.*:2: Warning: the `dsp' extension requires MIPS32 revision 2 or greater
|
||||
.*:2: Warning: the `eva' extension requires MIPS32 revision 2 or greater
|
||||
.*:2: Warning: the `mt' extension requires MIPS32 revision 2 or greater
|
||||
@ -0,0 +1,22 @@
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: MIPS16e2 MT ASE subset disassembly
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#source: mips16e2-mt-sub.s
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
[0-9a-f]+ <[^>]*> f0c0 3010 ehb
|
||||
[0-9a-f]+ <[^>]*> f026 6701 dmt
|
||||
[0-9a-f]+ <[^>]*> f026 6701 dmt
|
||||
[0-9a-f]+ <[^>]*> f022 6741 dmt v0
|
||||
[0-9a-f]+ <[^>]*> f027 6701 emt
|
||||
[0-9a-f]+ <[^>]*> f027 6701 emt
|
||||
[0-9a-f]+ <[^>]*> f023 6741 emt v0
|
||||
[0-9a-f]+ <[^>]*> f026 6700 dvpe
|
||||
[0-9a-f]+ <[^>]*> f026 6700 dvpe
|
||||
[0-9a-f]+ <[^>]*> f022 6740 dvpe v0
|
||||
[0-9a-f]+ <[^>]*> f027 6700 evpe
|
||||
[0-9a-f]+ <[^>]*> f027 6700 evpe
|
||||
[0-9a-f]+ <[^>]*> f023 6740 evpe v0
|
||||
\.\.\.
|
||||
Loading…
Reference in New Issue
Block a user