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2006-10-18 Dave Brolley <brolley@redhat.com> 

* Contribute the following changes:

        2006-06-14  Dave Brolley  <brolley@redhat.com>

        * sh64-sim.h (sh64_fipr,sh64_fiprs,sh64_fldp,sh64_fstp,sh64_ftrv)
        (sh64_fpref): New functions.
        * sh64.c (sh64_fipr,sh64_fiprs,sh64_fldp,sh64_fstp,sh64_ftrv)
        (sh64_fpref): New functions.
        (sh_models): Add sh2e, sh2a, sh2a_nofpu, sh4_nofpu, sh4a,
        sh4a_nofpu and sh4al.
        (sh2e_mach): New MACH.
        (sh2a_fpu_mach): New MACH.
        (sh2a_nofpu_mach): New MACH.
        (sh4_nofpu): New MACH.
        (sh4a_mach): New MACH.
        (sh4a_nofpu_mach): New MACH.
        (sh4al_mach): New MACH.
        * Makefile.in (stamp-*): Depend on $(CGEN_CPU_DIR)/sh-sim.cpu. Pass
        archfile to CGEN script.
        * arch.c: Regenerated.
        * arch.h: Regenerated.
        * cpu.c: Regenerated.
        * cpu.h: Regenerated.
        * cpuall.h: Regenerated.
        * decode-compact.c: Regenerated.
        * decode-compact.h: Regenerated.
        * decode-media.c: Regenerated.
        * decode-media.h: Regenerated.
        * defs-compact.h: Regenerated.
        * defs-media.h: Regenerated.
        * sem-compact-switch.c: Regenerated.
        * sem-compact.c: Regenerated.
        * sem-media-switch.c: Regenerated.
        * sem-media.c: Regenerated.
        * sh-desc.c: Regenerated.
        * sh-desc.h: Regenerated.
        * sh-opc.h: Regenerated.
This commit is contained in:
Dave Brolley 2006-10-18 18:13:22 +00:00
parent 4ce7dc1561
commit c7e628df2e
22 changed files with 11391 additions and 3652 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
sim/sh64/ChangeLog
View File

@ -1,3 +1,43 @@
2006-10-18 Dave Brolley <brolley@redhat.com>
* Contribute the following changes:
2006-06-14 Dave Brolley <brolley@redhat.com>
* sh64-sim.h (sh64_fipr,sh64_fiprs,sh64_fldp,sh64_fstp,sh64_ftrv)
(sh64_fpref): New functions.
* sh64.c (sh64_fipr,sh64_fiprs,sh64_fldp,sh64_fstp,sh64_ftrv)
(sh64_fpref): New functions.
(sh_models): Add sh2e, sh2a, sh2a_nofpu, sh4_nofpu, sh4a,
sh4a_nofpu and sh4al.
(sh2e_mach): New MACH.
(sh2a_fpu_mach): New MACH.
(sh2a_nofpu_mach): New MACH.
(sh4_nofpu): New MACH.
(sh4a_mach): New MACH.
(sh4a_nofpu_mach): New MACH.
(sh4al_mach): New MACH.
* Makefile.in (stamp-*): Depend on $(CGEN_CPU_DIR)/sh-sim.cpu. Pass
archfile to CGEN script.
* arch.c: Regenerated.
* arch.h: Regenerated.
* cpu.c: Regenerated.
* cpu.h: Regenerated.
* cpuall.h: Regenerated.
* decode-compact.c: Regenerated.
* decode-compact.h: Regenerated.
* decode-media.c: Regenerated.
* decode-media.h: Regenerated.
* defs-compact.h: Regenerated.
* defs-media.h: Regenerated.
* sem-compact-switch.c: Regenerated.
* sem-compact.c: Regenerated.
* sem-media-switch.c: Regenerated.
* sem-media.c: Regenerated.
* sh-desc.c: Regenerated.
* sh-desc.h: Regenerated.
* sh-opc.h: Regenerated.
2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
* configure: Regenerated.

36
sim/sh64/Makefile.in
View File

@ -104,50 +104,52 @@ stamp-all: stamp-arch stamp-desc stamp-cpu stamp-decode stamp-defs
stamp-decode: stamp-decode-compact stamp-decode-media
stamp-defs: stamp-defs-compact stamp-defs-media
stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all isa=compact,media \
stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all isa=compact,media archfile=$(CGEN_CPU_DIR)/sh.cpu \
FLAGS="with-scache"
touch $@
arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
arch.h ${srcdir}/arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
@true
stamp-desc: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
$(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) cpu=sh64 mach=all isa=compact,media
stamp-desc: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) cpu=sh64 mach=all isa=compact,media archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
desc.h: $(CGEN_MAINT) stamp-desc
@true
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-cpu $(CGEN_FLAGS_TO_PASS) \
cpu=sh64 mach=sh4,sh5 isa=compact,media FLAGS="with-multiple-isa with-scache"
cpu=sh64 mach=sh4,sh5 isa=compact,media FLAGS="with-multiple-isa with-scache" archfile=$(CGEN_CPU_DIR)/sh.cpu
rm -f $(srcdir)/model.c
touch $@
cpu.h: $(CGEN_MAINT) stamp-cpu
@true
stamp-defs-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
stamp-defs-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact"
cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
defs-compact.h: $(CGEN_MAINT) stamp-defs-compact
@true
stamp-defs-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
stamp-defs-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media"
cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
defs-media.h: $(CGEN_MAINT) stamp-defs-media
stamp-decode-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
stamp-decode-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" \
archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
sem-compact.c sem-compact-switch.c decode-compact.c decode-compact.h: $(CGEN_MAINT) stamp-compact
sem-compact.c sem-compact-switch.c decode-compact.c decode-compact.h: $(CGEN_MAINT) stamp-decode-compact
@true
stamp-decode-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
stamp-decode-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" \
archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
sem-media.c sem-media-switch.c decode-media.c decode-media.h: $(CGEN_MAINT) stamp-media
sem-media.c sem-media-switch.c decode-media.c decode-media.h: $(CGEN_MAINT) stamp-decode-media
@true

27
sim/sh64/arch.c
View File

@ -2,9 +2,9 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -30,15 +30,36 @@ const MACH *sim_machs[] =
#ifdef HAVE_CPU_SH64
& sh2_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh2e_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh2a_fpu_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh2a_nofpu_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh3_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh3e_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh4_nofpu_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh4_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh4a_nofpu_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh4a_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh4al_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh5_mach,
#endif

187
sim/sh64/arch.h
View File

@ -2,9 +2,9 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -29,16 +29,191 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_SH5, MODEL_MAX
MODEL_SH2A_NOFPU, MODEL_SH2A_FPU, MODEL_SH4_NOFPU, MODEL_SH4
, MODEL_SH4A_NOFPU, MODEL_SH4A, MODEL_SH4AL, MODEL_SH5
, MODEL_SH5_MEDIA, MODEL_SH2, MODEL_SH2E, MODEL_SH3
, MODEL_SH3E, MODEL_MAX
} MODEL_TYPE;
#define MAX_MODELS ((int) MODEL_MAX)
/* Enum declaration for unit types. */
typedef enum unit_type {
UNIT_NONE, UNIT_SH5_U_EXEC, UNIT_MAX
UNIT_NONE, UNIT_SH2A_NOFPU_U_MULR_GR, UNIT_SH2A_NOFPU_U_MULR, UNIT_SH2A_NOFPU_U_TRAP
, UNIT_SH2A_NOFPU_U_WRITE_BACK, UNIT_SH2A_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH2A_NOFPU_U_SHIFT, UNIT_SH2A_NOFPU_U_TAS
, UNIT_SH2A_NOFPU_U_MULSW, UNIT_SH2A_NOFPU_U_MULL, UNIT_SH2A_NOFPU_U_DMUL, UNIT_SH2A_NOFPU_U_MACL
, UNIT_SH2A_NOFPU_U_MACW, UNIT_SH2A_NOFPU_U_MULTIPLY, UNIT_SH2A_NOFPU_U_SET_MAC, UNIT_SH2A_NOFPU_U_LOAD_MAC
, UNIT_SH2A_NOFPU_U_LOAD_VBR, UNIT_SH2A_NOFPU_U_LOAD_GBR, UNIT_SH2A_NOFPU_U_USE_GR, UNIT_SH2A_NOFPU_U_LOAD_GR
, UNIT_SH2A_NOFPU_U_STC_VBR, UNIT_SH2A_NOFPU_U_LDCL_VBR, UNIT_SH2A_NOFPU_U_LDCL, UNIT_SH2A_NOFPU_U_USE_TBIT
, UNIT_SH2A_NOFPU_U_LDC_GBR, UNIT_SH2A_NOFPU_U_LDC_SR, UNIT_SH2A_NOFPU_U_SET_SR_BIT, UNIT_SH2A_NOFPU_U_USE_PR
, UNIT_SH2A_NOFPU_U_LOAD_PR, UNIT_SH2A_NOFPU_U_STS_PR, UNIT_SH2A_NOFPU_U_LDS_PR, UNIT_SH2A_NOFPU_U_MEMORY_ACCESS
, UNIT_SH2A_NOFPU_U_LOGIC_B, UNIT_SH2A_NOFPU_U_JSR, UNIT_SH2A_NOFPU_U_JMP, UNIT_SH2A_NOFPU_U_BRANCH
, UNIT_SH2A_NOFPU_U_SX, UNIT_SH2A_NOFPU_U_EXEC, UNIT_SH2A_FPU_U_USE_DR, UNIT_SH2A_FPU_U_LOAD_DR
, UNIT_SH2A_FPU_U_SET_DR, UNIT_SH2A_FPU_U_MULR_GR, UNIT_SH2A_FPU_U_MULR, UNIT_SH2A_FPU_U_FCNV
, UNIT_SH2A_FPU_U_FCMP, UNIT_SH2A_FPU_U_FSQRT, UNIT_SH2A_FPU_U_FDIV, UNIT_SH2A_FPU_U_FPU_LOAD_GR
, UNIT_SH2A_FPU_U_USE_FPSCR, UNIT_SH2A_FPU_U_LDSL_FPSCR, UNIT_SH2A_FPU_U_LDS_FPSCR, UNIT_SH2A_FPU_U_USE_FPUL
, UNIT_SH2A_FPU_U_FLDS_FPUL, UNIT_SH2A_FPU_U_LOAD_FPUL, UNIT_SH2A_FPU_U_SET_FPUL, UNIT_SH2A_FPU_U_FPU_MEMORY_ACCESS
, UNIT_SH2A_FPU_U_USE_FR, UNIT_SH2A_FPU_U_SET_FR_0, UNIT_SH2A_FPU_U_SET_FR, UNIT_SH2A_FPU_U_LOAD_FR
, UNIT_SH2A_FPU_U_MAYBE_FPU, UNIT_SH2A_FPU_U_FPU, UNIT_SH2A_FPU_U_TRAP, UNIT_SH2A_FPU_U_WRITE_BACK
, UNIT_SH2A_FPU_U_USE_MULTIPLY_RESULT, UNIT_SH2A_FPU_U_SHIFT, UNIT_SH2A_FPU_U_TAS, UNIT_SH2A_FPU_U_MULSW
, UNIT_SH2A_FPU_U_MULL, UNIT_SH2A_FPU_U_DMUL, UNIT_SH2A_FPU_U_MACL, UNIT_SH2A_FPU_U_MACW
, UNIT_SH2A_FPU_U_MULTIPLY, UNIT_SH2A_FPU_U_SET_MAC, UNIT_SH2A_FPU_U_LOAD_MAC, UNIT_SH2A_FPU_U_LOAD_VBR
, UNIT_SH2A_FPU_U_LOAD_GBR, UNIT_SH2A_FPU_U_USE_GR, UNIT_SH2A_FPU_U_LOAD_GR, UNIT_SH2A_FPU_U_STC_VBR
, UNIT_SH2A_FPU_U_LDCL_VBR, UNIT_SH2A_FPU_U_LDCL, UNIT_SH2A_FPU_U_USE_TBIT, UNIT_SH2A_FPU_U_LDC_GBR
, UNIT_SH2A_FPU_U_LDC_SR, UNIT_SH2A_FPU_U_SET_SR_BIT, UNIT_SH2A_FPU_U_USE_PR, UNIT_SH2A_FPU_U_LOAD_PR
, UNIT_SH2A_FPU_U_STS_PR, UNIT_SH2A_FPU_U_LDS_PR, UNIT_SH2A_FPU_U_MEMORY_ACCESS, UNIT_SH2A_FPU_U_LOGIC_B
, UNIT_SH2A_FPU_U_JSR, UNIT_SH2A_FPU_U_JMP, UNIT_SH2A_FPU_U_BRANCH, UNIT_SH2A_FPU_U_SX
, UNIT_SH2A_FPU_U_EXEC, UNIT_SH4_NOFPU_U_OCB, UNIT_SH4_NOFPU_U_MULR_GR, UNIT_SH4_NOFPU_U_MULR
, UNIT_SH4_NOFPU_U_TRAP, UNIT_SH4_NOFPU_U_WRITE_BACK, UNIT_SH4_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH4_NOFPU_U_SHIFT
, UNIT_SH4_NOFPU_U_TAS, UNIT_SH4_NOFPU_U_MULSW, UNIT_SH4_NOFPU_U_MULL, UNIT_SH4_NOFPU_U_DMUL
, UNIT_SH4_NOFPU_U_MACL, UNIT_SH4_NOFPU_U_MACW, UNIT_SH4_NOFPU_U_MULTIPLY, UNIT_SH4_NOFPU_U_SET_MAC
, UNIT_SH4_NOFPU_U_LOAD_MAC, UNIT_SH4_NOFPU_U_LOAD_VBR, UNIT_SH4_NOFPU_U_LOAD_GBR, UNIT_SH4_NOFPU_U_USE_GR
, UNIT_SH4_NOFPU_U_LOAD_GR, UNIT_SH4_NOFPU_U_STC_VBR, UNIT_SH4_NOFPU_U_LDCL_VBR, UNIT_SH4_NOFPU_U_LDCL
, UNIT_SH4_NOFPU_U_USE_TBIT, UNIT_SH4_NOFPU_U_LDC_GBR, UNIT_SH4_NOFPU_U_LDC_SR, UNIT_SH4_NOFPU_U_SET_SR_BIT
, UNIT_SH4_NOFPU_U_USE_PR, UNIT_SH4_NOFPU_U_LOAD_PR, UNIT_SH4_NOFPU_U_STS_PR, UNIT_SH4_NOFPU_U_LDS_PR
, UNIT_SH4_NOFPU_U_MEMORY_ACCESS, UNIT_SH4_NOFPU_U_LOGIC_B, UNIT_SH4_NOFPU_U_JSR, UNIT_SH4_NOFPU_U_JMP
, UNIT_SH4_NOFPU_U_BRANCH, UNIT_SH4_NOFPU_U_SX, UNIT_SH4_NOFPU_U_EXEC, UNIT_SH4_U_FTRV
, UNIT_SH4_U_FIPR, UNIT_SH4_U_OCB, UNIT_SH4_U_MULR_GR, UNIT_SH4_U_MULR
, UNIT_SH4_U_USE_DR, UNIT_SH4_U_LOAD_DR, UNIT_SH4_U_SET_DR, UNIT_SH4_U_FCNV
, UNIT_SH4_U_FCMP, UNIT_SH4_U_FSQRT, UNIT_SH4_U_FDIV, UNIT_SH4_U_FPU_LOAD_GR
, UNIT_SH4_U_USE_FPSCR, UNIT_SH4_U_LDSL_FPSCR, UNIT_SH4_U_LDS_FPSCR, UNIT_SH4_U_USE_FPUL
, UNIT_SH4_U_FLDS_FPUL, UNIT_SH4_U_LOAD_FPUL, UNIT_SH4_U_SET_FPUL, UNIT_SH4_U_FPU_MEMORY_ACCESS
, UNIT_SH4_U_USE_FR, UNIT_SH4_U_SET_FR_0, UNIT_SH4_U_SET_FR, UNIT_SH4_U_LOAD_FR
, UNIT_SH4_U_MAYBE_FPU, UNIT_SH4_U_FPU, UNIT_SH4_U_TRAP, UNIT_SH4_U_WRITE_BACK
, UNIT_SH4_U_USE_MULTIPLY_RESULT, UNIT_SH4_U_SHIFT, UNIT_SH4_U_TAS, UNIT_SH4_U_MULSW
, UNIT_SH4_U_MULL, UNIT_SH4_U_DMUL, UNIT_SH4_U_MACL, UNIT_SH4_U_MACW
, UNIT_SH4_U_MULTIPLY, UNIT_SH4_U_SET_MAC, UNIT_SH4_U_LOAD_MAC, UNIT_SH4_U_LOAD_VBR
, UNIT_SH4_U_LOAD_GBR, UNIT_SH4_U_USE_GR, UNIT_SH4_U_LOAD_GR, UNIT_SH4_U_STC_VBR
, UNIT_SH4_U_LDCL_VBR, UNIT_SH4_U_LDCL, UNIT_SH4_U_USE_TBIT, UNIT_SH4_U_LDC_GBR
, UNIT_SH4_U_LDC_SR, UNIT_SH4_U_SET_SR_BIT, UNIT_SH4_U_USE_PR, UNIT_SH4_U_LOAD_PR
, UNIT_SH4_U_STS_PR, UNIT_SH4_U_LDS_PR, UNIT_SH4_U_MEMORY_ACCESS, UNIT_SH4_U_LOGIC_B
, UNIT_SH4_U_JSR, UNIT_SH4_U_JMP, UNIT_SH4_U_BRANCH, UNIT_SH4_U_SX
, UNIT_SH4_U_EXEC, UNIT_SH4A_NOFPU_U_OCB, UNIT_SH4A_NOFPU_U_MULR_GR, UNIT_SH4A_NOFPU_U_MULR
, UNIT_SH4A_NOFPU_U_FCNV, UNIT_SH4A_NOFPU_U_FCMP, UNIT_SH4A_NOFPU_U_FSQRT, UNIT_SH4A_NOFPU_U_FDIV
, UNIT_SH4A_NOFPU_U_FPU_LOAD_GR, UNIT_SH4A_NOFPU_U_USE_FPSCR, UNIT_SH4A_NOFPU_U_LDSL_FPSCR, UNIT_SH4A_NOFPU_U_LDS_FPSCR
, UNIT_SH4A_NOFPU_U_USE_FPUL, UNIT_SH4A_NOFPU_U_FLDS_FPUL, UNIT_SH4A_NOFPU_U_LOAD_FPUL, UNIT_SH4A_NOFPU_U_SET_FPUL
, UNIT_SH4A_NOFPU_U_FPU_MEMORY_ACCESS, UNIT_SH4A_NOFPU_U_USE_FR, UNIT_SH4A_NOFPU_U_SET_FR_0, UNIT_SH4A_NOFPU_U_SET_FR
, UNIT_SH4A_NOFPU_U_LOAD_FR, UNIT_SH4A_NOFPU_U_MAYBE_FPU, UNIT_SH4A_NOFPU_U_FPU, UNIT_SH4A_NOFPU_U_TRAP
, UNIT_SH4A_NOFPU_U_WRITE_BACK, UNIT_SH4A_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH4A_NOFPU_U_SHIFT, UNIT_SH4A_NOFPU_U_TAS
, UNIT_SH4A_NOFPU_U_MULSW, UNIT_SH4A_NOFPU_U_MULL, UNIT_SH4A_NOFPU_U_DMUL, UNIT_SH4A_NOFPU_U_MACL
, UNIT_SH4A_NOFPU_U_MACW, UNIT_SH4A_NOFPU_U_MULTIPLY, UNIT_SH4A_NOFPU_U_SET_MAC, UNIT_SH4A_NOFPU_U_LOAD_MAC
, UNIT_SH4A_NOFPU_U_LOAD_VBR, UNIT_SH4A_NOFPU_U_LOAD_GBR, UNIT_SH4A_NOFPU_U_USE_GR, UNIT_SH4A_NOFPU_U_LOAD_GR
, UNIT_SH4A_NOFPU_U_STC_VBR, UNIT_SH4A_NOFPU_U_LDCL_VBR, UNIT_SH4A_NOFPU_U_LDCL, UNIT_SH4A_NOFPU_U_USE_TBIT
, UNIT_SH4A_NOFPU_U_LDC_GBR, UNIT_SH4A_NOFPU_U_LDC_SR, UNIT_SH4A_NOFPU_U_SET_SR_BIT, UNIT_SH4A_NOFPU_U_USE_PR
, UNIT_SH4A_NOFPU_U_LOAD_PR, UNIT_SH4A_NOFPU_U_STS_PR, UNIT_SH4A_NOFPU_U_LDS_PR, UNIT_SH4A_NOFPU_U_MEMORY_ACCESS
, UNIT_SH4A_NOFPU_U_LOGIC_B, UNIT_SH4A_NOFPU_U_JSR, UNIT_SH4A_NOFPU_U_JMP, UNIT_SH4A_NOFPU_U_BRANCH
, UNIT_SH4A_NOFPU_U_SX, UNIT_SH4A_NOFPU_U_EXEC, UNIT_SH4A_U_FTRV, UNIT_SH4A_U_FIPR
, UNIT_SH4A_U_OCB, UNIT_SH4A_U_MULR_GR, UNIT_SH4A_U_MULR, UNIT_SH4A_U_FCNV
, UNIT_SH4A_U_FCMP, UNIT_SH4A_U_FSQRT, UNIT_SH4A_U_FDIV, UNIT_SH4A_U_FPU_LOAD_GR
, UNIT_SH4A_U_USE_FPSCR, UNIT_SH4A_U_LDSL_FPSCR, UNIT_SH4A_U_LDS_FPSCR, UNIT_SH4A_U_USE_FPUL
, UNIT_SH4A_U_FLDS_FPUL, UNIT_SH4A_U_LOAD_FPUL, UNIT_SH4A_U_SET_FPUL, UNIT_SH4A_U_FPU_MEMORY_ACCESS
, UNIT_SH4A_U_USE_FR, UNIT_SH4A_U_SET_FR_0, UNIT_SH4A_U_SET_FR, UNIT_SH4A_U_LOAD_FR
, UNIT_SH4A_U_MAYBE_FPU, UNIT_SH4A_U_FPU, UNIT_SH4A_U_TRAP, UNIT_SH4A_U_WRITE_BACK
, UNIT_SH4A_U_USE_MULTIPLY_RESULT, UNIT_SH4A_U_SHIFT, UNIT_SH4A_U_TAS, UNIT_SH4A_U_MULSW
, UNIT_SH4A_U_MULL, UNIT_SH4A_U_DMUL, UNIT_SH4A_U_MACL, UNIT_SH4A_U_MACW
, UNIT_SH4A_U_MULTIPLY, UNIT_SH4A_U_SET_MAC, UNIT_SH4A_U_LOAD_MAC, UNIT_SH4A_U_LOAD_VBR
, UNIT_SH4A_U_LOAD_GBR, UNIT_SH4A_U_USE_GR, UNIT_SH4A_U_LOAD_GR, UNIT_SH4A_U_STC_VBR
, UNIT_SH4A_U_LDCL_VBR, UNIT_SH4A_U_LDCL, UNIT_SH4A_U_USE_TBIT, UNIT_SH4A_U_LDC_GBR
, UNIT_SH4A_U_LDC_SR, UNIT_SH4A_U_SET_SR_BIT, UNIT_SH4A_U_USE_PR, UNIT_SH4A_U_LOAD_PR
, UNIT_SH4A_U_STS_PR, UNIT_SH4A_U_LDS_PR, UNIT_SH4A_U_MEMORY_ACCESS, UNIT_SH4A_U_LOGIC_B
, UNIT_SH4A_U_JSR, UNIT_SH4A_U_JMP, UNIT_SH4A_U_BRANCH, UNIT_SH4A_U_SX
, UNIT_SH4A_U_EXEC, UNIT_SH4AL_U_OCB, UNIT_SH4AL_U_MULR_GR, UNIT_SH4AL_U_MULR
, UNIT_SH4AL_U_FCNV, UNIT_SH4AL_U_FCMP, UNIT_SH4AL_U_FSQRT, UNIT_SH4AL_U_FDIV
, UNIT_SH4AL_U_FPU_LOAD_GR, UNIT_SH4AL_U_USE_FPSCR, UNIT_SH4AL_U_LDSL_FPSCR, UNIT_SH4AL_U_LDS_FPSCR
, UNIT_SH4AL_U_USE_FPUL, UNIT_SH4AL_U_FLDS_FPUL, UNIT_SH4AL_U_LOAD_FPUL, UNIT_SH4AL_U_SET_FPUL
, UNIT_SH4AL_U_FPU_MEMORY_ACCESS, UNIT_SH4AL_U_USE_FR, UNIT_SH4AL_U_SET_FR_0, UNIT_SH4AL_U_SET_FR
, UNIT_SH4AL_U_LOAD_FR, UNIT_SH4AL_U_MAYBE_FPU, UNIT_SH4AL_U_FPU, UNIT_SH4AL_U_TRAP
, UNIT_SH4AL_U_WRITE_BACK, UNIT_SH4AL_U_USE_MULTIPLY_RESULT, UNIT_SH4AL_U_SHIFT, UNIT_SH4AL_U_TAS
, UNIT_SH4AL_U_MULSW, UNIT_SH4AL_U_MULL, UNIT_SH4AL_U_DMUL, UNIT_SH4AL_U_MACL
, UNIT_SH4AL_U_MACW, UNIT_SH4AL_U_MULTIPLY, UNIT_SH4AL_U_SET_MAC, UNIT_SH4AL_U_LOAD_MAC
, UNIT_SH4AL_U_LOAD_VBR, UNIT_SH4AL_U_LOAD_GBR, UNIT_SH4AL_U_USE_GR, UNIT_SH4AL_U_LOAD_GR
, UNIT_SH4AL_U_STC_VBR, UNIT_SH4AL_U_LDCL_VBR, UNIT_SH4AL_U_LDCL, UNIT_SH4AL_U_USE_TBIT
, UNIT_SH4AL_U_LDC_GBR, UNIT_SH4AL_U_LDC_SR, UNIT_SH4AL_U_SET_SR_BIT, UNIT_SH4AL_U_USE_PR
, UNIT_SH4AL_U_LOAD_PR, UNIT_SH4AL_U_STS_PR, UNIT_SH4AL_U_LDS_PR, UNIT_SH4AL_U_MEMORY_ACCESS
, UNIT_SH4AL_U_LOGIC_B, UNIT_SH4AL_U_JSR, UNIT_SH4AL_U_JMP, UNIT_SH4AL_U_BRANCH
, UNIT_SH4AL_U_SX, UNIT_SH4AL_U_EXEC, UNIT_SH5_U_FTRV, UNIT_SH5_U_FIPR
, UNIT_SH5_U_OCB, UNIT_SH5_U_MULR_GR, UNIT_SH5_U_MULR, UNIT_SH5_U_USE_DR
, UNIT_SH5_U_LOAD_DR, UNIT_SH5_U_SET_DR, UNIT_SH5_U_FCNV, UNIT_SH5_U_FCMP
, UNIT_SH5_U_FSQRT, UNIT_SH5_U_FDIV, UNIT_SH5_U_FPU_LOAD_GR, UNIT_SH5_U_USE_FPSCR
, UNIT_SH5_U_LDSL_FPSCR, UNIT_SH5_U_LDS_FPSCR, UNIT_SH5_U_USE_FPUL, UNIT_SH5_U_FLDS_FPUL
, UNIT_SH5_U_LOAD_FPUL, UNIT_SH5_U_SET_FPUL, UNIT_SH5_U_FPU_MEMORY_ACCESS, UNIT_SH5_U_USE_FR
, UNIT_SH5_U_SET_FR_0, UNIT_SH5_U_SET_FR, UNIT_SH5_U_LOAD_FR, UNIT_SH5_U_MAYBE_FPU
, UNIT_SH5_U_FPU, UNIT_SH5_U_TRAP, UNIT_SH5_U_WRITE_BACK, UNIT_SH5_U_USE_MULTIPLY_RESULT
, UNIT_SH5_U_SHIFT, UNIT_SH5_U_TAS, UNIT_SH5_U_MULSW, UNIT_SH5_U_MULL
, UNIT_SH5_U_DMUL, UNIT_SH5_U_MACL, UNIT_SH5_U_MACW, UNIT_SH5_U_MULTIPLY
, UNIT_SH5_U_SET_MAC, UNIT_SH5_U_LOAD_MAC, UNIT_SH5_U_LOAD_VBR, UNIT_SH5_U_LOAD_GBR
, UNIT_SH5_U_USE_GR, UNIT_SH5_U_LOAD_GR, UNIT_SH5_U_STC_VBR, UNIT_SH5_U_LDCL_VBR
, UNIT_SH5_U_LDCL, UNIT_SH5_U_USE_TBIT, UNIT_SH5_U_LDC_GBR, UNIT_SH5_U_LDC_SR
, UNIT_SH5_U_SET_SR_BIT, UNIT_SH5_U_USE_PR, UNIT_SH5_U_LOAD_PR, UNIT_SH5_U_STS_PR
, UNIT_SH5_U_LDS_PR, UNIT_SH5_U_MEMORY_ACCESS, UNIT_SH5_U_LOGIC_B, UNIT_SH5_U_JSR
, UNIT_SH5_U_JMP, UNIT_SH5_U_BRANCH, UNIT_SH5_U_SX, UNIT_SH5_U_EXEC
, UNIT_SH5_MEDIA_U_PUTCFG, UNIT_SH5_MEDIA_U_GETCFG, UNIT_SH5_MEDIA_U_PT, UNIT_SH5_MEDIA_U_FTRVS
, UNIT_SH5_MEDIA_U_FSQRTD, UNIT_SH5_MEDIA_U_FDIVD, UNIT_SH5_MEDIA_U_COND_BRANCH, UNIT_SH5_MEDIA_U_BLINK
, UNIT_SH5_MEDIA_U_USE_TR, UNIT_SH5_MEDIA_U_USE_MTRX, UNIT_SH5_MEDIA_U_USE_FV, UNIT_SH5_MEDIA_U_USE_FP
, UNIT_SH5_MEDIA_U_LOAD_MTRX, UNIT_SH5_MEDIA_U_LOAD_FV, UNIT_SH5_MEDIA_U_LOAD_FP, UNIT_SH5_MEDIA_U_SET_MTRX
, UNIT_SH5_MEDIA_U_SET_FV, UNIT_SH5_MEDIA_U_SET_FP, UNIT_SH5_MEDIA_U_SET_GR, UNIT_SH5_MEDIA_U_FTRV
, UNIT_SH5_MEDIA_U_FIPR, UNIT_SH5_MEDIA_U_OCB, UNIT_SH5_MEDIA_U_MULR_GR, UNIT_SH5_MEDIA_U_MULR
, UNIT_SH5_MEDIA_U_USE_DR, UNIT_SH5_MEDIA_U_LOAD_DR, UNIT_SH5_MEDIA_U_SET_DR, UNIT_SH5_MEDIA_U_FCNV
, UNIT_SH5_MEDIA_U_FCMP, UNIT_SH5_MEDIA_U_FSQRT, UNIT_SH5_MEDIA_U_FDIV, UNIT_SH5_MEDIA_U_FPU_LOAD_GR
, UNIT_SH5_MEDIA_U_USE_FPSCR, UNIT_SH5_MEDIA_U_LDSL_FPSCR, UNIT_SH5_MEDIA_U_LDS_FPSCR, UNIT_SH5_MEDIA_U_USE_FPUL
, UNIT_SH5_MEDIA_U_FLDS_FPUL, UNIT_SH5_MEDIA_U_LOAD_FPUL, UNIT_SH5_MEDIA_U_SET_FPUL, UNIT_SH5_MEDIA_U_FPU_MEMORY_ACCESS
, UNIT_SH5_MEDIA_U_USE_FR, UNIT_SH5_MEDIA_U_SET_FR_0, UNIT_SH5_MEDIA_U_SET_FR, UNIT_SH5_MEDIA_U_LOAD_FR
, UNIT_SH5_MEDIA_U_MAYBE_FPU, UNIT_SH5_MEDIA_U_FPU, UNIT_SH5_MEDIA_U_TRAP, UNIT_SH5_MEDIA_U_WRITE_BACK
, UNIT_SH5_MEDIA_U_USE_MULTIPLY_RESULT, UNIT_SH5_MEDIA_U_SHIFT, UNIT_SH5_MEDIA_U_TAS, UNIT_SH5_MEDIA_U_MULSW
, UNIT_SH5_MEDIA_U_MULL, UNIT_SH5_MEDIA_U_DMUL, UNIT_SH5_MEDIA_U_MACL, UNIT_SH5_MEDIA_U_MACW
, UNIT_SH5_MEDIA_U_MULTIPLY, UNIT_SH5_MEDIA_U_SET_MAC, UNIT_SH5_MEDIA_U_LOAD_MAC, UNIT_SH5_MEDIA_U_LOAD_VBR
, UNIT_SH5_MEDIA_U_LOAD_GBR, UNIT_SH5_MEDIA_U_USE_GR, UNIT_SH5_MEDIA_U_LOAD_GR, UNIT_SH5_MEDIA_U_STC_VBR
, UNIT_SH5_MEDIA_U_LDCL_VBR, UNIT_SH5_MEDIA_U_LDCL, UNIT_SH5_MEDIA_U_USE_TBIT, UNIT_SH5_MEDIA_U_LDC_GBR
, UNIT_SH5_MEDIA_U_LDC_SR, UNIT_SH5_MEDIA_U_SET_SR_BIT, UNIT_SH5_MEDIA_U_USE_PR, UNIT_SH5_MEDIA_U_LOAD_PR
, UNIT_SH5_MEDIA_U_STS_PR, UNIT_SH5_MEDIA_U_LDS_PR, UNIT_SH5_MEDIA_U_MEMORY_ACCESS, UNIT_SH5_MEDIA_U_LOGIC_B
, UNIT_SH5_MEDIA_U_JSR, UNIT_SH5_MEDIA_U_JMP, UNIT_SH5_MEDIA_U_BRANCH, UNIT_SH5_MEDIA_U_SX
, UNIT_SH5_MEDIA_U_EXEC, UNIT_SH2_U_TRAP, UNIT_SH2_U_WRITE_BACK, UNIT_SH2_U_USE_MULTIPLY_RESULT
, UNIT_SH2_U_SHIFT, UNIT_SH2_U_TAS, UNIT_SH2_U_MULSW, UNIT_SH2_U_MULL
, UNIT_SH2_U_DMUL, UNIT_SH2_U_MACL, UNIT_SH2_U_MACW, UNIT_SH2_U_MULTIPLY
, UNIT_SH2_U_SET_MAC, UNIT_SH2_U_LOAD_MAC, UNIT_SH2_U_LOAD_VBR, UNIT_SH2_U_LOAD_GBR
, UNIT_SH2_U_USE_GR, UNIT_SH2_U_LOAD_GR, UNIT_SH2_U_STC_VBR, UNIT_SH2_U_LDCL_VBR
, UNIT_SH2_U_LDCL, UNIT_SH2_U_USE_TBIT, UNIT_SH2_U_LDC_GBR, UNIT_SH2_U_LDC_SR
, UNIT_SH2_U_SET_SR_BIT, UNIT_SH2_U_USE_PR, UNIT_SH2_U_LOAD_PR, UNIT_SH2_U_STS_PR
, UNIT_SH2_U_LDS_PR, UNIT_SH2_U_MEMORY_ACCESS, UNIT_SH2_U_LOGIC_B, UNIT_SH2_U_JSR
, UNIT_SH2_U_JMP, UNIT_SH2_U_BRANCH, UNIT_SH2_U_SX, UNIT_SH2_U_EXEC
, UNIT_SH2E_U_FCNV, UNIT_SH2E_U_FCMP, UNIT_SH2E_U_FSQRT, UNIT_SH2E_U_FDIV
, UNIT_SH2E_U_FPU_LOAD_GR, UNIT_SH2E_U_USE_FPSCR, UNIT_SH2E_U_LDSL_FPSCR, UNIT_SH2E_U_LDS_FPSCR
, UNIT_SH2E_U_USE_FPUL, UNIT_SH2E_U_FLDS_FPUL, UNIT_SH2E_U_LOAD_FPUL, UNIT_SH2E_U_SET_FPUL
, UNIT_SH2E_U_FPU_MEMORY_ACCESS, UNIT_SH2E_U_USE_FR, UNIT_SH2E_U_SET_FR_0, UNIT_SH2E_U_SET_FR
, UNIT_SH2E_U_LOAD_FR, UNIT_SH2E_U_MAYBE_FPU, UNIT_SH2E_U_FPU, UNIT_SH2E_U_TRAP
, UNIT_SH2E_U_WRITE_BACK, UNIT_SH2E_U_USE_MULTIPLY_RESULT, UNIT_SH2E_U_SHIFT, UNIT_SH2E_U_TAS
, UNIT_SH2E_U_MULSW, UNIT_SH2E_U_MULL, UNIT_SH2E_U_DMUL, UNIT_SH2E_U_MACL
, UNIT_SH2E_U_MACW, UNIT_SH2E_U_MULTIPLY, UNIT_SH2E_U_SET_MAC, UNIT_SH2E_U_LOAD_MAC
, UNIT_SH2E_U_LOAD_VBR, UNIT_SH2E_U_LOAD_GBR, UNIT_SH2E_U_USE_GR, UNIT_SH2E_U_LOAD_GR
, UNIT_SH2E_U_STC_VBR, UNIT_SH2E_U_LDCL_VBR, UNIT_SH2E_U_LDCL, UNIT_SH2E_U_USE_TBIT
, UNIT_SH2E_U_LDC_GBR, UNIT_SH2E_U_LDC_SR, UNIT_SH2E_U_SET_SR_BIT, UNIT_SH2E_U_USE_PR
, UNIT_SH2E_U_LOAD_PR, UNIT_SH2E_U_STS_PR, UNIT_SH2E_U_LDS_PR, UNIT_SH2E_U_MEMORY_ACCESS
, UNIT_SH2E_U_LOGIC_B, UNIT_SH2E_U_JSR, UNIT_SH2E_U_JMP, UNIT_SH2E_U_BRANCH
, UNIT_SH2E_U_SX, UNIT_SH2E_U_EXEC, UNIT_SH3_U_TRAP, UNIT_SH3_U_WRITE_BACK
, UNIT_SH3_U_USE_MULTIPLY_RESULT, UNIT_SH3_U_SHIFT, UNIT_SH3_U_TAS, UNIT_SH3_U_MULSW
, UNIT_SH3_U_MULL, UNIT_SH3_U_DMUL, UNIT_SH3_U_MACL, UNIT_SH3_U_MACW
, UNIT_SH3_U_MULTIPLY, UNIT_SH3_U_SET_MAC, UNIT_SH3_U_LOAD_MAC, UNIT_SH3_U_LOAD_VBR
, UNIT_SH3_U_LOAD_GBR, UNIT_SH3_U_USE_GR, UNIT_SH3_U_LOAD_GR, UNIT_SH3_U_STC_VBR
, UNIT_SH3_U_LDCL_VBR, UNIT_SH3_U_LDCL, UNIT_SH3_U_USE_TBIT, UNIT_SH3_U_LDC_GBR
, UNIT_SH3_U_LDC_SR, UNIT_SH3_U_SET_SR_BIT, UNIT_SH3_U_USE_PR, UNIT_SH3_U_LOAD_PR
, UNIT_SH3_U_STS_PR, UNIT_SH3_U_LDS_PR, UNIT_SH3_U_MEMORY_ACCESS, UNIT_SH3_U_LOGIC_B
, UNIT_SH3_U_JSR, UNIT_SH3_U_JMP, UNIT_SH3_U_BRANCH, UNIT_SH3_U_SX
, UNIT_SH3_U_EXEC, UNIT_SH3E_U_FCNV, UNIT_SH3E_U_FCMP, UNIT_SH3E_U_FSQRT
, UNIT_SH3E_U_FDIV, UNIT_SH3E_U_FPU_LOAD_GR, UNIT_SH3E_U_USE_FPSCR, UNIT_SH3E_U_LDSL_FPSCR
, UNIT_SH3E_U_LDS_FPSCR, UNIT_SH3E_U_USE_FPUL, UNIT_SH3E_U_FLDS_FPUL, UNIT_SH3E_U_LOAD_FPUL
, UNIT_SH3E_U_SET_FPUL, UNIT_SH3E_U_FPU_MEMORY_ACCESS, UNIT_SH3E_U_USE_FR, UNIT_SH3E_U_SET_FR_0
, UNIT_SH3E_U_SET_FR, UNIT_SH3E_U_LOAD_FR, UNIT_SH3E_U_MAYBE_FPU, UNIT_SH3E_U_FPU
, UNIT_SH3E_U_TRAP, UNIT_SH3E_U_WRITE_BACK, UNIT_SH3E_U_USE_MULTIPLY_RESULT, UNIT_SH3E_U_SHIFT
, UNIT_SH3E_U_TAS, UNIT_SH3E_U_MULSW, UNIT_SH3E_U_MULL, UNIT_SH3E_U_DMUL
, UNIT_SH3E_U_MACL, UNIT_SH3E_U_MACW, UNIT_SH3E_U_MULTIPLY, UNIT_SH3E_U_SET_MAC
, UNIT_SH3E_U_LOAD_MAC, UNIT_SH3E_U_LOAD_VBR, UNIT_SH3E_U_LOAD_GBR, UNIT_SH3E_U_USE_GR
, UNIT_SH3E_U_LOAD_GR, UNIT_SH3E_U_STC_VBR, UNIT_SH3E_U_LDCL_VBR, UNIT_SH3E_U_LDCL
, UNIT_SH3E_U_USE_TBIT, UNIT_SH3E_U_LDC_GBR, UNIT_SH3E_U_LDC_SR, UNIT_SH3E_U_SET_SR_BIT
, UNIT_SH3E_U_USE_PR, UNIT_SH3E_U_LOAD_PR, UNIT_SH3E_U_STS_PR, UNIT_SH3E_U_LDS_PR
, UNIT_SH3E_U_MEMORY_ACCESS, UNIT_SH3E_U_LOGIC_B, UNIT_SH3E_U_JSR, UNIT_SH3E_U_JMP
, UNIT_SH3E_U_BRANCH, UNIT_SH3E_U_SX, UNIT_SH3E_U_EXEC, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (1)
#define MAX_UNITS (9)
#endif /* SH_ARCH_H */

78
sim/sh64/cpu.c
View File

@ -2,9 +2,9 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -238,18 +238,18 @@ sh64_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
/* Get the value of h-fp. */
DF
SF
sh64_h_fp_get (SIM_CPU *current_cpu, UINT regno)
{
return CPU (h_fp[regno]);
return GET_H_FP (regno);
}
/* Set a value for h-fp. */
void
sh64_h_fp_set (SIM_CPU *current_cpu, UINT regno, DF newval)
sh64_h_fp_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
CPU (h_fp[regno]) = newval;
SET_H_FP (regno, newval);
}
/* Get the value of h-fv. */
@ -300,6 +300,38 @@ sh64_h_dr_set (SIM_CPU *current_cpu, UINT regno, DF newval)
SET_H_DR (regno, newval);
}
/* Get the value of h-fsd. */
DF
sh64_h_fsd_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FSD (regno);
}
/* Set a value for h-fsd. */
void
sh64_h_fsd_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
SET_H_FSD (regno, newval);
}
/* Get the value of h-fmov. */
DF
sh64_h_fmov_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FMOV (regno);
}
/* Set a value for h-fmov. */
void
sh64_h_fmov_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
SET_H_FMOV (regno, newval);
}
/* Get the value of h-tr. */
DI
@ -428,22 +460,6 @@ sh64_h_fvc_set (SIM_CPU *current_cpu, UINT regno, SF newval)
SET_H_FVC (regno, newval);
}
/* Get the value of h-fpccr. */
SI
sh64_h_fpccr_get (SIM_CPU *current_cpu)
{
return GET_H_FPCCR ();
}
/* Set a value for h-fpccr. */
void
sh64_h_fpccr_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_FPCCR (newval);
}
/* Get the value of h-gbr. */
SI
@ -460,6 +476,22 @@ sh64_h_gbr_set (SIM_CPU *current_cpu, SI newval)
SET_H_GBR (newval);
}
/* Get the value of h-vbr. */
SI
sh64_h_vbr_get (SIM_CPU *current_cpu)
{
return GET_H_VBR ();
}
/* Set a value for h-vbr. */
void
sh64_h_vbr_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_VBR (newval);
}
/* Get the value of h-pr. */
SI

96
sim/sh64/cpu.h
View File

@ -2,9 +2,9 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -80,10 +80,32 @@ CPU (h_cr[(index)]) = (x);\
SF h_fr[64];
#define GET_H_FR(a1) CPU (h_fr)[a1]
#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
/* Single precision floating point register pairs */
DF h_fp[32];
#define GET_H_FP(a1) CPU (h_fp)[a1]
#define SET_H_FP(a1, x) (CPU (h_fp)[a1] = (x))
/* Single/Double precision floating point registers */
DF h_fsd[16];
#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), CPU (h_fr[index]))))
#define SET_H_FSD(index, x) \
do { \
if (GET_H_PRBIT ()) {\
SET_H_DRC ((index), (x));\
} else {\
SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\
}\
;} while (0)
/* floating point registers for fmov */
DF h_fmov[16];
#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index)))))
#define SET_H_FMOV(index, x) \
do { \
if (NOTBI (GET_H_SZBIT ())) {\
SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\
} else {\
if ((((((index)) & (1))) == (1))) {\
SET_H_XD ((((index)) & ((~ (1)))), (x));\
} else {\
SET_H_DR ((index), (x));\
}\
}\
;} while (0)
/* Branch target registers */
DI h_tr[8];
#define GET_H_TR(a1) CPU (h_tr)[a1]
@ -106,20 +128,20 @@ cgen_rtx_error (current_cpu, "cannot set ism directly");\
do { \
CPU (h_gr[(index)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_sr), 14), 1)
#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1)
#define SET_H_FRBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (14))))), SLLSI ((x), 14));\
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\
;} while (0)
#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_sr), 13), 1)
#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1)
#define SET_H_SZBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (13))))), SLLSI ((x), 13));\
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\
;} while (0)
#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_sr), 12), 1)
#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1)
#define SET_H_PRBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (12))))), SLLSI ((x), 12));\
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\
;} while (0)
#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
#define SET_H_SBIT(x) \
@ -136,15 +158,20 @@ CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
;} while (0)
#define GET_H_FV(index) CPU (h_fr[MULQI (ANDQI (index, 15), 4)])
#define GET_H_FP(index) CPU (h_fr[index])
#define SET_H_FP(index, x) \
do { \
CPU (h_fr[(index)]) = (x);\
;} while (0)
#define GET_H_FV(index) CPU (h_fr[index])
#define SET_H_FV(index, x) \
do { \
CPU (h_fr[MULQI (ANDQI ((index), 15), 4)]) = (x);\
CPU (h_fr[(index)]) = (x);\
;} while (0)
#define GET_H_FMTX(index) CPU (h_fr[MULQI (ANDQI (index, 3), 16)])
#define GET_H_FMTX(index) CPU (h_fr[index])
#define SET_H_FMTX(index, x) \
do { \
CPU (h_fr[MULQI (ANDQI ((index), 3), 16)]) = (x);\
CPU (h_fr[(index)]) = (x);\
;} while (0)
#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
#define SET_H_DR(index, x) \
@ -184,21 +211,16 @@ SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
do { \
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
;} while (0)
#define GET_H_FPCCR() ORSI (ORSI (ORSI (CPU (h_fpscr), SLLSI (GET_H_PRBIT (), 19)), SLLSI (GET_H_SZBIT (), 20)), SLLSI (GET_H_FRBIT (), 21))
#define SET_H_FPCCR(x) \
do { \
{\
CPU (h_fpscr) = (x);\
SET_H_PRBIT (ANDSI (SRLSI ((x), 19), 1));\
SET_H_SZBIT (ANDSI (SRLSI ((x), 20), 1));\
SET_H_FRBIT (ANDSI (SRLSI ((x), 21), 1));\
}\
;} while (0)
#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
#define SET_H_GBR(x) \
do { \
CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1)
#define SET_H_VBR(x) \
do { \
CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
#define SET_H_PR(x) \
do { \
@ -247,14 +269,18 @@ BI sh64_h_qbit_get (SIM_CPU *);
void sh64_h_qbit_set (SIM_CPU *, BI);
SF sh64_h_fr_get (SIM_CPU *, UINT);
void sh64_h_fr_set (SIM_CPU *, UINT, SF);
DF sh64_h_fp_get (SIM_CPU *, UINT);
void sh64_h_fp_set (SIM_CPU *, UINT, DF);
SF sh64_h_fp_get (SIM_CPU *, UINT);
void sh64_h_fp_set (SIM_CPU *, UINT, SF);
SF sh64_h_fv_get (SIM_CPU *, UINT);
void sh64_h_fv_set (SIM_CPU *, UINT, SF);
SF sh64_h_fmtx_get (SIM_CPU *, UINT);
void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
DF sh64_h_dr_get (SIM_CPU *, UINT);
void sh64_h_dr_set (SIM_CPU *, UINT, DF);
DF sh64_h_fsd_get (SIM_CPU *, UINT);
void sh64_h_fsd_set (SIM_CPU *, UINT, DF);
DF sh64_h_fmov_get (SIM_CPU *, UINT);
void sh64_h_fmov_set (SIM_CPU *, UINT, DF);
DI sh64_h_tr_get (SIM_CPU *, UINT);
void sh64_h_tr_set (SIM_CPU *, UINT, DI);
BI sh64_h_endian_get (SIM_CPU *);
@ -271,10 +297,10 @@ DF sh64_h_xd_get (SIM_CPU *, UINT);
void sh64_h_xd_set (SIM_CPU *, UINT, DF);
SF sh64_h_fvc_get (SIM_CPU *, UINT);
void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
SI sh64_h_fpccr_get (SIM_CPU *);
void sh64_h_fpccr_set (SIM_CPU *, SI);
SI sh64_h_gbr_get (SIM_CPU *);
void sh64_h_gbr_set (SIM_CPU *, SI);
SI sh64_h_vbr_get (SIM_CPU *);
void sh64_h_vbr_set (SIM_CPU *, SI);
SI sh64_h_pr_get (SIM_CPU *);
void sh64_h_pr_set (SIM_CPU *, SI);
SI sh64_h_macl_get (SIM_CPU *);
@ -288,10 +314,18 @@ void sh64_h_tbit_set (SIM_CPU *, BI);
extern CPUREG_FETCH_FN sh64_fetch_register;
extern CPUREG_STORE_FN sh64_store_register;
typedef struct {
int empty;
} MODEL_SH4_DATA;
typedef struct {
int empty;
} MODEL_SH5_DATA;
typedef struct {
int empty;
} MODEL_SH5_MEDIA_DATA;
/* Collection of various things for the trace handler to use. */
typedef struct trace_record {

13
sim/sh64/cpuall.h
View File

@ -2,9 +2,9 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -35,9 +35,16 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#endif
extern const MACH sh2_mach;
extern const MACH sh2e_mach;
extern const MACH sh2a_fpu_mach;
extern const MACH sh2a_nofpu_mach;
extern const MACH sh3_mach;
extern const MACH sh3e_mach;
extern const MACH sh4_nofpu_mach;
extern const MACH sh4_mach;
extern const MACH sh4a_nofpu_mach;
extern const MACH sh4a_mach;
extern const MACH sh4al_mach;
extern const MACH sh5_mach;
#ifndef WANT_CPU

4770
sim/sh64/decode-compact.c
View File

File diff suppressed because it is too large Load Diff

270
sim/sh64/decode-compact.h
View File

@ -2,9 +2,9 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -43,82 +43,234 @@ typedef enum sh64_compact_insn_type {
, SH64_COMPACT_INSN_CLRT_COMPACT, SH64_COMPACT_INSN_CMPEQ_COMPACT, SH64_COMPACT_INSN_CMPEQI_COMPACT, SH64_COMPACT_INSN_CMPGE_COMPACT
, SH64_COMPACT_INSN_CMPGT_COMPACT, SH64_COMPACT_INSN_CMPHI_COMPACT, SH64_COMPACT_INSN_CMPHS_COMPACT, SH64_COMPACT_INSN_CMPPL_COMPACT
, SH64_COMPACT_INSN_CMPPZ_COMPACT, SH64_COMPACT_INSN_CMPSTR_COMPACT, SH64_COMPACT_INSN_DIV0S_COMPACT, SH64_COMPACT_INSN_DIV0U_COMPACT
, SH64_COMPACT_INSN_DIV1_COMPACT, SH64_COMPACT_INSN_DMULSL_COMPACT, SH64_COMPACT_INSN_DMULUL_COMPACT, SH64_COMPACT_INSN_DT_COMPACT
, SH64_COMPACT_INSN_EXTSB_COMPACT, SH64_COMPACT_INSN_EXTSW_COMPACT, SH64_COMPACT_INSN_EXTUB_COMPACT, SH64_COMPACT_INSN_EXTUW_COMPACT
, SH64_COMPACT_INSN_FABS_COMPACT, SH64_COMPACT_INSN_FADD_COMPACT, SH64_COMPACT_INSN_FCMPEQ_COMPACT, SH64_COMPACT_INSN_FCMPGT_COMPACT
, SH64_COMPACT_INSN_FCNVDS_COMPACT, SH64_COMPACT_INSN_FCNVSD_COMPACT, SH64_COMPACT_INSN_FDIV_COMPACT, SH64_COMPACT_INSN_FIPR_COMPACT
, SH64_COMPACT_INSN_FLDS_COMPACT, SH64_COMPACT_INSN_FLDI0_COMPACT, SH64_COMPACT_INSN_FLDI1_COMPACT, SH64_COMPACT_INSN_FLOAT_COMPACT
, SH64_COMPACT_INSN_FMAC_COMPACT, SH64_COMPACT_INSN_FMOV1_COMPACT, SH64_COMPACT_INSN_FMOV2_COMPACT, SH64_COMPACT_INSN_FMOV3_COMPACT
, SH64_COMPACT_INSN_FMOV4_COMPACT, SH64_COMPACT_INSN_FMOV5_COMPACT, SH64_COMPACT_INSN_FMOV6_COMPACT, SH64_COMPACT_INSN_FMOV7_COMPACT
, SH64_COMPACT_INSN_DIV1_COMPACT, SH64_COMPACT_INSN_DIVU_COMPACT, SH64_COMPACT_INSN_MULR_COMPACT, SH64_COMPACT_INSN_DMULSL_COMPACT
, SH64_COMPACT_INSN_DMULUL_COMPACT, SH64_COMPACT_INSN_DT_COMPACT, SH64_COMPACT_INSN_EXTSB_COMPACT, SH64_COMPACT_INSN_EXTSW_COMPACT
, SH64_COMPACT_INSN_EXTUB_COMPACT, SH64_COMPACT_INSN_EXTUW_COMPACT, SH64_COMPACT_INSN_FABS_COMPACT, SH64_COMPACT_INSN_FADD_COMPACT
, SH64_COMPACT_INSN_FCMPEQ_COMPACT, SH64_COMPACT_INSN_FCMPGT_COMPACT, SH64_COMPACT_INSN_FCNVDS_COMPACT, SH64_COMPACT_INSN_FCNVSD_COMPACT
, SH64_COMPACT_INSN_FDIV_COMPACT, SH64_COMPACT_INSN_FIPR_COMPACT, SH64_COMPACT_INSN_FLDS_COMPACT, SH64_COMPACT_INSN_FLDI0_COMPACT
, SH64_COMPACT_INSN_FLDI1_COMPACT, SH64_COMPACT_INSN_FLOAT_COMPACT, SH64_COMPACT_INSN_FMAC_COMPACT, SH64_COMPACT_INSN_FMOV1_COMPACT
, SH64_COMPACT_INSN_FMOV2_COMPACT, SH64_COMPACT_INSN_FMOV3_COMPACT, SH64_COMPACT_INSN_FMOV4_COMPACT, SH64_COMPACT_INSN_FMOV5_COMPACT
, SH64_COMPACT_INSN_FMOV6_COMPACT, SH64_COMPACT_INSN_FMOV7_COMPACT, SH64_COMPACT_INSN_FMOV8_COMPACT, SH64_COMPACT_INSN_FMOV9_COMPACT
, SH64_COMPACT_INSN_FMUL_COMPACT, SH64_COMPACT_INSN_FNEG_COMPACT, SH64_COMPACT_INSN_FRCHG_COMPACT, SH64_COMPACT_INSN_FSCHG_COMPACT
, SH64_COMPACT_INSN_FSQRT_COMPACT, SH64_COMPACT_INSN_FSTS_COMPACT, SH64_COMPACT_INSN_FSUB_COMPACT, SH64_COMPACT_INSN_FTRC_COMPACT
, SH64_COMPACT_INSN_FTRV_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JSR_COMPACT, SH64_COMPACT_INSN_LDC_COMPACT
, SH64_COMPACT_INSN_LDCL_COMPACT, SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_INSN_LDS_FPUL_COMPACT
, SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, SH64_COMPACT_INSN_LDS_MACH_COMPACT, SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_INSN_LDS_MACL_COMPACT
, SH64_COMPACT_INSN_LDSL_MACL_COMPACT, SH64_COMPACT_INSN_LDS_PR_COMPACT, SH64_COMPACT_INSN_LDSL_PR_COMPACT, SH64_COMPACT_INSN_MACL_COMPACT
, SH64_COMPACT_INSN_MACW_COMPACT, SH64_COMPACT_INSN_MOV_COMPACT, SH64_COMPACT_INSN_MOVI_COMPACT, SH64_COMPACT_INSN_MOVB1_COMPACT
, SH64_COMPACT_INSN_FTRV_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JSR_COMPACT, SH64_COMPACT_INSN_LDC_GBR_COMPACT
, SH64_COMPACT_INSN_LDC_VBR_COMPACT, SH64_COMPACT_INSN_LDC_SR_COMPACT, SH64_COMPACT_INSN_LDCL_GBR_COMPACT, SH64_COMPACT_INSN_LDCL_VBR_COMPACT
, SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_INSN_LDS_FPUL_COMPACT, SH64_COMPACT_INSN_LDSL_FPUL_COMPACT
, SH64_COMPACT_INSN_LDS_MACH_COMPACT, SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_INSN_LDS_MACL_COMPACT, SH64_COMPACT_INSN_LDSL_MACL_COMPACT
, SH64_COMPACT_INSN_LDS_PR_COMPACT, SH64_COMPACT_INSN_LDSL_PR_COMPACT, SH64_COMPACT_INSN_MACL_COMPACT, SH64_COMPACT_INSN_MACW_COMPACT
, SH64_COMPACT_INSN_MOV_COMPACT, SH64_COMPACT_INSN_MOVI_COMPACT, SH64_COMPACT_INSN_MOVI20_COMPACT, SH64_COMPACT_INSN_MOVB1_COMPACT
, SH64_COMPACT_INSN_MOVB2_COMPACT, SH64_COMPACT_INSN_MOVB3_COMPACT, SH64_COMPACT_INSN_MOVB4_COMPACT, SH64_COMPACT_INSN_MOVB5_COMPACT
, SH64_COMPACT_INSN_MOVB6_COMPACT, SH64_COMPACT_INSN_MOVB7_COMPACT, SH64_COMPACT_INSN_MOVB8_COMPACT, SH64_COMPACT_INSN_MOVB9_COMPACT
, SH64_COMPACT_INSN_MOVB10_COMPACT, SH64_COMPACT_INSN_MOVL1_COMPACT, SH64_COMPACT_INSN_MOVL2_COMPACT, SH64_COMPACT_INSN_MOVL3_COMPACT
, SH64_COMPACT_INSN_MOVL4_COMPACT, SH64_COMPACT_INSN_MOVL5_COMPACT, SH64_COMPACT_INSN_MOVL6_COMPACT, SH64_COMPACT_INSN_MOVL7_COMPACT
, SH64_COMPACT_INSN_MOVL8_COMPACT, SH64_COMPACT_INSN_MOVL9_COMPACT, SH64_COMPACT_INSN_MOVL10_COMPACT, SH64_COMPACT_INSN_MOVL11_COMPACT
, SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT, SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW4_COMPACT
, SH64_COMPACT_INSN_MOVW5_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT, SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT
, SH64_COMPACT_INSN_MOVW9_COMPACT, SH64_COMPACT_INSN_MOVW10_COMPACT, SH64_COMPACT_INSN_MOVW11_COMPACT, SH64_COMPACT_INSN_MOVA_COMPACT
, SH64_COMPACT_INSN_MOVCAL_COMPACT, SH64_COMPACT_INSN_MOVT_COMPACT, SH64_COMPACT_INSN_MULL_COMPACT, SH64_COMPACT_INSN_MULSW_COMPACT
, SH64_COMPACT_INSN_MULUW_COMPACT, SH64_COMPACT_INSN_NEG_COMPACT, SH64_COMPACT_INSN_NEGC_COMPACT, SH64_COMPACT_INSN_NOP_COMPACT
, SH64_COMPACT_INSN_NOT_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT, SH64_COMPACT_INSN_OCBWB_COMPACT
, SH64_COMPACT_INSN_OR_COMPACT, SH64_COMPACT_INSN_ORI_COMPACT, SH64_COMPACT_INSN_ORB_COMPACT, SH64_COMPACT_INSN_PREF_COMPACT
, SH64_COMPACT_INSN_ROTCL_COMPACT, SH64_COMPACT_INSN_ROTCR_COMPACT, SH64_COMPACT_INSN_ROTL_COMPACT, SH64_COMPACT_INSN_ROTR_COMPACT
, SH64_COMPACT_INSN_RTS_COMPACT, SH64_COMPACT_INSN_SETS_COMPACT, SH64_COMPACT_INSN_SETT_COMPACT, SH64_COMPACT_INSN_SHAD_COMPACT
, SH64_COMPACT_INSN_SHAL_COMPACT, SH64_COMPACT_INSN_SHAR_COMPACT, SH64_COMPACT_INSN_SHLD_COMPACT, SH64_COMPACT_INSN_SHLL_COMPACT
, SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT, SH64_COMPACT_INSN_SHLR_COMPACT
, SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT, SH64_COMPACT_INSN_STC_GBR_COMPACT
, SH64_COMPACT_INSN_STCL_GBR_COMPACT, SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_INSN_STS_FPUL_COMPACT
, SH64_COMPACT_INSN_STSL_FPUL_COMPACT, SH64_COMPACT_INSN_STS_MACH_COMPACT, SH64_COMPACT_INSN_STSL_MACH_COMPACT, SH64_COMPACT_INSN_STS_MACL_COMPACT
, SH64_COMPACT_INSN_STSL_MACL_COMPACT, SH64_COMPACT_INSN_STS_PR_COMPACT, SH64_COMPACT_INSN_STSL_PR_COMPACT, SH64_COMPACT_INSN_SUB_COMPACT
, SH64_COMPACT_INSN_SUBC_COMPACT, SH64_COMPACT_INSN_SUBV_COMPACT, SH64_COMPACT_INSN_SWAPB_COMPACT, SH64_COMPACT_INSN_SWAPW_COMPACT
, SH64_COMPACT_INSN_TASB_COMPACT, SH64_COMPACT_INSN_TRAPA_COMPACT, SH64_COMPACT_INSN_TST_COMPACT, SH64_COMPACT_INSN_TSTI_COMPACT
, SH64_COMPACT_INSN_TSTB_COMPACT, SH64_COMPACT_INSN_XOR_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORB_COMPACT
, SH64_COMPACT_INSN_XTRCT_COMPACT, SH64_COMPACT_INSN_MAX
, SH64_COMPACT_INSN_MOVL12_COMPACT, SH64_COMPACT_INSN_MOVL13_COMPACT, SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT
, SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW4_COMPACT, SH64_COMPACT_INSN_MOVW5_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT
, SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT, SH64_COMPACT_INSN_MOVW9_COMPACT, SH64_COMPACT_INSN_MOVW10_COMPACT
, SH64_COMPACT_INSN_MOVW11_COMPACT, SH64_COMPACT_INSN_MOVA_COMPACT, SH64_COMPACT_INSN_MOVCAL_COMPACT, SH64_COMPACT_INSN_MOVCOL_COMPACT
, SH64_COMPACT_INSN_MOVT_COMPACT, SH64_COMPACT_INSN_MOVUAL_COMPACT, SH64_COMPACT_INSN_MOVUAL2_COMPACT, SH64_COMPACT_INSN_MULL_COMPACT
, SH64_COMPACT_INSN_MULSW_COMPACT, SH64_COMPACT_INSN_MULUW_COMPACT, SH64_COMPACT_INSN_NEG_COMPACT, SH64_COMPACT_INSN_NEGC_COMPACT
, SH64_COMPACT_INSN_NOP_COMPACT, SH64_COMPACT_INSN_NOT_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT
, SH64_COMPACT_INSN_OCBWB_COMPACT, SH64_COMPACT_INSN_OR_COMPACT, SH64_COMPACT_INSN_ORI_COMPACT, SH64_COMPACT_INSN_ORB_COMPACT
, SH64_COMPACT_INSN_PREF_COMPACT, SH64_COMPACT_INSN_ROTCL_COMPACT, SH64_COMPACT_INSN_ROTCR_COMPACT, SH64_COMPACT_INSN_ROTL_COMPACT
, SH64_COMPACT_INSN_ROTR_COMPACT, SH64_COMPACT_INSN_RTS_COMPACT, SH64_COMPACT_INSN_SETS_COMPACT, SH64_COMPACT_INSN_SETT_COMPACT
, SH64_COMPACT_INSN_SHAD_COMPACT, SH64_COMPACT_INSN_SHAL_COMPACT, SH64_COMPACT_INSN_SHAR_COMPACT, SH64_COMPACT_INSN_SHLD_COMPACT
, SH64_COMPACT_INSN_SHLL_COMPACT, SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT
, SH64_COMPACT_INSN_SHLR_COMPACT, SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT
, SH64_COMPACT_INSN_STC_GBR_COMPACT, SH64_COMPACT_INSN_STC_VBR_COMPACT, SH64_COMPACT_INSN_STCL_GBR_COMPACT, SH64_COMPACT_INSN_STCL_VBR_COMPACT
, SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_INSN_STS_FPUL_COMPACT, SH64_COMPACT_INSN_STSL_FPUL_COMPACT
, SH64_COMPACT_INSN_STS_MACH_COMPACT, SH64_COMPACT_INSN_STSL_MACH_COMPACT, SH64_COMPACT_INSN_STS_MACL_COMPACT, SH64_COMPACT_INSN_STSL_MACL_COMPACT
, SH64_COMPACT_INSN_STS_PR_COMPACT, SH64_COMPACT_INSN_STSL_PR_COMPACT, SH64_COMPACT_INSN_SUB_COMPACT, SH64_COMPACT_INSN_SUBC_COMPACT
, SH64_COMPACT_INSN_SUBV_COMPACT, SH64_COMPACT_INSN_SWAPB_COMPACT, SH64_COMPACT_INSN_SWAPW_COMPACT, SH64_COMPACT_INSN_TASB_COMPACT
, SH64_COMPACT_INSN_TRAPA_COMPACT, SH64_COMPACT_INSN_TST_COMPACT, SH64_COMPACT_INSN_TSTI_COMPACT, SH64_COMPACT_INSN_TSTB_COMPACT
, SH64_COMPACT_INSN_XOR_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORB_COMPACT, SH64_COMPACT_INSN_XTRCT_COMPACT
, SH64_COMPACT_INSN__MAX
} SH64_COMPACT_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family sh64. */
typedef enum sh64_compact_sfmt_type {
SH64_COMPACT_SFMT_EMPTY, SH64_COMPACT_SFMT_ADD_COMPACT, SH64_COMPACT_SFMT_ADDI_COMPACT, SH64_COMPACT_SFMT_ADDC_COMPACT
, SH64_COMPACT_SFMT_ADDV_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT
, SH64_COMPACT_SFMT_BF_COMPACT, SH64_COMPACT_SFMT_BRA_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT, SH64_COMPACT_SFMT_BRK_COMPACT
, SH64_COMPACT_SFMT_BSR_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT, SH64_COMPACT_SFMT_CLRMAC_COMPACT, SH64_COMPACT_SFMT_CLRS_COMPACT
, SH64_COMPACT_SFMT_CLRT_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT, SH64_COMPACT_SFMT_CMPEQI_COMPACT, SH64_COMPACT_SFMT_CMPPL_COMPACT
, SH64_COMPACT_SFMT_DIV0S_COMPACT, SH64_COMPACT_SFMT_DIV0U_COMPACT, SH64_COMPACT_SFMT_DIV1_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT
, SH64_COMPACT_SFMT_DT_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT
, SH64_COMPACT_SFMT_FCMPEQ_COMPACT, SH64_COMPACT_SFMT_FCNVDS_COMPACT, SH64_COMPACT_SFMT_FCNVSD_COMPACT, SH64_COMPACT_SFMT_FIPR_COMPACT
, SH64_COMPACT_SFMT_FLDS_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT, SH64_COMPACT_SFMT_FLOAT_COMPACT, SH64_COMPACT_SFMT_FMAC_COMPACT
, SH64_COMPACT_SFMT_FMOV1_COMPACT, SH64_COMPACT_SFMT_FMOV2_COMPACT, SH64_COMPACT_SFMT_FMOV3_COMPACT, SH64_COMPACT_SFMT_FMOV4_COMPACT
, SH64_COMPACT_SFMT_FMOV5_COMPACT, SH64_COMPACT_SFMT_FMOV6_COMPACT, SH64_COMPACT_SFMT_FMOV7_COMPACT, SH64_COMPACT_SFMT_FRCHG_COMPACT
, SH64_COMPACT_SFMT_BF_COMPACT, SH64_COMPACT_SFMT_BFS_COMPACT, SH64_COMPACT_SFMT_BRA_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT
, SH64_COMPACT_SFMT_BRK_COMPACT, SH64_COMPACT_SFMT_BSR_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT, SH64_COMPACT_SFMT_CLRMAC_COMPACT
, SH64_COMPACT_SFMT_CLRS_COMPACT, SH64_COMPACT_SFMT_CLRT_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT, SH64_COMPACT_SFMT_CMPEQI_COMPACT
, SH64_COMPACT_SFMT_CMPPL_COMPACT, SH64_COMPACT_SFMT_DIV0S_COMPACT, SH64_COMPACT_SFMT_DIV0U_COMPACT, SH64_COMPACT_SFMT_DIV1_COMPACT
, SH64_COMPACT_SFMT_DIVU_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT
, SH64_COMPACT_SFMT_FABS_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT, SH64_COMPACT_SFMT_FCMPEQ_COMPACT, SH64_COMPACT_SFMT_FCNVDS_COMPACT
, SH64_COMPACT_SFMT_FCNVSD_COMPACT, SH64_COMPACT_SFMT_FIPR_COMPACT, SH64_COMPACT_SFMT_FLDS_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT
, SH64_COMPACT_SFMT_FLOAT_COMPACT, SH64_COMPACT_SFMT_FMAC_COMPACT, SH64_COMPACT_SFMT_FMOV1_COMPACT, SH64_COMPACT_SFMT_FMOV2_COMPACT
, SH64_COMPACT_SFMT_FMOV3_COMPACT, SH64_COMPACT_SFMT_FMOV4_COMPACT, SH64_COMPACT_SFMT_FMOV5_COMPACT, SH64_COMPACT_SFMT_FMOV6_COMPACT
, SH64_COMPACT_SFMT_FMOV7_COMPACT, SH64_COMPACT_SFMT_FMOV8_COMPACT, SH64_COMPACT_SFMT_FMOV9_COMPACT, SH64_COMPACT_SFMT_FRCHG_COMPACT
, SH64_COMPACT_SFMT_FSCHG_COMPACT, SH64_COMPACT_SFMT_FSTS_COMPACT, SH64_COMPACT_SFMT_FTRC_COMPACT, SH64_COMPACT_SFMT_FTRV_COMPACT
, SH64_COMPACT_SFMT_JMP_COMPACT, SH64_COMPACT_SFMT_LDC_COMPACT, SH64_COMPACT_SFMT_LDCL_COMPACT, SH64_COMPACT_SFMT_LDS_FPSCR_COMPACT
, SH64_COMPACT_SFMT_LDSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDS_FPUL_COMPACT, SH64_COMPACT_SFMT_LDSL_FPUL_COMPACT, SH64_COMPACT_SFMT_LDS_MACH_COMPACT
, SH64_COMPACT_SFMT_LDSL_MACH_COMPACT, SH64_COMPACT_SFMT_LDS_MACL_COMPACT, SH64_COMPACT_SFMT_LDSL_MACL_COMPACT, SH64_COMPACT_SFMT_LDS_PR_COMPACT
, SH64_COMPACT_SFMT_LDSL_PR_COMPACT, SH64_COMPACT_SFMT_MACL_COMPACT, SH64_COMPACT_SFMT_MACW_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT
, SH64_COMPACT_SFMT_MOVI_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT
, SH64_COMPACT_SFMT_MOVB4_COMPACT, SH64_COMPACT_SFMT_MOVB5_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT
, SH64_COMPACT_SFMT_MOVB8_COMPACT, SH64_COMPACT_SFMT_MOVB9_COMPACT, SH64_COMPACT_SFMT_MOVB10_COMPACT, SH64_COMPACT_SFMT_MOVL4_COMPACT
, SH64_COMPACT_SFMT_MOVL5_COMPACT, SH64_COMPACT_SFMT_MOVL7_COMPACT, SH64_COMPACT_SFMT_MOVL9_COMPACT, SH64_COMPACT_SFMT_MOVL10_COMPACT
, SH64_COMPACT_SFMT_MOVL11_COMPACT, SH64_COMPACT_SFMT_MOVW4_COMPACT, SH64_COMPACT_SFMT_MOVW5_COMPACT, SH64_COMPACT_SFMT_MOVW9_COMPACT
, SH64_COMPACT_SFMT_LDC_GBR_COMPACT, SH64_COMPACT_SFMT_LDC_VBR_COMPACT, SH64_COMPACT_SFMT_LDC_SR_COMPACT, SH64_COMPACT_SFMT_LDCL_GBR_COMPACT
, SH64_COMPACT_SFMT_LDCL_VBR_COMPACT, SH64_COMPACT_SFMT_LDS_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDS_FPUL_COMPACT
, SH64_COMPACT_SFMT_LDSL_FPUL_COMPACT, SH64_COMPACT_SFMT_LDS_MACH_COMPACT, SH64_COMPACT_SFMT_LDSL_MACH_COMPACT, SH64_COMPACT_SFMT_LDS_MACL_COMPACT
, SH64_COMPACT_SFMT_LDSL_MACL_COMPACT, SH64_COMPACT_SFMT_LDS_PR_COMPACT, SH64_COMPACT_SFMT_LDSL_PR_COMPACT, SH64_COMPACT_SFMT_MACL_COMPACT
, SH64_COMPACT_SFMT_MACW_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT, SH64_COMPACT_SFMT_MOVI_COMPACT, SH64_COMPACT_SFMT_MOVI20_COMPACT
, SH64_COMPACT_SFMT_MOVB1_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT, SH64_COMPACT_SFMT_MOVB4_COMPACT
, SH64_COMPACT_SFMT_MOVB5_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT
, SH64_COMPACT_SFMT_MOVB9_COMPACT, SH64_COMPACT_SFMT_MOVB10_COMPACT, SH64_COMPACT_SFMT_MOVL1_COMPACT, SH64_COMPACT_SFMT_MOVL2_COMPACT
, SH64_COMPACT_SFMT_MOVL3_COMPACT, SH64_COMPACT_SFMT_MOVL4_COMPACT, SH64_COMPACT_SFMT_MOVL5_COMPACT, SH64_COMPACT_SFMT_MOVL6_COMPACT
, SH64_COMPACT_SFMT_MOVL7_COMPACT, SH64_COMPACT_SFMT_MOVL8_COMPACT, SH64_COMPACT_SFMT_MOVL9_COMPACT, SH64_COMPACT_SFMT_MOVL10_COMPACT
, SH64_COMPACT_SFMT_MOVL11_COMPACT, SH64_COMPACT_SFMT_MOVL12_COMPACT, SH64_COMPACT_SFMT_MOVL13_COMPACT, SH64_COMPACT_SFMT_MOVW1_COMPACT
, SH64_COMPACT_SFMT_MOVW2_COMPACT, SH64_COMPACT_SFMT_MOVW3_COMPACT, SH64_COMPACT_SFMT_MOVW4_COMPACT, SH64_COMPACT_SFMT_MOVW5_COMPACT
, SH64_COMPACT_SFMT_MOVW6_COMPACT, SH64_COMPACT_SFMT_MOVW7_COMPACT, SH64_COMPACT_SFMT_MOVW8_COMPACT, SH64_COMPACT_SFMT_MOVW9_COMPACT
, SH64_COMPACT_SFMT_MOVW10_COMPACT, SH64_COMPACT_SFMT_MOVW11_COMPACT, SH64_COMPACT_SFMT_MOVA_COMPACT, SH64_COMPACT_SFMT_MOVCAL_COMPACT
, SH64_COMPACT_SFMT_MOVT_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT, SH64_COMPACT_SFMT_NEGC_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT
, SH64_COMPACT_SFMT_ROTCL_COMPACT, SH64_COMPACT_SFMT_RTS_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT
, SH64_COMPACT_SFMT_STC_GBR_COMPACT, SH64_COMPACT_SFMT_STCL_GBR_COMPACT, SH64_COMPACT_SFMT_STS_FPSCR_COMPACT, SH64_COMPACT_SFMT_STSL_FPSCR_COMPACT
, SH64_COMPACT_SFMT_STS_FPUL_COMPACT, SH64_COMPACT_SFMT_STSL_FPUL_COMPACT, SH64_COMPACT_SFMT_STS_MACH_COMPACT, SH64_COMPACT_SFMT_STSL_MACH_COMPACT
, SH64_COMPACT_SFMT_STS_MACL_COMPACT, SH64_COMPACT_SFMT_STSL_MACL_COMPACT, SH64_COMPACT_SFMT_STS_PR_COMPACT, SH64_COMPACT_SFMT_STSL_PR_COMPACT
, SH64_COMPACT_SFMT_TASB_COMPACT, SH64_COMPACT_SFMT_TRAPA_COMPACT, SH64_COMPACT_SFMT_TSTI_COMPACT, SH64_COMPACT_SFMT_TSTB_COMPACT
, SH64_COMPACT_SFMT_XORI_COMPACT
, SH64_COMPACT_SFMT_MOVCOL_COMPACT, SH64_COMPACT_SFMT_MOVT_COMPACT, SH64_COMPACT_SFMT_MOVUAL_COMPACT, SH64_COMPACT_SFMT_MOVUAL2_COMPACT
, SH64_COMPACT_SFMT_MULL_COMPACT, SH64_COMPACT_SFMT_NEGC_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT, SH64_COMPACT_SFMT_PREF_COMPACT
, SH64_COMPACT_SFMT_ROTCL_COMPACT, SH64_COMPACT_SFMT_RTS_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT, SH64_COMPACT_SFMT_STC_GBR_COMPACT
, SH64_COMPACT_SFMT_STC_VBR_COMPACT, SH64_COMPACT_SFMT_STCL_GBR_COMPACT, SH64_COMPACT_SFMT_STCL_VBR_COMPACT, SH64_COMPACT_SFMT_STS_FPSCR_COMPACT
, SH64_COMPACT_SFMT_STSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_STS_FPUL_COMPACT, SH64_COMPACT_SFMT_STSL_FPUL_COMPACT, SH64_COMPACT_SFMT_STS_MACH_COMPACT
, SH64_COMPACT_SFMT_STSL_MACH_COMPACT, SH64_COMPACT_SFMT_STS_MACL_COMPACT, SH64_COMPACT_SFMT_STSL_MACL_COMPACT, SH64_COMPACT_SFMT_STS_PR_COMPACT
, SH64_COMPACT_SFMT_STSL_PR_COMPACT, SH64_COMPACT_SFMT_TASB_COMPACT, SH64_COMPACT_SFMT_TRAPA_COMPACT, SH64_COMPACT_SFMT_TSTI_COMPACT
, SH64_COMPACT_SFMT_TSTB_COMPACT
} SH64_COMPACT_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_putcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_getcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_pt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_ftrvs (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fsqrtd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fdivd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_cond_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_blink (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_use_tr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
extern int sh64_model_sh5_media_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
extern int sh64_model_sh5_media_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
/* Profiling before/after handlers (user written) */

2441
sim/sh64/decode-media.c
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File diff suppressed because one or more lines are too long

175
sim/sh64/decode-media.h
View File

@ -2,9 +2,9 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -87,7 +87,7 @@ typedef enum sh64_media_insn_type {
, SH64_MEDIA_INSN_STLOL, SH64_MEDIA_INSN_STLOQ, SH64_MEDIA_INSN_STXB, SH64_MEDIA_INSN_STXL
, SH64_MEDIA_INSN_STXQ, SH64_MEDIA_INSN_STXW, SH64_MEDIA_INSN_SUB, SH64_MEDIA_INSN_SUBL
, SH64_MEDIA_INSN_SWAPQ, SH64_MEDIA_INSN_SYNCI, SH64_MEDIA_INSN_SYNCO, SH64_MEDIA_INSN_TRAPA
, SH64_MEDIA_INSN_XOR, SH64_MEDIA_INSN_XORI, SH64_MEDIA_INSN_MAX
, SH64_MEDIA_INSN_XOR, SH64_MEDIA_INSN_XORI, SH64_MEDIA_INSN__MAX
} SH64_MEDIA_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family sh64. */
@ -96,23 +96,170 @@ typedef enum sh64_media_sfmt_type {
, SH64_MEDIA_SFMT_BEQ, SH64_MEDIA_SFMT_BEQI, SH64_MEDIA_SFMT_BLINK, SH64_MEDIA_SFMT_BRK
, SH64_MEDIA_SFMT_BYTEREV, SH64_MEDIA_SFMT_CMVEQ, SH64_MEDIA_SFMT_FABSD, SH64_MEDIA_SFMT_FABSS
, SH64_MEDIA_SFMT_FADDD, SH64_MEDIA_SFMT_FADDS, SH64_MEDIA_SFMT_FCMPEQD, SH64_MEDIA_SFMT_FCMPEQS
, SH64_MEDIA_SFMT_FCNVDS, SH64_MEDIA_SFMT_FCNVSD, SH64_MEDIA_SFMT_FIPRS, SH64_MEDIA_SFMT_FLDD
, SH64_MEDIA_SFMT_FLDP, SH64_MEDIA_SFMT_FLDS, SH64_MEDIA_SFMT_FLDXD, SH64_MEDIA_SFMT_FLDXP
, SH64_MEDIA_SFMT_FLDXS, SH64_MEDIA_SFMT_FMACS, SH64_MEDIA_SFMT_FMOVDQ, SH64_MEDIA_SFMT_FMOVLS
, SH64_MEDIA_SFMT_FMOVQD, SH64_MEDIA_SFMT_FMOVSL, SH64_MEDIA_SFMT_FSTD, SH64_MEDIA_SFMT_FSTP
, SH64_MEDIA_SFMT_FSTS, SH64_MEDIA_SFMT_FSTXD, SH64_MEDIA_SFMT_FSTXP, SH64_MEDIA_SFMT_FSTXS
, SH64_MEDIA_SFMT_FTRVS, SH64_MEDIA_SFMT_GETCON, SH64_MEDIA_SFMT_GETTR, SH64_MEDIA_SFMT_LDB
, SH64_MEDIA_SFMT_LDL, SH64_MEDIA_SFMT_LDQ, SH64_MEDIA_SFMT_LDUW, SH64_MEDIA_SFMT_LDXB
, SH64_MEDIA_SFMT_MCMV, SH64_MEDIA_SFMT_MOVI, SH64_MEDIA_SFMT_MPERMW, SH64_MEDIA_SFMT_ORI
, SH64_MEDIA_SFMT_PTA, SH64_MEDIA_SFMT_PTABS, SH64_MEDIA_SFMT_PTREL, SH64_MEDIA_SFMT_PUTCON
, SH64_MEDIA_SFMT_FCNVDS, SH64_MEDIA_SFMT_FCNVSD, SH64_MEDIA_SFMT_FGETSCR, SH64_MEDIA_SFMT_FIPRS
, SH64_MEDIA_SFMT_FLDD, SH64_MEDIA_SFMT_FLDP, SH64_MEDIA_SFMT_FLDS, SH64_MEDIA_SFMT_FLDXD
, SH64_MEDIA_SFMT_FLDXP, SH64_MEDIA_SFMT_FLDXS, SH64_MEDIA_SFMT_FMACS, SH64_MEDIA_SFMT_FMOVDQ
, SH64_MEDIA_SFMT_FMOVLS, SH64_MEDIA_SFMT_FMOVQD, SH64_MEDIA_SFMT_FMOVSL, SH64_MEDIA_SFMT_FPUTSCR
, SH64_MEDIA_SFMT_FSTD, SH64_MEDIA_SFMT_FSTS, SH64_MEDIA_SFMT_FSTXD, SH64_MEDIA_SFMT_FSTXS
, SH64_MEDIA_SFMT_FTRVS, SH64_MEDIA_SFMT_GETCFG, SH64_MEDIA_SFMT_GETCON, SH64_MEDIA_SFMT_GETTR
, SH64_MEDIA_SFMT_LDB, SH64_MEDIA_SFMT_LDL, SH64_MEDIA_SFMT_LDQ, SH64_MEDIA_SFMT_LDUW
, SH64_MEDIA_SFMT_LDHIL, SH64_MEDIA_SFMT_LDHIQ, SH64_MEDIA_SFMT_LDLOL, SH64_MEDIA_SFMT_LDLOQ
, SH64_MEDIA_SFMT_LDXB, SH64_MEDIA_SFMT_LDXL, SH64_MEDIA_SFMT_LDXQ, SH64_MEDIA_SFMT_LDXUB
, SH64_MEDIA_SFMT_LDXUW, SH64_MEDIA_SFMT_LDXW, SH64_MEDIA_SFMT_MCMV, SH64_MEDIA_SFMT_MOVI
, SH64_MEDIA_SFMT_MPERMW, SH64_MEDIA_SFMT_NOP, SH64_MEDIA_SFMT_ORI, SH64_MEDIA_SFMT_PTA
, SH64_MEDIA_SFMT_PTABS, SH64_MEDIA_SFMT_PTREL, SH64_MEDIA_SFMT_PUTCFG, SH64_MEDIA_SFMT_PUTCON
, SH64_MEDIA_SFMT_SHARI, SH64_MEDIA_SFMT_SHARIL, SH64_MEDIA_SFMT_SHORI, SH64_MEDIA_SFMT_STB
, SH64_MEDIA_SFMT_STL, SH64_MEDIA_SFMT_STQ, SH64_MEDIA_SFMT_STW, SH64_MEDIA_SFMT_STHIL
, SH64_MEDIA_SFMT_STXB, SH64_MEDIA_SFMT_SWAPQ, SH64_MEDIA_SFMT_TRAPA, SH64_MEDIA_SFMT_XORI
, SH64_MEDIA_SFMT_STHIQ, SH64_MEDIA_SFMT_STLOL, SH64_MEDIA_SFMT_STLOQ, SH64_MEDIA_SFMT_STXB
, SH64_MEDIA_SFMT_STXL, SH64_MEDIA_SFMT_STXQ, SH64_MEDIA_SFMT_STXW, SH64_MEDIA_SFMT_SWAPQ
, SH64_MEDIA_SFMT_TRAPA, SH64_MEDIA_SFMT_XORI
} SH64_MEDIA_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_putcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_getcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_pt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_ftrvs (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fsqrtd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fdivd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_cond_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_blink (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_use_tr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
extern int sh64_model_sh5_media_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
extern int sh64_model_sh5_media_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
/* Profiling before/after handlers (user written) */

286
sim/sh64/defs-compact.h
View File

@ -2,9 +2,9 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -31,26 +31,19 @@ union sem_fields {
struct { /* no operands */
int empty;
} fmt_empty;
struct { /* */
SI f_dn;
} sfmt_fcnvds_compact;
struct { /* */
IADDR i_disp12;
} sfmt_bra_compact;
struct { /* */
IADDR i_disp8;
} sfmt_bf_compact;
struct { /* */
SI f_imm4x2;
UINT f_rm;
} sfmt_movw11_compact;
struct { /* */
SI f_imm8x2;
UINT f_rn;
} sfmt_movw10_compact;
struct { /* */
SI f_imm4x2;
UINT f_rn;
UINT f_rm;
} sfmt_movw5_compact;
struct { /* */
SI f_imm8x4;
@ -60,6 +53,10 @@ union sem_fields {
UINT f_imm4;
UINT f_rm;
} sfmt_movb5_compact;
struct { /* */
INT f_imm20;
UINT f_rn;
} sfmt_movi20_compact;
struct { /* */
SI f_vm;
SI f_vn;
@ -68,11 +65,26 @@ union sem_fields {
UINT f_imm8;
UINT f_rn;
} sfmt_addi_compact;
struct { /* */
SI f_imm12x4;
UINT f_rm;
UINT f_rn;
} sfmt_movl12_compact;
struct { /* */
SI f_imm4x4;
UINT f_rm;
UINT f_rn;
} sfmt_movl5_compact;
struct { /* */
SI f_dm;
SI f_imm12x8;
UINT f_rn;
} sfmt_fmov9_compact;
struct { /* */
SI f_dn;
SI f_imm12x8;
UINT f_rm;
} sfmt_fmov8_compact;
#if WITH_SCACHE_PBB
/* Writeback handler. */
struct {
@ -141,10 +153,10 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_ADD_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_ADDI_COMPACT_VARS \
UINT f_op4; \
@ -153,9 +165,9 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_ADDI_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_AND_COMPACT_VARS \
UINT f_op4; \
@ -165,10 +177,10 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_AND_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_ANDI_COMPACT_VARS \
UINT f_op8; \
@ -176,8 +188,8 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_ANDI_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_ANDB_COMPACT_VARS \
UINT f_op8; \
@ -185,8 +197,8 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_ANDB_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_BF_COMPACT_VARS \
UINT f_op8; \
@ -194,8 +206,8 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_BF_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
f_disp8 = ((((EXTRACT_LSB0_INT (insn, 16, 7, 8)) << (1))) + (((pc) + (4)))); \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_BRA_COMPACT_VARS \
UINT f_op4; \
@ -203,8 +215,8 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_BRA_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_disp12 = ((((EXTRACT_LSB0_INT (insn, 16, 11, 12)) << (1))) + (((pc) + (4)))); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_disp12 = ((((EXTRACT_MSB0_INT (insn, 16, 4, 12)) << (1))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_BRAF_COMPACT_VARS \
UINT f_op4; \
@ -213,16 +225,16 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_BRAF_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_BRK_COMPACT_VARS \
UINT f_op16; \
unsigned int length;
#define EXTRACT_IFMT_BRK_COMPACT_CODE \
length = 2; \
f_op16 = EXTRACT_LSB0_UINT (insn, 16, 15, 16); \
f_op16 = EXTRACT_MSB0_UINT (insn, 16, 0, 16); \
#define EXTRACT_IFMT_FABS_COMPACT_VARS \
UINT f_op4; \
@ -231,9 +243,9 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FABS_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_FADD_COMPACT_VARS \
UINT f_op4; \
@ -243,23 +255,23 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FADD_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_FCNVDS_COMPACT_VARS \
UINT f_op4; \
SI f_dn; \
UINT f_8_1; \
UINT f_7_1; \
UINT f_sub8; \
unsigned int length;
#define EXTRACT_IFMT_FCNVDS_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_dn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 3)) << (1)); \
f_8_1 = EXTRACT_LSB0_UINT (insn, 16, 8, 1); \
f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_dn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 3)) << (1)); \
f_7_1 = EXTRACT_MSB0_UINT (insn, 16, 7, 1); \
f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_FIPR_COMPACT_VARS \
UINT f_op4; \
@ -269,10 +281,10 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FIPR_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2)); \
f_vm = ((EXTRACT_LSB0_UINT (insn, 16, 9, 2)) << (2)); \
f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_vn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 2)) << (2)); \
f_vm = ((EXTRACT_MSB0_UINT (insn, 16, 6, 2)) << (2)); \
f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_FLDS_COMPACT_VARS \
UINT f_op4; \
@ -281,9 +293,9 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FLDS_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_FMAC_COMPACT_VARS \
UINT f_op4; \
@ -293,10 +305,23 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FMAC_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_FMOV1_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
UINT f_sub4; \
unsigned int length;
#define EXTRACT_IFMT_FMOV1_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_FMOV2_COMPACT_VARS \
UINT f_op4; \
@ -306,10 +331,10 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FMOV2_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_FMOV5_COMPACT_VARS \
UINT f_op4; \
@ -319,10 +344,48 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FMOV5_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_FMOV8_COMPACT_VARS \
UINT f_op4; \
SI f_dn; \
UINT f_7_1; \
UINT f_rm; \
UINT f_sub4; \
UINT f_16_4; \
SI f_imm12x8; \
unsigned int length;
#define EXTRACT_IFMT_FMOV8_COMPACT_CODE \
length = 4; \
f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_dn = ((EXTRACT_MSB0_UINT (insn, 32, 4, 3)) << (1)); \
f_7_1 = EXTRACT_MSB0_UINT (insn, 32, 7, 1); \
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_16_4 = EXTRACT_MSB0_UINT (insn, 32, 16, 4); \
f_imm12x8 = ((EXTRACT_MSB0_INT (insn, 32, 20, 12)) << (3)); \
#define EXTRACT_IFMT_FMOV9_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
SI f_dm; \
UINT f_11_1; \
UINT f_sub4; \
UINT f_16_4; \
SI f_imm12x8; \
unsigned int length;
#define EXTRACT_IFMT_FMOV9_COMPACT_CODE \
length = 4; \
f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_dm = ((EXTRACT_MSB0_UINT (insn, 32, 8, 3)) << (1)); \
f_11_1 = EXTRACT_MSB0_UINT (insn, 32, 11, 1); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_16_4 = EXTRACT_MSB0_UINT (insn, 32, 16, 4); \
f_imm12x8 = ((EXTRACT_MSB0_INT (insn, 32, 20, 12)) << (3)); \
#define EXTRACT_IFMT_FTRV_COMPACT_VARS \
UINT f_op4; \
@ -331,9 +394,26 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FTRV_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2)); \
f_sub10 = EXTRACT_LSB0_UINT (insn, 16, 9, 10); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_vn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 2)) << (2)); \
f_sub10 = EXTRACT_MSB0_UINT (insn, 16, 6, 10); \
#define EXTRACT_IFMT_MOVI20_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
INT f_imm20_hi; \
UINT f_imm20_lo; \
INT f_imm20; \
UINT f_sub4; \
unsigned int length;
#define EXTRACT_IFMT_MOVI20_COMPACT_CODE \
length = 4; \
f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_imm20_hi = EXTRACT_MSB0_INT (insn, 32, 8, 4); \
f_imm20_lo = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
f_imm20 = ((((f_imm20_hi) << (16))) | (f_imm20_lo));\
f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
#define EXTRACT_IFMT_MOVB5_COMPACT_VARS \
UINT f_op8; \
@ -342,9 +422,9 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_MOVB5_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
f_imm4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_imm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_MOVL4_COMPACT_VARS \
UINT f_op8; \
@ -352,8 +432,8 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_MOVL4_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_imm8x4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
#define EXTRACT_IFMT_MOVL5_COMPACT_VARS \
UINT f_op4; \
@ -363,10 +443,10 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_MOVL5_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
f_imm4x4 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (2)); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_imm4x4 = ((EXTRACT_MSB0_UINT (insn, 16, 12, 4)) << (2)); \
#define EXTRACT_IFMT_MOVL10_COMPACT_VARS \
UINT f_op4; \
@ -375,9 +455,26 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_MOVL10_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_imm8x4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
#define EXTRACT_IFMT_MOVL12_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
UINT f_sub4; \
UINT f_16_4; \
SI f_imm12x4; \
unsigned int length;
#define EXTRACT_IFMT_MOVL12_COMPACT_CODE \
length = 4; \
f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_16_4 = EXTRACT_MSB0_UINT (insn, 32, 16, 4); \
f_imm12x4 = ((EXTRACT_MSB0_INT (insn, 32, 20, 12)) << (2)); \
#define EXTRACT_IFMT_MOVW4_COMPACT_VARS \
UINT f_op8; \
@ -385,19 +482,19 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_MOVW4_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_imm8x2 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \
#define EXTRACT_IFMT_MOVW5_COMPACT_VARS \
UINT f_op8; \
UINT f_rn; \
UINT f_rm; \
SI f_imm4x2; \
unsigned int length;
#define EXTRACT_IFMT_MOVW5_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)); \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_imm4x2 = ((EXTRACT_MSB0_UINT (insn, 16, 12, 4)) << (1)); \
#define EXTRACT_IFMT_MOVW10_COMPACT_VARS \
UINT f_op4; \
@ -406,19 +503,8 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_MOVW10_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); \
#define EXTRACT_IFMT_MOVW11_COMPACT_VARS \
UINT f_op8; \
UINT f_rm; \
SI f_imm4x2; \
unsigned int length;
#define EXTRACT_IFMT_MOVW11_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)); \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_imm8x2 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \
#endif /* DEFS_SH64_COMPACT_H */

563
sim/sh64/defs-media.h
View File

@ -2,9 +2,9 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -56,11 +56,6 @@ union sem_fields {
UINT f_dest;
UINT f_left;
} sfmt_xori;
struct { /* */
INT f_disp6;
UINT f_dest;
UINT f_left;
} sfmt_sthil;
struct { /* */
UINT f_dest;
UINT f_left;
@ -76,6 +71,11 @@ union sem_fields {
UINT f_dest;
UINT f_left;
} sfmt_lduw;
struct { /* */
INT f_disp6;
UINT f_dest;
UINT f_left;
} sfmt_getcfg;
struct { /* */
SI f_disp10x4;
UINT f_dest;
@ -106,11 +106,6 @@ union sem_fields {
UINT f_left;
UINT f_right;
} sfmt_add;
struct {
INT f_disp6;
UINT f_dest;
UINT f_left;
} sfmt_ldhil;
#if WITH_SCACHE_PBB
/* Writeback handler. */
struct {
@ -181,12 +176,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_ADD_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_ADDI_VARS \
UINT f_op; \
@ -197,11 +192,11 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_ADDI_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10 = EXTRACT_MSB0_INT (insn, 32, 12, 10); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_ALLOCO_VARS \
UINT f_op; \
@ -213,12 +208,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_ALLOCO_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_disp6x32 = ((EXTRACT_LSB0_INT (insn, 32, 15, 6)) << (5)); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp6x32 = ((EXTRACT_MSB0_INT (insn, 32, 16, 6)) << (5)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op; \
@ -226,20 +221,20 @@ struct scache {
UINT f_ext; \
UINT f_right; \
UINT f_likely; \
UINT f_8_2; \
UINT f_23_2; \
UINT f_tra; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_BEQ_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \
f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \
f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_BEQI_VARS \
UINT f_op; \
@ -247,24 +242,24 @@ struct scache {
UINT f_ext; \
INT f_imm6; \
UINT f_likely; \
UINT f_8_2; \
UINT f_23_2; \
UINT f_tra; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_BEQI_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_imm6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); \
f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_imm6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); \
f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \
f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \
f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_BLINK_VARS \
UINT f_op; \
UINT f_25; \
UINT f_6_3; \
UINT f_trb; \
UINT f_ext; \
UINT f_right; \
@ -273,13 +268,13 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_BLINK_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 3); \
f_trb = EXTRACT_LSB0_UINT (insn, 32, 22, 3); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_6_3 = EXTRACT_MSB0_UINT (insn, 32, 6, 3); \
f_trb = EXTRACT_MSB0_UINT (insn, 32, 9, 3); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_BRK_VARS \
UINT f_op; \
@ -291,12 +286,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_BRK_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_BYTEREV_VARS \
UINT f_op; \
@ -308,50 +303,50 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_BYTEREV_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FABSD_VARS \
UINT f_op; \
UINT f_ext; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FABSD_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FABSS_VARS \
UINT f_op; \
UINT f_ext; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FABSS_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FADDD_VARS \
UINT f_op; \
@ -363,12 +358,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FADDD_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FADDS_VARS \
UINT f_op; \
@ -380,12 +375,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FADDS_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FCMPEQD_VARS \
UINT f_op; \
@ -397,12 +392,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FCMPEQD_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FCMPEQS_VARS \
UINT f_op; \
@ -414,50 +409,50 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FCMPEQS_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FCNVDS_VARS \
UINT f_op; \
UINT f_ext; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FCNVDS_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FCNVSD_VARS \
UINT f_op; \
UINT f_ext; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FCNVSD_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FGETSCR_VARS \
UINT f_op; \
@ -469,12 +464,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FGETSCR_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FIPRS_VARS \
UINT f_op; \
@ -486,12 +481,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FIPRS_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FLDD_VARS \
UINT f_op; \
@ -502,11 +497,11 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FLDD_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FLDP_VARS \
UINT f_op; \
@ -517,11 +512,11 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FLDP_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FLDS_VARS \
UINT f_op; \
@ -532,11 +527,11 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FLDS_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x4 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (2)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FLDXD_VARS \
UINT f_op; \
@ -548,12 +543,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FLDXD_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FLDXP_VARS \
UINT f_op; \
@ -565,31 +560,31 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FLDXP_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FMOVDQ_VARS \
UINT f_op; \
UINT f_ext; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FMOVDQ_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FMOVLS_VARS \
UINT f_op; \
@ -601,50 +596,50 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FMOVLS_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FMOVSL_VARS \
UINT f_op; \
UINT f_ext; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FMOVSL_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FPUTSCR_VARS \
UINT f_op; \
UINT f_ext; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FPUTSCR_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FSTXD_VARS \
UINT f_op; \
@ -656,12 +651,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FSTXD_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FTRVS_VARS \
UINT f_op; \
@ -673,12 +668,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_FTRVS_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_GETCFG_VARS \
UINT f_op; \
@ -690,12 +685,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_GETCFG_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_disp6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_GETCON_VARS \
UINT f_op; \
@ -707,12 +702,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_GETCON_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_LDL_VARS \
UINT f_op; \
@ -723,11 +718,11 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_LDL_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x4 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (2)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_LDQ_VARS \
UINT f_op; \
@ -738,11 +733,11 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_LDQ_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_MMACNFX_WL_VARS \
UINT f_op; \
@ -754,12 +749,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_MMACNFX_WL_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_MOVI_VARS \
UINT f_op; \
@ -769,10 +764,10 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_MOVI_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_imm16 = EXTRACT_LSB0_INT (insn, 32, 25, 16); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_imm16 = EXTRACT_MSB0_INT (insn, 32, 6, 16); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_ORI_VARS \
UINT f_op; \
@ -783,11 +778,11 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_ORI_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_imm10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_imm10 = EXTRACT_MSB0_INT (insn, 32, 12, 10); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_PREFI_VARS \
UINT f_op; \
@ -799,29 +794,29 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_PREFI_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_disp6x32 = ((EXTRACT_LSB0_INT (insn, 32, 15, 6)) << (5)); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp6x32 = ((EXTRACT_MSB0_INT (insn, 32, 16, 6)) << (5)); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_PTA_VARS \
UINT f_op; \
DI f_disp16; \
UINT f_likely; \
UINT f_8_2; \
UINT f_23_2; \
UINT f_tra; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_PTA_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_disp16 = ((((EXTRACT_LSB0_INT (insn, 32, 25, 16)) << (2))) + (pc)); \
f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 6, 16)) << (2))) + (pc)); \
f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \
f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \
f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_PTABS_VARS \
UINT f_op; \
@ -829,20 +824,20 @@ struct scache {
UINT f_ext; \
UINT f_right; \
UINT f_likely; \
UINT f_8_2; \
UINT f_23_2; \
UINT f_tra; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_PTABS_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \
f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \
f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_PUTCON_VARS \
UINT f_op; \
@ -854,12 +849,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_PUTCON_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_SHARI_VARS \
UINT f_op; \
@ -871,12 +866,12 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_SHARI_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_uimm6 = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_SHORI_VARS \
UINT f_op; \
@ -886,10 +881,10 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_SHORI_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 25, 16); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 6, 16); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_STW_VARS \
UINT f_op; \
@ -900,11 +895,11 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_STW_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_disp10x2 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (1)); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x2 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (1)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_TRAPA_VARS \
UINT f_op; \
@ -916,11 +911,11 @@ struct scache {
unsigned int length;
#define EXTRACT_IFMT_TRAPA_CODE \
length = 4; \
f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#endif /* DEFS_SH64_MEDIA_H */

1306
sim/sh64/sem-compact-switch.c
View File

File diff suppressed because it is too large Load Diff

1310
sim/sh64/sem-compact.c
View File

File diff suppressed because it is too large Load Diff

247
sim/sh64/sem-media-switch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -548,12 +548,19 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
#undef FLD
}
@ -626,6 +633,8 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -633,6 +642,7 @@ if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -651,6 +661,8 @@ if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -658,6 +670,7 @@ if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -676,6 +689,8 @@ if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -683,6 +698,7 @@ if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -701,6 +717,8 @@ if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -708,6 +726,7 @@ if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -726,6 +745,8 @@ if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -733,6 +754,7 @@ if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -751,6 +773,8 @@ if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -758,6 +782,7 @@ if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -787,6 +812,11 @@ if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
if (EQSI (FLD (f_dest), 63)) {
((void) 0); /*nop*/
} else {
((void) 0); /*nop*/
}
}
SEM_BRANCH_FINI (vpc);
@ -804,6 +834,8 @@ if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -811,6 +843,7 @@ if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -829,6 +862,8 @@ if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -836,6 +871,7 @@ if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -1327,12 +1363,16 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_shori.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
((void) 0); /*nop*/
{
SF opval = SUBWORDSISF (CPU (h_fpscr));
CPU (h_fr[FLD (f_dest)]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
}
#undef FLD
}
@ -1348,17 +1388,18 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
UQI tmp_g;
UQI tmp_h;
SF tmp_temp;
tmp_g = FLD (f_left);
tmp_h = FLD (f_right);
tmp_temp = sh64_fmuls (current_cpu, CPU (h_fr[tmp_g]), CPU (h_fr[tmp_h]));
tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 1)]), CPU (h_fr[ADDQI (tmp_h, 1)])));
tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 2)]), CPU (h_fr[ADDQI (tmp_h, 2)])));
tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 3)]), CPU (h_fr[ADDQI (tmp_h, 3)])));
{
SF opval = tmp_temp;
SF opval = GET_H_FV (FLD (f_left));
SET_H_FV (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval);
}
{
SF opval = GET_H_FV (FLD (f_right));
SET_H_FV (FLD (f_right), opval);
TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval);
}
{
SF opval = sh64_fiprs (current_cpu, FLD (f_left), FLD (f_right));
CPU (h_fr[FLD (f_dest)]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
}
@ -1397,18 +1438,12 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI tmp_f;
tmp_f = FLD (f_dest);
{
SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)));
CPU (h_fr[tmp_f]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
}
{
SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)));
CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
SF opval = GET_H_FP (FLD (f_dest));
SET_H_FP (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval);
}
sh64_fldp (current_cpu, pc, GET_H_GR (FLD (f_left)), FLD (f_disp10x8), FLD (f_dest));
}
#undef FLD
@ -1463,18 +1498,12 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI tmp_f;
tmp_f = FLD (f_dest);
{
SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
CPU (h_fr[tmp_f]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
}
{
SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)));
CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
SF opval = GET_H_FP (FLD (f_dest));
SET_H_FP (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval);
}
sh64_fldp (current_cpu, pc, GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)), FLD (f_dest));
}
#undef FLD
@ -1789,12 +1818,16 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_fabsd.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
((void) 0); /*nop*/
{
SI opval = SUBWORDSFSI (CPU (h_fr[FLD (f_left_right)]));
CPU (h_fpscr) = opval;
TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval);
}
#undef FLD
}
@ -1867,18 +1900,12 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI tmp_f;
tmp_f = FLD (f_dest);
{
SF opval = CPU (h_fr[tmp_f]);
SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
}
{
SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
SF opval = GET_H_FP (FLD (f_dest));
SET_H_FP (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval);
}
sh64_fstp (current_cpu, pc, GET_H_GR (FLD (f_left)), FLD (f_disp10x8), FLD (f_dest));
}
#undef FLD
@ -1933,18 +1960,12 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI tmp_f;
tmp_f = FLD (f_dest);
{
SF opval = CPU (h_fr[tmp_f]);
SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
}
{
SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
SF opval = GET_H_FP (FLD (f_dest));
SET_H_FP (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval);
}
sh64_fstp (current_cpu, pc, GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)), FLD (f_dest));
}
#undef FLD
@ -2093,7 +2114,24 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
SF opval = GET_H_FMTX (FLD (f_left));
SET_H_FMTX (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "fmtx", 'f', opval);
}
{
SF opval = GET_H_FV (FLD (f_right));
SET_H_FV (FLD (f_right), opval);
TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval);
}
{
SF opval = GET_H_FV (FLD (f_dest));
SET_H_FV (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval);
}
sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest));
}
#undef FLD
}
@ -2103,12 +2141,21 @@ sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest));
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI tmp_address;
tmp_address = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
((void) 0); /*nop*/
{
DI opval = GETMEMSI (current_cpu, pc, tmp_address);
SET_H_GR (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
}
#undef FLD
}
@ -2156,12 +2203,19 @@ sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest));
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
#undef FLD
}
@ -2285,7 +2339,7 @@ sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest));
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@ -2348,7 +2402,7 @@ if (ANDQI (tmp_bytecount, 2)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@ -2417,7 +2471,7 @@ if (ANDQI (tmp_bytecount, 4)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@ -2480,7 +2534,7 @@ if (ANDQI (tmp_bytecount, 1)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@ -4383,12 +4437,19 @@ if (ANDQI (tmp_bytecount, 1)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
#undef FLD
}
@ -4398,12 +4459,19 @@ if (ANDQI (tmp_bytecount, 1)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
#undef FLD
}
@ -4413,12 +4481,19 @@ if (ANDQI (tmp_bytecount, 1)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
#undef FLD
}
@ -4466,12 +4541,19 @@ if (ANDQI (tmp_bytecount, 1)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
#undef FLD
}
@ -4486,11 +4568,14 @@ if (ANDQI (tmp_bytecount, 1)) {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
{
DI opval = ADDSI (FLD (f_disp16), 1);
CPU (h_tr[FLD (f_tra)]) = opval;
TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
}
}
#undef FLD
}
@ -4505,11 +4590,14 @@ if (ANDQI (tmp_bytecount, 1)) {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
{
DI opval = GET_H_GR (FLD (f_right));
CPU (h_tr[FLD (f_tra)]) = opval;
TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
}
}
#undef FLD
}
@ -4524,11 +4612,14 @@ if (ANDQI (tmp_bytecount, 1)) {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
{
DI opval = FLD (f_disp16);
CPU (h_tr[FLD (f_tra)]) = opval;
TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
}
}
#undef FLD
}
@ -4543,11 +4634,14 @@ if (ANDQI (tmp_bytecount, 1)) {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
{
DI opval = ADDDI (pc, GET_H_GR (FLD (f_right)));
CPU (h_tr[FLD (f_tra)]) = opval;
TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
}
}
#undef FLD
}
@ -4557,12 +4651,21 @@ if (ANDQI (tmp_bytecount, 1)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI tmp_address;
tmp_address = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
((void) 0); /*nop*/
{
SI opval = GET_H_GR (FLD (f_dest));
SETMEMSI (current_cpu, pc, tmp_address, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
#undef FLD
}
@ -4944,7 +5047,7 @@ if (ANDQI (tmp_bytecount, 1)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@ -5028,7 +5131,7 @@ if (ANDQI (tmp_bytecount, 1)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@ -5134,7 +5237,7 @@ if (ANDQI (tmp_bytecount, 1)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@ -5218,7 +5321,7 @@ if (ANDQI (tmp_bytecount, 2)) {
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

247
sim/sh64/sem-media.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -18,7 +18,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -311,13 +311,20 @@ SEM_FN_NAME (sh64_media,addzl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,alloco) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
return vpc;
#undef FLD
@ -398,6 +405,8 @@ SEM_FN_NAME (sh64_media,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -405,6 +414,7 @@ if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -425,6 +435,8 @@ SEM_FN_NAME (sh64_media,beqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -432,6 +444,7 @@ if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -452,6 +465,8 @@ SEM_FN_NAME (sh64_media,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -459,6 +474,7 @@ if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -479,6 +495,8 @@ SEM_FN_NAME (sh64_media,bgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -486,6 +504,7 @@ if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -506,6 +525,8 @@ SEM_FN_NAME (sh64_media,bgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -513,6 +534,7 @@ if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -533,6 +555,8 @@ SEM_FN_NAME (sh64_media,bgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -540,6 +564,7 @@ if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -571,6 +596,11 @@ SEM_FN_NAME (sh64_media,blink) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
if (EQSI (FLD (f_dest), 63)) {
((void) 0); /*nop*/
} else {
((void) 0); /*nop*/
}
}
SEM_BRANCH_FINI (vpc);
@ -590,6 +620,8 @@ SEM_FN_NAME (sh64_media,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -597,6 +629,7 @@ if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -617,6 +650,8 @@ SEM_FN_NAME (sh64_media,bnei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
{
UDI opval = CPU (h_tr[FLD (f_tra)]);
@ -624,6 +659,7 @@ if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
abuf->written = written;
@ -1162,13 +1198,17 @@ SEM_FN_NAME (sh64_media,fdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,fgetscr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_shori.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
((void) 0); /*nop*/
{
SF opval = SUBWORDSISF (CPU (h_fpscr));
CPU (h_fr[FLD (f_dest)]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
}
return vpc;
#undef FLD
@ -1186,17 +1226,18 @@ SEM_FN_NAME (sh64_media,fiprs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
UQI tmp_g;
UQI tmp_h;
SF tmp_temp;
tmp_g = FLD (f_left);
tmp_h = FLD (f_right);
tmp_temp = sh64_fmuls (current_cpu, CPU (h_fr[tmp_g]), CPU (h_fr[tmp_h]));
tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 1)]), CPU (h_fr[ADDQI (tmp_h, 1)])));
tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 2)]), CPU (h_fr[ADDQI (tmp_h, 2)])));
tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 3)]), CPU (h_fr[ADDQI (tmp_h, 3)])));
{
SF opval = tmp_temp;
SF opval = GET_H_FV (FLD (f_left));
SET_H_FV (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval);
}
{
SF opval = GET_H_FV (FLD (f_right));
SET_H_FV (FLD (f_right), opval);
TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval);
}
{
SF opval = sh64_fiprs (current_cpu, FLD (f_left), FLD (f_right));
CPU (h_fr[FLD (f_dest)]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
}
@ -1239,18 +1280,12 @@ SEM_FN_NAME (sh64_media,fldp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI tmp_f;
tmp_f = FLD (f_dest);
{
SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)));
CPU (h_fr[tmp_f]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
}
{
SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)));
CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
SF opval = GET_H_FP (FLD (f_dest));
SET_H_FP (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval);
}
sh64_fldp (current_cpu, pc, GET_H_GR (FLD (f_left)), FLD (f_disp10x8), FLD (f_dest));
}
return vpc;
@ -1311,18 +1346,12 @@ SEM_FN_NAME (sh64_media,fldxp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI tmp_f;
tmp_f = FLD (f_dest);
{
SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
CPU (h_fr[tmp_f]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
}
{
SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)));
CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
SF opval = GET_H_FP (FLD (f_dest));
SET_H_FP (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval);
}
sh64_fldp (current_cpu, pc, GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)), FLD (f_dest));
}
return vpc;
@ -1670,13 +1699,17 @@ SEM_FN_NAME (sh64_media,fnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,fputscr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_fabsd.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
((void) 0); /*nop*/
{
SI opval = SUBWORDSFSI (CPU (h_fr[FLD (f_left_right)]));
CPU (h_fpscr) = opval;
TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval);
}
return vpc;
#undef FLD
@ -1757,18 +1790,12 @@ SEM_FN_NAME (sh64_media,fstp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI tmp_f;
tmp_f = FLD (f_dest);
{
SF opval = CPU (h_fr[tmp_f]);
SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
}
{
SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
SF opval = GET_H_FP (FLD (f_dest));
SET_H_FP (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval);
}
sh64_fstp (current_cpu, pc, GET_H_GR (FLD (f_left)), FLD (f_disp10x8), FLD (f_dest));
}
return vpc;
@ -1829,18 +1856,12 @@ SEM_FN_NAME (sh64_media,fstxp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI tmp_f;
tmp_f = FLD (f_dest);
{
SF opval = CPU (h_fr[tmp_f]);
SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
}
{
SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
SF opval = GET_H_FP (FLD (f_dest));
SET_H_FP (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval);
}
sh64_fstp (current_cpu, pc, GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)), FLD (f_dest));
}
return vpc;
@ -2005,7 +2026,24 @@ SEM_FN_NAME (sh64_media,ftrvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
SF opval = GET_H_FMTX (FLD (f_left));
SET_H_FMTX (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "fmtx", 'f', opval);
}
{
SF opval = GET_H_FV (FLD (f_right));
SET_H_FV (FLD (f_right), opval);
TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval);
}
{
SF opval = GET_H_FV (FLD (f_dest));
SET_H_FV (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval);
}
sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest));
}
return vpc;
#undef FLD
@ -2016,13 +2054,22 @@ sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest));
static SEM_PC
SEM_FN_NAME (sh64_media,getcfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI tmp_address;
tmp_address = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
((void) 0); /*nop*/
{
DI opval = GETMEMSI (current_cpu, pc, tmp_address);
SET_H_GR (FLD (f_dest), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
}
return vpc;
#undef FLD
@ -2075,13 +2122,20 @@ SEM_FN_NAME (sh64_media,gettr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,icbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
return vpc;
#undef FLD
@ -2218,7 +2272,7 @@ SEM_FN_NAME (sh64_media,ldw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,ldhil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
@ -2283,7 +2337,7 @@ if (ANDQI (tmp_bytecount, 2)) {
static SEM_PC
SEM_FN_NAME (sh64_media,ldhiq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
@ -2354,7 +2408,7 @@ if (ANDQI (tmp_bytecount, 4)) {
static SEM_PC
SEM_FN_NAME (sh64_media,ldlol) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
@ -2419,7 +2473,7 @@ if (ANDQI (tmp_bytecount, 1)) {
static SEM_PC
SEM_FN_NAME (sh64_media,ldloq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
@ -4458,13 +4512,20 @@ SEM_FN_NAME (sh64_media,nsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,ocbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
return vpc;
#undef FLD
@ -4475,13 +4536,20 @@ SEM_FN_NAME (sh64_media,ocbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,ocbp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
return vpc;
#undef FLD
@ -4492,13 +4560,20 @@ SEM_FN_NAME (sh64_media,ocbp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,ocbwb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
return vpc;
#undef FLD
@ -4551,13 +4626,20 @@ SEM_FN_NAME (sh64_media,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,prefi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_xori.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
DI opval = GET_H_GR (FLD (f_left));
SET_H_GR (FLD (f_left), opval);
TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
}
((void) 0); /*nop*/
}
return vpc;
#undef FLD
@ -4574,11 +4656,14 @@ SEM_FN_NAME (sh64_media,pta) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
{
DI opval = ADDSI (FLD (f_disp16), 1);
CPU (h_tr[FLD (f_tra)]) = opval;
TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
}
}
return vpc;
#undef FLD
@ -4595,11 +4680,14 @@ SEM_FN_NAME (sh64_media,ptabs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
{
DI opval = GET_H_GR (FLD (f_right));
CPU (h_tr[FLD (f_tra)]) = opval;
TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
}
}
return vpc;
#undef FLD
@ -4616,11 +4704,14 @@ SEM_FN_NAME (sh64_media,ptb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
{
DI opval = FLD (f_disp16);
CPU (h_tr[FLD (f_tra)]) = opval;
TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
}
}
return vpc;
#undef FLD
@ -4637,11 +4728,14 @@ SEM_FN_NAME (sh64_media,ptrel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
((void) 0); /*nop*/
{
DI opval = ADDDI (pc, GET_H_GR (FLD (f_right)));
CPU (h_tr[FLD (f_tra)]) = opval;
TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
}
}
return vpc;
#undef FLD
@ -4652,13 +4746,22 @@ SEM_FN_NAME (sh64_media,ptrel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,putcfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI tmp_address;
tmp_address = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
((void) 0); /*nop*/
{
SI opval = GET_H_GR (FLD (f_dest));
SETMEMSI (current_cpu, pc, tmp_address, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
return vpc;
#undef FLD
@ -5081,7 +5184,7 @@ SEM_FN_NAME (sh64_media,stw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (sh64_media,sthil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
@ -5167,7 +5270,7 @@ if (ANDQI (tmp_bytecount, 1)) {
static SEM_PC
SEM_FN_NAME (sh64_media,sthiq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
@ -5275,7 +5378,7 @@ if (ANDQI (tmp_bytecount, 1)) {
static SEM_PC
SEM_FN_NAME (sh64_media,stlol) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
@ -5361,7 +5464,7 @@ if (ANDQI (tmp_bytecount, 2)) {
static SEM_PC
SEM_FN_NAME (sh64_media,stloq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_ldhil.f
#define FLD(f) abuf->fields.sfmt_getcfg.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;

2428
sim/sh64/sh-desc.c
View File

File diff suppressed because it is too large Load Diff

165
sim/sh64/sh-desc.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@ -18,13 +18,15 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef SH_CPU_H
#define SH_CPU_H
#include "opcode/cgen-bitset.h"
#define CGEN_ARCH sh
/* Given symbol S, return sh_cgen_<S>. */
@ -38,7 +40,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Selected cpu families. */
#define HAVE_CPU_SH64
#define CGEN_INSN_LSB0_P 1
#define CGEN_INSN_LSB0_P 0
/* Minimum size of any insn (in bytes). */
#define CGEN_MIN_INSN_SIZE 2
@ -48,8 +50,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define CGEN_INT_INSN_P 1
/* Maximum nymber of syntax bytes in an instruction. */
#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 22
/* Maximum number of syntax elements in an instruction. */
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
@ -87,8 +89,10 @@ typedef enum xf_names {
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
MACH_BASE, MACH_SH2, MACH_SH3, MACH_SH3E
, MACH_SH4, MACH_SH5, MACH_MAX
MACH_BASE, MACH_SH2, MACH_SH2E, MACH_SH2A_FPU
, MACH_SH2A_NOFPU, MACH_SH3, MACH_SH3E, MACH_SH4_NOFPU
, MACH_SH4, MACH_SH4A_NOFPU, MACH_SH4A, MACH_SH4AL
, MACH_SH5, MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
@ -96,10 +100,24 @@ typedef enum isa_attr {
ISA_COMPACT, ISA_MEDIA, ISA_MAX
} ISA_ATTR;
/* Enum declaration for sh4 insn groups. */
typedef enum sh4_group_attr {
SH4_GROUP_NONE, SH4_GROUP_MT, SH4_GROUP_EX, SH4_GROUP_BR
, SH4_GROUP_LS, SH4_GROUP_FE, SH4_GROUP_CO, SH4_GROUP_MAX
} SH4_GROUP_ATTR;
/* Enum declaration for sh4a insn groups. */
typedef enum sh4a_group_attr {
SH4A_GROUP_NONE, SH4A_GROUP_MT, SH4A_GROUP_EX, SH4A_GROUP_BR
, SH4A_GROUP_LS, SH4A_GROUP_FE, SH4A_GROUP_CO, SH4A_GROUP_MAX
} SH4A_GROUP_ATTR;
/* Number of architecture variants. */
#define MAX_ISAS ((int) ISA_MAX)
#define MAX_MACHS ((int) MACH_MAX)
/* Ifield support. */
/* Ifield attribute indices. */
/* Enum declaration for cgen_ifld attrs. */
@ -112,21 +130,33 @@ typedef enum cgen_ifld_attr {
/* Number of non-boolean elements in cgen_ifld_attr. */
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
/* cgen_ifld attribute accessor macros. */
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
/* Enum declaration for sh ifield types. */
typedef enum ifield_type {
SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8
, SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10
, SH_F_RN, SH_F_RM, SH_F_8_1, SH_F_DISP8
, SH_F_DISP12, SH_F_IMM8, SH_F_IMM4, SH_F_IMM4X2
, SH_F_IMM4X4, SH_F_IMM8X2, SH_F_IMM8X4, SH_F_DN
, SH_F_RN, SH_F_RM, SH_F_7_1, SH_F_11_1
, SH_F_16_4, SH_F_DISP8, SH_F_DISP12, SH_F_IMM8
, SH_F_IMM4, SH_F_IMM4X2, SH_F_IMM4X4, SH_F_IMM8X2
, SH_F_IMM8X4, SH_F_IMM12X4, SH_F_IMM12X8, SH_F_DN
, SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN
, SH_F_XM, SH_F_OP, SH_F_EXT, SH_F_RSVD
, SH_F_LEFT, SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT
, SH_F_TRA, SH_F_TRB, SH_F_LIKELY, SH_F_25
, SH_F_8_2, SH_F_IMM6, SH_F_IMM10, SH_F_IMM16
, SH_F_UIMM6, SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32
, SH_F_DISP10, SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2
, SH_F_DISP16, SH_F_MAX
, SH_F_XM, SH_F_IMM20_HI, SH_F_IMM20_LO, SH_F_IMM20
, SH_F_OP, SH_F_EXT, SH_F_RSVD, SH_F_LEFT
, SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT, SH_F_TRA
, SH_F_TRB, SH_F_LIKELY, SH_F_6_3, SH_F_23_2
, SH_F_IMM6, SH_F_IMM10, SH_F_IMM16, SH_F_UIMM6
, SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32, SH_F_DISP10
, SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2, SH_F_DISP16
, SH_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) SH_F_MAX)
@ -136,12 +166,21 @@ typedef enum ifield_type {
/* Enum declaration for cgen_hw attrs. */
typedef enum cgen_hw_attr {
CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA
, CGEN_HW_END_NBOOLS
} CGEN_HW_ATTR;
/* Number of non-boolean elements in cgen_hw_attr. */
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
/* cgen_hw attribute accessor macros. */
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
/* Enum declaration for sh hardware types. */
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
@ -149,11 +188,11 @@ typedef enum cgen_hw_type {
, HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT
, HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT
, HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV
, HW_H_FMTX, HW_H_DR, HW_H_TR, HW_H_ENDIAN
, HW_H_ISM, HW_H_FRC, HW_H_DRC, HW_H_XF
, HW_H_XD, HW_H_FVC, HW_H_FPCCR, HW_H_GBR
, HW_H_PR, HW_H_MACL, HW_H_MACH, HW_H_TBIT
, HW_MAX
, HW_H_FMTX, HW_H_DR, HW_H_FSD, HW_H_FMOV
, HW_H_TR, HW_H_ENDIAN, HW_H_ISM, HW_H_FRC
, HW_H_DRC, HW_H_XF, HW_H_XD, HW_H_FVC
, HW_H_GBR, HW_H_VBR, HW_H_PR, HW_H_MACL
, HW_H_MACH, HW_H_TBIT, HW_MAX
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
@ -171,30 +210,44 @@ typedef enum cgen_operand_attr {
/* Number of non-boolean elements in cgen_operand_attr. */
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
/* cgen_operand attribute accessor macros. */
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
/* Enum declaration for sh operand types. */
typedef enum cgen_operand_type {
SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM
, SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM
, SH_OPERAND_FVN, SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM
, SH_OPERAND_IMM4, SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM4X2
, SH_OPERAND_FR0, SH_OPERAND_FMOVN, SH_OPERAND_FMOVM, SH_OPERAND_FVN
, SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM, SH_OPERAND_IMM4
, SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM20, SH_OPERAND_IMM4X2
, SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8
, SH_OPERAND_DISP12, SH_OPERAND_RM64, SH_OPERAND_RN64, SH_OPERAND_GBR
, SH_OPERAND_PR, SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT
, SH_OPERAND_MBIT, SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT
, SH_OPERAND_SZBIT, SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH
, SH_OPERAND_FSDM, SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG
, SH_OPERAND_FRH, SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF
, SH_OPERAND_FVG, SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG
, SH_OPERAND_DRG, SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH
, SH_OPERAND_CRJ, SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB
, SH_OPERAND_DISP6, SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2
, SH_OPERAND_DISP10X4, SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6
, SH_OPERAND_IMM10, SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16
, SH_OPERAND_LIKELY, SH_OPERAND_MAX
, SH_OPERAND_DISP12, SH_OPERAND_IMM12X4, SH_OPERAND_IMM12X8, SH_OPERAND_RM64
, SH_OPERAND_RN64, SH_OPERAND_GBR, SH_OPERAND_VBR, SH_OPERAND_PR
, SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT, SH_OPERAND_MBIT
, SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT, SH_OPERAND_SZBIT
, SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH, SH_OPERAND_FSDM
, SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG, SH_OPERAND_FRH
, SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF, SH_OPERAND_FVG
, SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG, SH_OPERAND_DRG
, SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH, SH_OPERAND_CRJ
, SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB, SH_OPERAND_DISP6
, SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2, SH_OPERAND_DISP10X4
, SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6, SH_OPERAND_IMM10
, SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16, SH_OPERAND_LIKELY
, SH_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
#define MAX_OPERANDS 72
#define MAX_OPERANDS 79
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
@ -204,18 +257,39 @@ typedef enum cgen_operand_type {
/* Enum declaration for cgen_insn attrs. */
typedef enum cgen_insn_attr {
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN
, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
, CGEN_INSN_END_NBOOLS
, CGEN_INSN_32_BIT_INSN, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
, CGEN_INSN_ISA, CGEN_INSN_SH4_GROUP, CGEN_INSN_SH4A_GROUP, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
/* cgen_insn attribute accessor macros. */
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_INSN_SH4_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_SH4A_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4A_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
#define CGEN_ATTR_CGEN_INSN_ILLSLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ILLSLOT)) != 0)
#define CGEN_ATTR_CGEN_INSN_FP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FP_INSN)) != 0)
#define CGEN_ATTR_CGEN_INSN_32_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_32_BIT_INSN)) != 0)
/* cgen.h uses things we just defined. */
#include "opcode/cgen.h"
extern const struct cgen_ifld sh_cgen_ifld_table[];
/* Attributes. */
extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[];
extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[];
@ -232,6 +306,8 @@ extern CGEN_KEYWORD sh_cgen_opval_h_fp;
extern CGEN_KEYWORD sh_cgen_opval_h_fv;
extern CGEN_KEYWORD sh_cgen_opval_h_fmtx;
extern CGEN_KEYWORD sh_cgen_opval_h_dr;
extern CGEN_KEYWORD sh_cgen_opval_h_fsd;
extern CGEN_KEYWORD sh_cgen_opval_h_fmov;
extern CGEN_KEYWORD sh_cgen_opval_h_tr;
extern CGEN_KEYWORD sh_cgen_opval_frc_names;
extern CGEN_KEYWORD sh_cgen_opval_drc_names;
@ -239,10 +315,7 @@ extern CGEN_KEYWORD sh_cgen_opval_xf_names;
extern CGEN_KEYWORD sh_cgen_opval_frc_names;
extern CGEN_KEYWORD sh_cgen_opval_h_fvc;
/* Ifield support. */
extern const struct cgen_ifld sh_cgen_ifld_table[];
extern const CGEN_HW_ENTRY sh_cgen_hw_table[];

201
sim/sh64/sh-opc.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996-2005 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@ -18,24 +18,13 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef SH_OPC_H
#define SH_OPC_H
/* -- opc.h */
/* Allows reason codes to be output when assembler errors occur. */
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
/* Override disassembly hashing - there are variable bits in the top
byte of these instructions. */
#define CGEN_DIS_HASH_SIZE 8
#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
/* -- asm.c */
/* Enum declaration for sh instruction types. */
typedef enum cgen_insn_type {
SH_INSN_INVALID, SH_INSN_ADD_COMPACT, SH_INSN_ADDI_COMPACT, SH_INSN_ADDC_COMPACT
@ -46,103 +35,106 @@ typedef enum cgen_insn_type {
, SH_INSN_CMPEQ_COMPACT, SH_INSN_CMPEQI_COMPACT, SH_INSN_CMPGE_COMPACT, SH_INSN_CMPGT_COMPACT
, SH_INSN_CMPHI_COMPACT, SH_INSN_CMPHS_COMPACT, SH_INSN_CMPPL_COMPACT, SH_INSN_CMPPZ_COMPACT
, SH_INSN_CMPSTR_COMPACT, SH_INSN_DIV0S_COMPACT, SH_INSN_DIV0U_COMPACT, SH_INSN_DIV1_COMPACT
, SH_INSN_DMULSL_COMPACT, SH_INSN_DMULUL_COMPACT, SH_INSN_DT_COMPACT, SH_INSN_EXTSB_COMPACT
, SH_INSN_EXTSW_COMPACT, SH_INSN_EXTUB_COMPACT, SH_INSN_EXTUW_COMPACT, SH_INSN_FABS_COMPACT
, SH_INSN_FADD_COMPACT, SH_INSN_FCMPEQ_COMPACT, SH_INSN_FCMPGT_COMPACT, SH_INSN_FCNVDS_COMPACT
, SH_INSN_FCNVSD_COMPACT, SH_INSN_FDIV_COMPACT, SH_INSN_FIPR_COMPACT, SH_INSN_FLDS_COMPACT
, SH_INSN_FLDI0_COMPACT, SH_INSN_FLDI1_COMPACT, SH_INSN_FLOAT_COMPACT, SH_INSN_FMAC_COMPACT
, SH_INSN_FMOV1_COMPACT, SH_INSN_FMOV2_COMPACT, SH_INSN_FMOV3_COMPACT, SH_INSN_FMOV4_COMPACT
, SH_INSN_FMOV5_COMPACT, SH_INSN_FMOV6_COMPACT, SH_INSN_FMOV7_COMPACT, SH_INSN_FMUL_COMPACT
, SH_INSN_DIVU_COMPACT, SH_INSN_MULR_COMPACT, SH_INSN_DMULSL_COMPACT, SH_INSN_DMULUL_COMPACT
, SH_INSN_DT_COMPACT, SH_INSN_EXTSB_COMPACT, SH_INSN_EXTSW_COMPACT, SH_INSN_EXTUB_COMPACT
, SH_INSN_EXTUW_COMPACT, SH_INSN_FABS_COMPACT, SH_INSN_FADD_COMPACT, SH_INSN_FCMPEQ_COMPACT
, SH_INSN_FCMPGT_COMPACT, SH_INSN_FCNVDS_COMPACT, SH_INSN_FCNVSD_COMPACT, SH_INSN_FDIV_COMPACT
, SH_INSN_FIPR_COMPACT, SH_INSN_FLDS_COMPACT, SH_INSN_FLDI0_COMPACT, SH_INSN_FLDI1_COMPACT
, SH_INSN_FLOAT_COMPACT, SH_INSN_FMAC_COMPACT, SH_INSN_FMOV1_COMPACT, SH_INSN_FMOV2_COMPACT
, SH_INSN_FMOV3_COMPACT, SH_INSN_FMOV4_COMPACT, SH_INSN_FMOV5_COMPACT, SH_INSN_FMOV6_COMPACT
, SH_INSN_FMOV7_COMPACT, SH_INSN_FMOV8_COMPACT, SH_INSN_FMOV9_COMPACT, SH_INSN_FMUL_COMPACT
, SH_INSN_FNEG_COMPACT, SH_INSN_FRCHG_COMPACT, SH_INSN_FSCHG_COMPACT, SH_INSN_FSQRT_COMPACT
, SH_INSN_FSTS_COMPACT, SH_INSN_FSUB_COMPACT, SH_INSN_FTRC_COMPACT, SH_INSN_FTRV_COMPACT
, SH_INSN_JMP_COMPACT, SH_INSN_JSR_COMPACT, SH_INSN_LDC_COMPACT, SH_INSN_LDCL_COMPACT
, SH_INSN_LDS_FPSCR_COMPACT, SH_INSN_LDSL_FPSCR_COMPACT, SH_INSN_LDS_FPUL_COMPACT, SH_INSN_LDSL_FPUL_COMPACT
, SH_INSN_LDS_MACH_COMPACT, SH_INSN_LDSL_MACH_COMPACT, SH_INSN_LDS_MACL_COMPACT, SH_INSN_LDSL_MACL_COMPACT
, SH_INSN_LDS_PR_COMPACT, SH_INSN_LDSL_PR_COMPACT, SH_INSN_MACL_COMPACT, SH_INSN_MACW_COMPACT
, SH_INSN_MOV_COMPACT, SH_INSN_MOVI_COMPACT, SH_INSN_MOVB1_COMPACT, SH_INSN_MOVB2_COMPACT
, SH_INSN_JMP_COMPACT, SH_INSN_JSR_COMPACT, SH_INSN_LDC_GBR_COMPACT, SH_INSN_LDC_VBR_COMPACT
, SH_INSN_LDC_SR_COMPACT, SH_INSN_LDCL_GBR_COMPACT, SH_INSN_LDCL_VBR_COMPACT, SH_INSN_LDS_FPSCR_COMPACT
, SH_INSN_LDSL_FPSCR_COMPACT, SH_INSN_LDS_FPUL_COMPACT, SH_INSN_LDSL_FPUL_COMPACT, SH_INSN_LDS_MACH_COMPACT
, SH_INSN_LDSL_MACH_COMPACT, SH_INSN_LDS_MACL_COMPACT, SH_INSN_LDSL_MACL_COMPACT, SH_INSN_LDS_PR_COMPACT
, SH_INSN_LDSL_PR_COMPACT, SH_INSN_MACL_COMPACT, SH_INSN_MACW_COMPACT, SH_INSN_MOV_COMPACT
, SH_INSN_MOVI_COMPACT, SH_INSN_MOVI20_COMPACT, SH_INSN_MOVB1_COMPACT, SH_INSN_MOVB2_COMPACT
, SH_INSN_MOVB3_COMPACT, SH_INSN_MOVB4_COMPACT, SH_INSN_MOVB5_COMPACT, SH_INSN_MOVB6_COMPACT
, SH_INSN_MOVB7_COMPACT, SH_INSN_MOVB8_COMPACT, SH_INSN_MOVB9_COMPACT, SH_INSN_MOVB10_COMPACT
, SH_INSN_MOVL1_COMPACT, SH_INSN_MOVL2_COMPACT, SH_INSN_MOVL3_COMPACT, SH_INSN_MOVL4_COMPACT
, SH_INSN_MOVL5_COMPACT, SH_INSN_MOVL6_COMPACT, SH_INSN_MOVL7_COMPACT, SH_INSN_MOVL8_COMPACT
, SH_INSN_MOVL9_COMPACT, SH_INSN_MOVL10_COMPACT, SH_INSN_MOVL11_COMPACT, SH_INSN_MOVW1_COMPACT
, SH_INSN_MOVW2_COMPACT, SH_INSN_MOVW3_COMPACT, SH_INSN_MOVW4_COMPACT, SH_INSN_MOVW5_COMPACT
, SH_INSN_MOVW6_COMPACT, SH_INSN_MOVW7_COMPACT, SH_INSN_MOVW8_COMPACT, SH_INSN_MOVW9_COMPACT
, SH_INSN_MOVW10_COMPACT, SH_INSN_MOVW11_COMPACT, SH_INSN_MOVA_COMPACT, SH_INSN_MOVCAL_COMPACT
, SH_INSN_MOVT_COMPACT, SH_INSN_MULL_COMPACT, SH_INSN_MULSW_COMPACT, SH_INSN_MULUW_COMPACT
, SH_INSN_NEG_COMPACT, SH_INSN_NEGC_COMPACT, SH_INSN_NOP_COMPACT, SH_INSN_NOT_COMPACT
, SH_INSN_OCBI_COMPACT, SH_INSN_OCBP_COMPACT, SH_INSN_OCBWB_COMPACT, SH_INSN_OR_COMPACT
, SH_INSN_ORI_COMPACT, SH_INSN_ORB_COMPACT, SH_INSN_PREF_COMPACT, SH_INSN_ROTCL_COMPACT
, SH_INSN_ROTCR_COMPACT, SH_INSN_ROTL_COMPACT, SH_INSN_ROTR_COMPACT, SH_INSN_RTS_COMPACT
, SH_INSN_SETS_COMPACT, SH_INSN_SETT_COMPACT, SH_INSN_SHAD_COMPACT, SH_INSN_SHAL_COMPACT
, SH_INSN_SHAR_COMPACT, SH_INSN_SHLD_COMPACT, SH_INSN_SHLL_COMPACT, SH_INSN_SHLL2_COMPACT
, SH_INSN_SHLL8_COMPACT, SH_INSN_SHLL16_COMPACT, SH_INSN_SHLR_COMPACT, SH_INSN_SHLR2_COMPACT
, SH_INSN_SHLR8_COMPACT, SH_INSN_SHLR16_COMPACT, SH_INSN_STC_GBR_COMPACT, SH_INSN_STCL_GBR_COMPACT
, SH_INSN_STS_FPSCR_COMPACT, SH_INSN_STSL_FPSCR_COMPACT, SH_INSN_STS_FPUL_COMPACT, SH_INSN_STSL_FPUL_COMPACT
, SH_INSN_STS_MACH_COMPACT, SH_INSN_STSL_MACH_COMPACT, SH_INSN_STS_MACL_COMPACT, SH_INSN_STSL_MACL_COMPACT
, SH_INSN_STS_PR_COMPACT, SH_INSN_STSL_PR_COMPACT, SH_INSN_SUB_COMPACT, SH_INSN_SUBC_COMPACT
, SH_INSN_SUBV_COMPACT, SH_INSN_SWAPB_COMPACT, SH_INSN_SWAPW_COMPACT, SH_INSN_TASB_COMPACT
, SH_INSN_TRAPA_COMPACT, SH_INSN_TST_COMPACT, SH_INSN_TSTI_COMPACT, SH_INSN_TSTB_COMPACT
, SH_INSN_XOR_COMPACT, SH_INSN_XORI_COMPACT, SH_INSN_XORB_COMPACT, SH_INSN_XTRCT_COMPACT
, SH_INSN_ADD, SH_INSN_ADDL, SH_INSN_ADDI, SH_INSN_ADDIL
, SH_INSN_ADDZL, SH_INSN_ALLOCO, SH_INSN_AND, SH_INSN_ANDC
, SH_INSN_ANDI, SH_INSN_BEQ, SH_INSN_BEQI, SH_INSN_BGE
, SH_INSN_BGEU, SH_INSN_BGT, SH_INSN_BGTU, SH_INSN_BLINK
, SH_INSN_BNE, SH_INSN_BNEI, SH_INSN_BRK, SH_INSN_BYTEREV
, SH_INSN_CMPEQ, SH_INSN_CMPGT, SH_INSN_CMPGTU, SH_INSN_CMVEQ
, SH_INSN_CMVNE, SH_INSN_FABSD, SH_INSN_FABSS, SH_INSN_FADDD
, SH_INSN_FADDS, SH_INSN_FCMPEQD, SH_INSN_FCMPEQS, SH_INSN_FCMPGED
, SH_INSN_FCMPGES, SH_INSN_FCMPGTD, SH_INSN_FCMPGTS, SH_INSN_FCMPUND
, SH_INSN_FCMPUNS, SH_INSN_FCNVDS, SH_INSN_FCNVSD, SH_INSN_FDIVD
, SH_INSN_FDIVS, SH_INSN_FGETSCR, SH_INSN_FIPRS, SH_INSN_FLDD
, SH_INSN_FLDP, SH_INSN_FLDS, SH_INSN_FLDXD, SH_INSN_FLDXP
, SH_INSN_FLDXS, SH_INSN_FLOATLD, SH_INSN_FLOATLS, SH_INSN_FLOATQD
, SH_INSN_FLOATQS, SH_INSN_FMACS, SH_INSN_FMOVD, SH_INSN_FMOVDQ
, SH_INSN_FMOVLS, SH_INSN_FMOVQD, SH_INSN_FMOVS, SH_INSN_FMOVSL
, SH_INSN_FMULD, SH_INSN_FMULS, SH_INSN_FNEGD, SH_INSN_FNEGS
, SH_INSN_FPUTSCR, SH_INSN_FSQRTD, SH_INSN_FSQRTS, SH_INSN_FSTD
, SH_INSN_FSTP, SH_INSN_FSTS, SH_INSN_FSTXD, SH_INSN_FSTXP
, SH_INSN_FSTXS, SH_INSN_FSUBD, SH_INSN_FSUBS, SH_INSN_FTRCDL
, SH_INSN_FTRCSL, SH_INSN_FTRCDQ, SH_INSN_FTRCSQ, SH_INSN_FTRVS
, SH_INSN_GETCFG, SH_INSN_GETCON, SH_INSN_GETTR, SH_INSN_ICBI
, SH_INSN_LDB, SH_INSN_LDL, SH_INSN_LDQ, SH_INSN_LDUB
, SH_INSN_LDUW, SH_INSN_LDW, SH_INSN_LDHIL, SH_INSN_LDHIQ
, SH_INSN_LDLOL, SH_INSN_LDLOQ, SH_INSN_LDXB, SH_INSN_LDXL
, SH_INSN_LDXQ, SH_INSN_LDXUB, SH_INSN_LDXUW, SH_INSN_LDXW
, SH_INSN_MABSL, SH_INSN_MABSW, SH_INSN_MADDL, SH_INSN_MADDW
, SH_INSN_MADDSL, SH_INSN_MADDSUB, SH_INSN_MADDSW, SH_INSN_MCMPEQB
, SH_INSN_MCMPEQL, SH_INSN_MCMPEQW, SH_INSN_MCMPGTL, SH_INSN_MCMPGTUB
, SH_INSN_MCMPGTW, SH_INSN_MCMV, SH_INSN_MCNVSLW, SH_INSN_MCNVSWB
, SH_INSN_MCNVSWUB, SH_INSN_MEXTR1, SH_INSN_MEXTR2, SH_INSN_MEXTR3
, SH_INSN_MEXTR4, SH_INSN_MEXTR5, SH_INSN_MEXTR6, SH_INSN_MEXTR7
, SH_INSN_MMACFXWL, SH_INSN_MMACNFX_WL, SH_INSN_MMULL, SH_INSN_MMULW
, SH_INSN_MMULFXL, SH_INSN_MMULFXW, SH_INSN_MMULFXRPW, SH_INSN_MMULHIWL
, SH_INSN_MMULLOWL, SH_INSN_MMULSUMWQ, SH_INSN_MOVI, SH_INSN_MPERMW
, SH_INSN_MSADUBQ, SH_INSN_MSHALDSL, SH_INSN_MSHALDSW, SH_INSN_MSHARDL
, SH_INSN_MSHARDW, SH_INSN_MSHARDSQ, SH_INSN_MSHFHIB, SH_INSN_MSHFHIL
, SH_INSN_MSHFHIW, SH_INSN_MSHFLOB, SH_INSN_MSHFLOL, SH_INSN_MSHFLOW
, SH_INSN_MSHLLDL, SH_INSN_MSHLLDW, SH_INSN_MSHLRDL, SH_INSN_MSHLRDW
, SH_INSN_MSUBL, SH_INSN_MSUBW, SH_INSN_MSUBSL, SH_INSN_MSUBSUB
, SH_INSN_MSUBSW, SH_INSN_MULSL, SH_INSN_MULUL, SH_INSN_NOP
, SH_INSN_NSB, SH_INSN_OCBI, SH_INSN_OCBP, SH_INSN_OCBWB
, SH_INSN_OR, SH_INSN_ORI, SH_INSN_PREFI, SH_INSN_PTA
, SH_INSN_PTABS, SH_INSN_PTB, SH_INSN_PTREL, SH_INSN_PUTCFG
, SH_INSN_PUTCON, SH_INSN_RTE, SH_INSN_SHARD, SH_INSN_SHARDL
, SH_INSN_SHARI, SH_INSN_SHARIL, SH_INSN_SHLLD, SH_INSN_SHLLDL
, SH_INSN_SHLLI, SH_INSN_SHLLIL, SH_INSN_SHLRD, SH_INSN_SHLRDL
, SH_INSN_SHLRI, SH_INSN_SHLRIL, SH_INSN_SHORI, SH_INSN_SLEEP
, SH_INSN_STB, SH_INSN_STL, SH_INSN_STQ, SH_INSN_STW
, SH_INSN_STHIL, SH_INSN_STHIQ, SH_INSN_STLOL, SH_INSN_STLOQ
, SH_INSN_STXB, SH_INSN_STXL, SH_INSN_STXQ, SH_INSN_STXW
, SH_INSN_SUB, SH_INSN_SUBL, SH_INSN_SWAPQ, SH_INSN_SYNCI
, SH_INSN_SYNCO, SH_INSN_TRAPA, SH_INSN_XOR, SH_INSN_XORI
, SH_INSN_MAX
, SH_INSN_MOVL9_COMPACT, SH_INSN_MOVL10_COMPACT, SH_INSN_MOVL11_COMPACT, SH_INSN_MOVL12_COMPACT
, SH_INSN_MOVL13_COMPACT, SH_INSN_MOVW1_COMPACT, SH_INSN_MOVW2_COMPACT, SH_INSN_MOVW3_COMPACT
, SH_INSN_MOVW4_COMPACT, SH_INSN_MOVW5_COMPACT, SH_INSN_MOVW6_COMPACT, SH_INSN_MOVW7_COMPACT
, SH_INSN_MOVW8_COMPACT, SH_INSN_MOVW9_COMPACT, SH_INSN_MOVW10_COMPACT, SH_INSN_MOVW11_COMPACT
, SH_INSN_MOVA_COMPACT, SH_INSN_MOVCAL_COMPACT, SH_INSN_MOVCOL_COMPACT, SH_INSN_MOVT_COMPACT
, SH_INSN_MOVUAL_COMPACT, SH_INSN_MOVUAL2_COMPACT, SH_INSN_MULL_COMPACT, SH_INSN_MULSW_COMPACT
, SH_INSN_MULUW_COMPACT, SH_INSN_NEG_COMPACT, SH_INSN_NEGC_COMPACT, SH_INSN_NOP_COMPACT
, SH_INSN_NOT_COMPACT, SH_INSN_OCBI_COMPACT, SH_INSN_OCBP_COMPACT, SH_INSN_OCBWB_COMPACT
, SH_INSN_OR_COMPACT, SH_INSN_ORI_COMPACT, SH_INSN_ORB_COMPACT, SH_INSN_PREF_COMPACT
, SH_INSN_ROTCL_COMPACT, SH_INSN_ROTCR_COMPACT, SH_INSN_ROTL_COMPACT, SH_INSN_ROTR_COMPACT
, SH_INSN_RTS_COMPACT, SH_INSN_SETS_COMPACT, SH_INSN_SETT_COMPACT, SH_INSN_SHAD_COMPACT
, SH_INSN_SHAL_COMPACT, SH_INSN_SHAR_COMPACT, SH_INSN_SHLD_COMPACT, SH_INSN_SHLL_COMPACT
, SH_INSN_SHLL2_COMPACT, SH_INSN_SHLL8_COMPACT, SH_INSN_SHLL16_COMPACT, SH_INSN_SHLR_COMPACT
, SH_INSN_SHLR2_COMPACT, SH_INSN_SHLR8_COMPACT, SH_INSN_SHLR16_COMPACT, SH_INSN_STC_GBR_COMPACT
, SH_INSN_STC_VBR_COMPACT, SH_INSN_STCL_GBR_COMPACT, SH_INSN_STCL_VBR_COMPACT, SH_INSN_STS_FPSCR_COMPACT
, SH_INSN_STSL_FPSCR_COMPACT, SH_INSN_STS_FPUL_COMPACT, SH_INSN_STSL_FPUL_COMPACT, SH_INSN_STS_MACH_COMPACT
, SH_INSN_STSL_MACH_COMPACT, SH_INSN_STS_MACL_COMPACT, SH_INSN_STSL_MACL_COMPACT, SH_INSN_STS_PR_COMPACT
, SH_INSN_STSL_PR_COMPACT, SH_INSN_SUB_COMPACT, SH_INSN_SUBC_COMPACT, SH_INSN_SUBV_COMPACT
, SH_INSN_SWAPB_COMPACT, SH_INSN_SWAPW_COMPACT, SH_INSN_TASB_COMPACT, SH_INSN_TRAPA_COMPACT
, SH_INSN_TST_COMPACT, SH_INSN_TSTI_COMPACT, SH_INSN_TSTB_COMPACT, SH_INSN_XOR_COMPACT
, SH_INSN_XORI_COMPACT, SH_INSN_XORB_COMPACT, SH_INSN_XTRCT_COMPACT, SH_INSN_ADD
, SH_INSN_ADDL, SH_INSN_ADDI, SH_INSN_ADDIL, SH_INSN_ADDZL
, SH_INSN_ALLOCO, SH_INSN_AND, SH_INSN_ANDC, SH_INSN_ANDI
, SH_INSN_BEQ, SH_INSN_BEQI, SH_INSN_BGE, SH_INSN_BGEU
, SH_INSN_BGT, SH_INSN_BGTU, SH_INSN_BLINK, SH_INSN_BNE
, SH_INSN_BNEI, SH_INSN_BRK, SH_INSN_BYTEREV, SH_INSN_CMPEQ
, SH_INSN_CMPGT, SH_INSN_CMPGTU, SH_INSN_CMVEQ, SH_INSN_CMVNE
, SH_INSN_FABSD, SH_INSN_FABSS, SH_INSN_FADDD, SH_INSN_FADDS
, SH_INSN_FCMPEQD, SH_INSN_FCMPEQS, SH_INSN_FCMPGED, SH_INSN_FCMPGES
, SH_INSN_FCMPGTD, SH_INSN_FCMPGTS, SH_INSN_FCMPUND, SH_INSN_FCMPUNS
, SH_INSN_FCNVDS, SH_INSN_FCNVSD, SH_INSN_FDIVD, SH_INSN_FDIVS
, SH_INSN_FGETSCR, SH_INSN_FIPRS, SH_INSN_FLDD, SH_INSN_FLDP
, SH_INSN_FLDS, SH_INSN_FLDXD, SH_INSN_FLDXP, SH_INSN_FLDXS
, SH_INSN_FLOATLD, SH_INSN_FLOATLS, SH_INSN_FLOATQD, SH_INSN_FLOATQS
, SH_INSN_FMACS, SH_INSN_FMOVD, SH_INSN_FMOVDQ, SH_INSN_FMOVLS
, SH_INSN_FMOVQD, SH_INSN_FMOVS, SH_INSN_FMOVSL, SH_INSN_FMULD
, SH_INSN_FMULS, SH_INSN_FNEGD, SH_INSN_FNEGS, SH_INSN_FPUTSCR
, SH_INSN_FSQRTD, SH_INSN_FSQRTS, SH_INSN_FSTD, SH_INSN_FSTP
, SH_INSN_FSTS, SH_INSN_FSTXD, SH_INSN_FSTXP, SH_INSN_FSTXS
, SH_INSN_FSUBD, SH_INSN_FSUBS, SH_INSN_FTRCDL, SH_INSN_FTRCSL
, SH_INSN_FTRCDQ, SH_INSN_FTRCSQ, SH_INSN_FTRVS, SH_INSN_GETCFG
, SH_INSN_GETCON, SH_INSN_GETTR, SH_INSN_ICBI, SH_INSN_LDB
, SH_INSN_LDL, SH_INSN_LDQ, SH_INSN_LDUB, SH_INSN_LDUW
, SH_INSN_LDW, SH_INSN_LDHIL, SH_INSN_LDHIQ, SH_INSN_LDLOL
, SH_INSN_LDLOQ, SH_INSN_LDXB, SH_INSN_LDXL, SH_INSN_LDXQ
, SH_INSN_LDXUB, SH_INSN_LDXUW, SH_INSN_LDXW, SH_INSN_MABSL
, SH_INSN_MABSW, SH_INSN_MADDL, SH_INSN_MADDW, SH_INSN_MADDSL
, SH_INSN_MADDSUB, SH_INSN_MADDSW, SH_INSN_MCMPEQB, SH_INSN_MCMPEQL
, SH_INSN_MCMPEQW, SH_INSN_MCMPGTL, SH_INSN_MCMPGTUB, SH_INSN_MCMPGTW
, SH_INSN_MCMV, SH_INSN_MCNVSLW, SH_INSN_MCNVSWB, SH_INSN_MCNVSWUB
, SH_INSN_MEXTR1, SH_INSN_MEXTR2, SH_INSN_MEXTR3, SH_INSN_MEXTR4
, SH_INSN_MEXTR5, SH_INSN_MEXTR6, SH_INSN_MEXTR7, SH_INSN_MMACFXWL
, SH_INSN_MMACNFX_WL, SH_INSN_MMULL, SH_INSN_MMULW, SH_INSN_MMULFXL
, SH_INSN_MMULFXW, SH_INSN_MMULFXRPW, SH_INSN_MMULHIWL, SH_INSN_MMULLOWL
, SH_INSN_MMULSUMWQ, SH_INSN_MOVI, SH_INSN_MPERMW, SH_INSN_MSADUBQ
, SH_INSN_MSHALDSL, SH_INSN_MSHALDSW, SH_INSN_MSHARDL, SH_INSN_MSHARDW
, SH_INSN_MSHARDSQ, SH_INSN_MSHFHIB, SH_INSN_MSHFHIL, SH_INSN_MSHFHIW
, SH_INSN_MSHFLOB, SH_INSN_MSHFLOL, SH_INSN_MSHFLOW, SH_INSN_MSHLLDL
, SH_INSN_MSHLLDW, SH_INSN_MSHLRDL, SH_INSN_MSHLRDW, SH_INSN_MSUBL
, SH_INSN_MSUBW, SH_INSN_MSUBSL, SH_INSN_MSUBSUB, SH_INSN_MSUBSW
, SH_INSN_MULSL, SH_INSN_MULUL, SH_INSN_NOP, SH_INSN_NSB
, SH_INSN_OCBI, SH_INSN_OCBP, SH_INSN_OCBWB, SH_INSN_OR
, SH_INSN_ORI, SH_INSN_PREFI, SH_INSN_PTA, SH_INSN_PTABS
, SH_INSN_PTB, SH_INSN_PTREL, SH_INSN_PUTCFG, SH_INSN_PUTCON
, SH_INSN_RTE, SH_INSN_SHARD, SH_INSN_SHARDL, SH_INSN_SHARI
, SH_INSN_SHARIL, SH_INSN_SHLLD, SH_INSN_SHLLDL, SH_INSN_SHLLI
, SH_INSN_SHLLIL, SH_INSN_SHLRD, SH_INSN_SHLRDL, SH_INSN_SHLRI
, SH_INSN_SHLRIL, SH_INSN_SHORI, SH_INSN_SLEEP, SH_INSN_STB
, SH_INSN_STL, SH_INSN_STQ, SH_INSN_STW, SH_INSN_STHIL
, SH_INSN_STHIQ, SH_INSN_STLOL, SH_INSN_STLOQ, SH_INSN_STXB
, SH_INSN_STXL, SH_INSN_STXQ, SH_INSN_STXW, SH_INSN_SUB
, SH_INSN_SUBL, SH_INSN_SWAPQ, SH_INSN_SYNCI, SH_INSN_SYNCO
, SH_INSN_TRAPA, SH_INSN_XOR, SH_INSN_XORI
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID SH_INSN_INVALID
/* Total number of insns in table. */
#define MAX_INSNS ((int) SH_INSN_MAX)
#define MAX_INSNS ((int) SH_INSN_XORI + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
@ -158,7 +150,9 @@ struct cgen_fields
long f_sub10;
long f_rn;
long f_rm;
long f_8_1;
long f_7_1;
long f_11_1;
long f_16_4;
long f_disp8;
long f_disp12;
long f_imm8;
@ -167,12 +161,17 @@ struct cgen_fields
long f_imm4x4;
long f_imm8x2;
long f_imm8x4;
long f_imm12x4;
long f_imm12x8;
long f_dn;
long f_dm;
long f_vn;
long f_vm;
long f_xn;
long f_xm;
long f_imm20_hi;
long f_imm20_lo;
long f_imm20;
long f_op;
long f_ext;
long f_rsvd;
@ -183,8 +182,8 @@ struct cgen_fields
long f_tra;
long f_trb;
long f_likely;
long f_25;
long f_8_2;
long f_6_3;
long f_23_2;
long f_imm6;
long f_imm10;
long f_imm16;

10
sim/sh64/sh64-sim.h
View File

@ -1,5 +1,5 @@
/* collection of junk waiting time to sort out
Copyright (C) 2000 Free Software Foundation, Inc.
Copyright (C) 2000, 2006 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of the GNU Simulators.
@ -42,6 +42,7 @@ extern IDESC * sh64_idesc_compact;
BI sh64_endian (SIM_CPU *);
VOID sh64_break (SIM_CPU *, PCADDR);
SI sh64_movua (SIM_CPU *, PCADDR, SI);
VOID sh64_trapa (SIM_CPU *, DI, PCADDR);
VOID sh64_compact_trapa (SIM_CPU *, UQI, PCADDR);
@ -74,7 +75,12 @@ DF sh64_ftrcdq (SIM_CPU *, DF);
SF sh64_ftrcsl (SIM_CPU *, SF);
DF sh64_ftrcsq (SIM_CPU *, SF);
VOID sh64_ftrvs (SIM_CPU *, unsigned, unsigned, unsigned);
VOID sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n);
SF sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h);
VOID sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f);
VOID sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f);
VOID sh64_ftrv (SIM_CPU *cpu, UINT ignored);
VOID sh64_pref (SIM_CPU *cpu, SI addr);
BI sh64_fcmpeqs (SIM_CPU *, SF, SF);
BI sh64_fcmpeqd (SIM_CPU *, DF, DF);
BI sh64_fcmpges (SIM_CPU *, SF, SF);

147
sim/sh64/sh64.c
View File

@ -1,5 +1,5 @@
/* SH5 simulator support code
Copyright (C) 2000, 2001 Free Software Foundation, Inc.
Copyright (C) 2000, 2001, 2006 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of the GNU simulators.
@ -460,7 +460,7 @@ sh64_ftrcsq(SIM_CPU *current_cpu, SF frgh)
return (DF) result;
}
void
VOID
sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f)
{
int i, j;
@ -484,6 +484,52 @@ sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f)
}
}
VOID
sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n)
{
SF result = sh64_fmuls (cpu, sh64_h_fvc_get (cpu, m), sh64_h_fvc_get (cpu, n));
result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 1), sh64_h_frc_get (cpu, n + 1)));
result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 2), sh64_h_frc_get (cpu, n + 2)));
result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 3), sh64_h_frc_get (cpu, n + 3)));
sh64_h_frc_set (cpu, n + 3, result);
}
SF
sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h)
{
SF temp = sh64_fmuls (cpu, sh64_h_fr_get (cpu, g), sh64_h_fr_get (cpu, h));
temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 1), sh64_h_fr_get (cpu, h + 1)));
temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 2), sh64_h_fr_get (cpu, h + 2)));
temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 3), sh64_h_fr_get (cpu, h + 3)));
return temp;
}
VOID
sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f)
{
sh64_h_fr_set (cpu, f, GETMEMSF (cpu, pc, rm + rn));
sh64_h_fr_set (cpu, f + 1, GETMEMSF (cpu, pc, rm + rn + 4));
}
VOID
sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f)
{
SETMEMSF (cpu, pc, rm + rn, sh64_h_fr_get (cpu, f));
SETMEMSF (cpu, pc, rm + rn + 4, sh64_h_fr_get (cpu, f + 1));
}
VOID
sh64_ftrv (SIM_CPU *cpu, UINT ignored)
{
/* TODO: Unimplemented. */
}
VOID
sh64_pref (SIM_CPU *cpu, SI addr)
{
/* TODO: Unimplemented. */
}
/* Count the number of arguments. */
static int
count_argc (cpu)
@ -688,6 +734,22 @@ sh64_break (SIM_CPU *current_cpu, PCADDR pc)
sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
}
SI
sh64_movua (SIM_CPU *current_cpu, PCADDR pc, SI rn)
{
SI v;
int i;
/* Move the data one byte at a time to avoid alignment problems.
Be aware of endianness. */
v = 0;
for (i = 0; i < 4; ++i)
v = (v << 8) | (GETMEMQI (current_cpu, pc, rn + i) & 0xff);
v = T2H_4 (v);
return v;
}
void
set_isa (SIM_CPU *current_cpu, int mode)
{
@ -971,11 +1033,18 @@ sh64_model_init()
static const MODEL sh_models [] =
{
{ "sh2", & sh2_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh3", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh3e", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh4", & sh4_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh5", & sh5_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh2", & sh2_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh2e", & sh2e_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh2a", & sh2a_fpu_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh2a_nofpu", & sh2a_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh3", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh3e", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh4", & sh4_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh4_nofpu", & sh4_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh4a", & sh4a_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh4a_nofpu", & sh4a_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh4al", & sh4al_mach, MODEL_SH5, NULL, sh64_model_init },
{ "sh5", & sh5_mach, MODEL_SH5, NULL, sh64_model_init },
{ 0 }
};
@ -997,10 +1066,34 @@ const MACH sh2_mach =
sh64_prepare_run
};
const MACH sh2e_mach =
{
"sh2e", "sh2e", MACH_SH5,
16, 16, &sh_models[1], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
const MACH sh2a_fpu_mach =
{
"sh2a", "sh2a", MACH_SH5,
16, 16, &sh_models[2], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
const MACH sh2a_nofpu_mach =
{
"sh2a_nofpu", "sh2a_nofpu", MACH_SH5,
16, 16, &sh_models[3], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
const MACH sh3_mach =
{
"sh3", "sh3", MACH_SH5,
16, 16, &sh_models[1], &sh5_imp_properties,
16, 16, &sh_models[4], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
@ -1008,7 +1101,7 @@ const MACH sh3_mach =
const MACH sh3e_mach =
{
"sh3e", "sh3e", MACH_SH5,
16, 16, &sh_models[2], &sh5_imp_properties,
16, 16, &sh_models[5], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
@ -1016,7 +1109,39 @@ const MACH sh3e_mach =
const MACH sh4_mach =
{
"sh4", "sh4", MACH_SH5,
16, 16, &sh_models[3], &sh5_imp_properties,
16, 16, &sh_models[6], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
const MACH sh4_nofpu_mach =
{
"sh4_nofpu", "sh4_nofpu", MACH_SH5,
16, 16, &sh_models[7], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
const MACH sh4a_mach =
{
"sh4a", "sh4a", MACH_SH5,
16, 16, &sh_models[8], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
const MACH sh4a_nofpu_mach =
{
"sh4a_nofpu", "sh4a_nofpu", MACH_SH5,
16, 16, &sh_models[9], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
const MACH sh4al_mach =
{
"sh4al", "sh4al", MACH_SH5,
16, 16, &sh_models[10], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
@ -1024,7 +1149,7 @@ const MACH sh4_mach =
const MACH sh5_mach =
{
"sh5", "sh5", MACH_SH5,
32, 32, &sh_models[4], &sh5_imp_properties,
32, 32, &sh_models[11], &sh5_imp_properties,
shmedia_init_cpu,
sh64_prepare_run
};