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2006-12-29  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_modrm_byte): Handle shift count
	register with 3 operands.

gas/testsuite/

2006-12-29  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/intel.s: Add tests for "shrd %cl,%edx,%eax" and
	"shld %cl,%edx,%eax".
	* gas/i386/opcode.s: Likewise.

	* gas/i386/intel.d: Updated.
	* gas/i386/opcode-intel.d: Likewise.
	* gas/i386/opcode-suffix.d: Likewise.
	* gas/i386/opcode.d: Likewise.
This commit is contained in:
H.J. Lu 2006-12-29 21:48:48 +00:00
parent 2d45707707
commit c81128dcdf
9 changed files with 38 additions and 6 deletions
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5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2006-12-29 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_modrm_byte): Handle shift count
register with 3 operands.
2006-12-28 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Check i.reg_operands

11
gas/config/tc-i386.c
View File

@ -3436,10 +3436,13 @@ build_modrm_byte ()
source = 0;
break;
case 3:
/* When there are 3 operands, one of them must be immediate,
which may be the first or the last operand. */
assert (i.imm_operands == 1);
source = (i.types[0] & Imm) ? 1 : 0;
/* When there are 3 operands, one of them may be immediate,
which may be the first or the last operand. Otherwise,
the first operand must be shift count register (cl). */
assert (i.imm_operands == 1
|| (i.imm_operands == 0
&& (i.types[0] & ShiftCount)));
source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
break;
case 4:
/* When there are 4 operands, the first two must be immediate

11
gas/testsuite/ChangeLog
View File

@ -1,3 +1,14 @@
2006-12-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/intel.s: Add tests for "shrd %cl,%edx,%eax" and
"shld %cl,%edx,%eax".
* gas/i386/opcode.s: Likewise.
* gas/i386/intel.d: Updated.
* gas/i386/opcode-intel.d: Likewise.
* gas/i386/opcode-suffix.d: Likewise.
* gas/i386/opcode.d: Likewise.
2006-12-27 Kazu Hirata <kazu@codesourcery.com>
* gas/m68k/all.exp: Add support for fido.

3
gas/testsuite/gas/i386/intel.d
View File

@ -628,5 +628,6 @@ Disassembly of section .text:
a87: b0 11 [ ]*mov \$0x11,%al
a89: b3 47 [ ]*mov \$0x47,%bl
a8b: b3 47 [ ]*mov \$0x47,%bl
a8d: 00 00 .*
a8d: 0f ad d0 [ ]*shrd %cl,%edx,%eax
a90: 0f a5 d0 [ ]*shld %cl,%edx,%eax
[ ]*...

5
gas/testsuite/gas/i386/intel.s
View File

@ -624,5 +624,8 @@ rot5:
mov %al, 0x11
mov %bl, ((( 0x4711 ) >> 8) & 0xff)
mov %bl, 0x47
shrd eax, edx, cl
shld eax, edx, cl
.p2align 4,0

2
gas/testsuite/gas/i386/opcode-intel.d
View File

@ -606,4 +606,6 @@ Disassembly of section .text:
*[0-9a-f]+: 0f 00 c8[ ]+str[ ]+eax
*[0-9a-f]+: 66 0f 00 c8[ ]+str[ ]+ax
*[0-9a-f]+: 0f 00 08[ ]+str[ ]+(WORD PTR )?\[eax\]
*[0-9a-f]+: 0f ad d0 [ ]*shrd[ ]+eax,edx,cl
*[0-9a-f]+: 0f a5 d0 [ ]*shld[ ]+eax,edx,cl
\.\.\.

2
gas/testsuite/gas/i386/opcode-suffix.d
View File

@ -583,4 +583,6 @@ Disassembly of section .text:
*[0-9a-f]+: 0f 00 c8[ ]+strl[ ]+%eax
*[0-9a-f]+: 66 0f 00 c8[ ]+strw[ ]+%ax
*[0-9a-f]+: 0f 00 08[ ]+strw[ ]+\(%eax\)
*[0-9a-f]+: 0f ad d0 [ ]*shrdl[ ]+%cl,%edx,%eax
*[0-9a-f]+: 0f a5 d0 [ ]*shldl[ ]+%cl,%edx,%eax
\.\.\.

2
gas/testsuite/gas/i386/opcode.d
View File

@ -582,4 +582,6 @@ Disassembly of section .text:
9e5: 0f 00 c8 [ ]*str %eax
9e8: 66 0f 00 c8 [ ]*str %ax
9ec: 0f 00 08 [ ]*str \(%eax\)
9ef: 0f ad d0 [ ]*shrd %cl,%edx,%eax
9f2: 0f a5 d0 [ ]*shld %cl,%edx,%eax
\.\.\.

3
gas/testsuite/gas/i386/opcode.s
View File

@ -578,5 +578,8 @@ foo:
str %ax
str (%eax)
shrd %cl,%edx,%eax
shld %cl,%edx,%eax
# Force a good alignment.
.p2align 4,0