2003-08-03 Jason Eckhardt <jle@rice.edu>
* gas/i860/dual01.{s,d}: New files.
* gas/i860/dual02-err.{s,l}: New files.
* gas/i860/dual03.{s,d}: New files.
* gas/i860/i860.exp: Execute the above new tests.
* gas/i860/README.i860: Update.
This commit is contained in:
Jason Eckhardt
parent
3ab6b7717b
commit
c83c437177
@ -1,3 +1,11 @@
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2003-08-03 Jason Eckhardt <jle@rice.edu>
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* gas/i860/dual01.{s,d}: New files.
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* gas/i860/dual02-err.{s,l}: New files.
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* gas/i860/dual03.{s,d}: New files.
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* gas/i860/i860.exp: Execute the above new tests.
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* gas/i860/README.i860: Update.
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2003-08-02 Alan Modra <amodra@bigpond.net.au>
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* gas/d10v/address-001.d: Adjust for objdump -d change.
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@ -3,10 +3,12 @@ Testsuite for the i860 version of the GNU assembler
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---------------------------------------------------
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This is a simple testsuite for the i860 assembler. It currently
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consists of testcases for checking that every instruction is
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parsed correctly and that correct object code is generated.
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consists mostly of testcases for checking that every instruction is
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parsed correctly and that correct object code is generated (these
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are called "blah.s"). The files called "blah-err.s" test for error
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conditions.
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It includes testcases for the base i860XR instruction set as well
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The suite includes testcases for the base i860XR instruction set as well
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as the enhanced i860XP instructions and control registers.
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The expected results files were generated using the UNIX System V/i860
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@ -17,11 +19,18 @@ way GAS/i860 is tested against a known good assembler.
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TODO:
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- Relocation testing is basically non-existent.
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- pst.d (pixel store) is the only instruction with no testcase.
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- Tests for dual instruction mode: alignment of a dual mode pair,
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check that dual mode has a proper pair (FLOP/integer) of instructions,
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known gas defect when handling the d.fnop, etc.
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- All current testcases use the default AT&T/SVR4 syntax; a few simple
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tests of the Intel syntax should be added to prevent bitrot.
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- More tests for dual instruction mode: check that dual mode has a
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proper pair (FLOP/core) of instructions, and other error conditions.
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- Most current testcases use the default AT&T/SVR4 syntax; a few simple
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tests of the Intel syntax should be added to prevent bitrot (including
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relocatable expression syntax, etc). Test file dual03.s uses Intel
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syntax lightly (i.e., register names without '%' prefix).
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Contact me (Jason Eckhardt, jle@rice.edu) if you'd like to help.
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Known failures:
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- dual01.s: GAS mishandles d.fnop (dual bit erroneously set on next
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instruction).
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- dual02-err.s: GAS currently doesn't check that dual mode pairs
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are properly aligned.
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21
gas/testsuite/gas/i860/dual01.d
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21
gas/testsuite/gas/i860/dual01.d
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@ -0,0 +1,21 @@
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#as:
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#objdump: -d
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#name: i860 dual01
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <\.text>:
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0: 00 00 00 a0 shl %r0,%r0,%r0
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4: 00 00 00 a0 shl %r0,%r0,%r0
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8: b0 47 4c 49 d.pfadd.dd %f8,%f10,%f12
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c: 00 28 c6 90 adds %r5,%r6,%r6
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10: b0 47 4c 49 d.pfadd.dd %f8,%f10,%f12
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14: 10 00 58 25 fld.d 16\(%r10\),%f24
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18: 00 02 00 b0 d.shrd %r0,%r0,%r0
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1c: 08 00 48 25 fld.d 8\(%r10\),%f8
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20: 00 02 00 b0 d.shrd %r0,%r0,%r0
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24: 00 00 50 25 fld.d 0\(%r10\),%f16
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28: 00 00 00 a0 shl %r0,%r0,%r0
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2c: 00 00 00 a0 shl %r0,%r0,%r0
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17
gas/testsuite/gas/i860/dual01.s
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17
gas/testsuite/gas/i860/dual01.s
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# Test fnop's dual bit (all other floating point operations have their dual
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# bit tested in their individual test files).
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.text
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.align 8
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nop
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nop
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d.pfadd.dd %f8,%f10,%f12
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adds %r5,%r6,%r6
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d.pfadd.dd %f8,%f10,%f12
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fld.d 16(%r10),%f24
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d.fnop
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fld.d 8(%r10),%f8
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d.fnop
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fld.d 0(%r10),%f16
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nop
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nop
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2
gas/testsuite/gas/i860/dual02-err.l
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2
gas/testsuite/gas/i860/dual02-err.l
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.*: Assembler messages:
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.*:7: Error: FLOP with 'd\.' prefix must be 8-byte aligned
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9
gas/testsuite/gas/i860/dual02-err.s
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9
gas/testsuite/gas/i860/dual02-err.s
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# Dual-mode pairs must be aligned on an 8-byte boundary. This tests
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# that an error is reported if not properly aligned.
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.text
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.align 8
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nop
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d.fadd.ss %f3,%f5,%f7
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addu %r4,%r5,%r6
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53
gas/testsuite/gas/i860/dual03.d
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53
gas/testsuite/gas/i860/dual03.d
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#as: -mintel-syntax
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#objdump: -d
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#name: i860 dual03
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <L1-0x20>:
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0: 00 00 14 22 fld.d %r0\(%r16\),%f20
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4: fe ff 15 94 adds -2,%r0,%r21
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8: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0
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c: fa ff 31 96 adds -6,%r17,%r17
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10: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0
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14: 02 a8 20 b6 bla %r21,%r17,0x00000020 // 20 <L1>
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18: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0
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1c: 09 00 16 26 fld.d 8\(%r16\)\+\+,%f22
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00000020 <L1>:
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20: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30
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24: 06 a8 20 b6 bla %r21,%r17,0x00000040 // 40 <L2>
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28: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31
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2c: 09 00 14 26 fld.d 8\(%r16\)\+\+,%f20
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30: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30
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34: 0a 00 00 68 br 0x00000060 // 60 <S>
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38: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31
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3c: 00 00 00 a0 shl %r0,%r0,%r0
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00000040 <L2>:
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40: 30 b6 de 4b d.pfadd.ss %f22,%f30,%f30
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44: f6 af 3f b6 bla %r21,%r17,0x00000020 // 20 <L1>
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48: 30 be ff 4b d.pfadd.ss %f23,%f31,%f31
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4c: 09 00 16 26 fld.d 8\(%r16\)\+\+,%f22
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50: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30
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54: 00 00 00 a0 shl %r0,%r0,%r0
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58: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31
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5c: 00 00 00 a0 shl %r0,%r0,%r0
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00000060 <S>:
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60: 30 b4 de 4b pfadd.ss %f22,%f30,%f30
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64: fc ff 15 94 adds -4,%r0,%r21
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68: 30 bc ff 4b pfadd.ss %f23,%f31,%f31
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6c: 02 a8 20 5a bte %r21,%r17,0x00000078 // 78 <DONE>
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70: 0b 00 14 26 fld.l 8\(%r16\)\+\+,%f20
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74: 30 a4 de 4b pfadd.ss %f20,%f30,%f30
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00000078 <DONE>:
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78: 30 04 1e 48 pfadd.ss %f0,%f0,%f30
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7c: 30 f4 ff 4b pfadd.ss %f30,%f31,%f31
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80: 30 04 1e 48 pfadd.ss %f0,%f0,%f30
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84: 30 04 00 48 pfadd.ss %f0,%f0,%f0
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88: 30 04 1f 48 pfadd.ss %f0,%f0,%f31
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8c: 30 f0 f0 4b fadd.ss %f30,%f31,%f16
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46
gas/testsuite/gas/i860/dual03.s
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46
gas/testsuite/gas/i860/dual03.s
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// A larger dual-mode test, from the programmer's reference manual.
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// This uses Intel syntax, as in the manual.
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// Single-precision vector sum
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fld.d r0(r16),f20
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mov -2,r21
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d.pfadd.ss f0,f0,f0
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adds -6,r17,r17
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d.pfadd.ss f0,f0,f0
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bla r21,r17,L1
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d.pfadd.ss f0,f0,f0
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fld.d 8(r16)++,f22
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L1:
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d.pfadd.ss f20,f30,f30
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bla r21,r17,L2
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d.pfadd.ss f21,f31,f31
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fld.d 8(r16)++,f20
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d.pfadd.ss f20,f30,f30
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br S
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d.pfadd.ss f21,f31,f31
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nop
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L2:
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d.pfadd.ss f22,f30,f30
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bla r21,r17,L1
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d.pfadd.ss f23,f31,f31
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fld.d 8(r16)++,f22
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d.pfadd.ss f20,f30,f30
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nop
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d.pfadd.ss f21,f31,f31
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nop
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S:
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pfadd.ss f22,f30,f30
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mov -4,r21
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pfadd.ss f23,f31,f31
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bte r21,r17,DONE
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fld.l 8(r16)++,f20
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pfadd.ss f20,f30,f30
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DONE:
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pfadd.ss f0,f0,f30
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pfadd.ss f30,f31,f31
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pfadd.ss f0,f0,f30
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pfadd.ss f0,f0,f0
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pfadd.ss f0,f0,f31
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fadd.ss f30,f31,f16
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@ -1,9 +1,53 @@
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# i860 assembler testsuite.
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if [istarget i860-*-*] {
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foreach file [lsort [glob -nocomplain -- $srcdir/$subdir/*.s]] {
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set file [file tail $file]
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set file [file rootname $file]
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run_dump_test "$file"
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proc run_list_test { name opts } {
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global srcdir subdir
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set testname "i860 $name"
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set file $srcdir/$subdir/$name
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gas_run ${name}.s $opts ">&dump.out"
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if { [regexp_diff "dump.out" "${file}.l"] } then {
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fail $testname
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verbose "output is [file_contents "dump.out"]" 2
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return
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}
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}
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pass $testname
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}
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if [istarget i860-*-*] {
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run_dump_test "bitwise"
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run_dump_test "branch"
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run_dump_test "bte"
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run_dump_test "dual01"
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run_list_test "dual02-err" ""
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run_dump_test "dual03"
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run_dump_test "fldst01"
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run_dump_test "fldst02"
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run_dump_test "fldst03"
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run_dump_test "fldst04"
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run_dump_test "fldst05"
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run_dump_test "fldst06"
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run_dump_test "fldst07"
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run_dump_test "fldst08"
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run_dump_test "float01"
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run_dump_test "float02"
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run_dump_test "float03"
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run_dump_test "float04"
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run_dump_test "form"
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run_dump_test "iarith"
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run_dump_test "ldst01"
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run_dump_test "ldst02"
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run_dump_test "ldst03"
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run_dump_test "ldst04"
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run_dump_test "ldst05"
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run_dump_test "ldst06"
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run_dump_test "pfam"
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run_dump_test "pfmam"
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run_dump_test "pfmsm"
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run_dump_test "pfsm"
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run_dump_test "regress01"
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run_dump_test "shift"
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run_dump_test "simd"
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run_dump_test "system"
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run_dump_test "xp"
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}
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