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2004-01-24 Chris Demetriou <cgd@broadcom.com> 

* config/tc-mips.c (hilo_interlocks): Change definition
        so that MIPS32, MIPS64 and later ISAs are included, along with
        the already-included machines.  Update comments.
This commit is contained in:
Chris Demetriou 2004-01-25 06:01:03 +00:00
parent 424688adb8
commit c8978940ea
2 changed files with 29 additions and 8 deletions
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6
gas/ChangeLog
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@ -1,3 +1,9 @@
2004-01-24 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (hilo_interlocks): Change definition
so that MIPS32, MIPS64 and later ISAs are included, along with
the already-included machines. Update comments.
2004-01-23 Daniel Jacobowitz <drow@mvista.com>
* config/tc-arm.c (tc_gen_reloc): Improve error message for

31
gas/config/tc-mips.c
View File

@ -325,15 +325,30 @@ static int mips_32bitmode = 0;
/* True if CPU has a ror instruction. */
#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
/* Whether the processor uses hardware interlocks to protect
reads from the HI and LO registers, and thus does not
require nops to be inserted. */
/* True if mflo and mfhi can be immediately followed by instructions
which write to the HI and LO registers.
#define hilo_interlocks (mips_opts.arch == CPU_R4010 \
|| mips_opts.arch == CPU_VR5500 \
|| mips_opts.arch == CPU_RM7000 \
|| mips_opts.arch == CPU_SB1 \
)
According to MIPS specifications, MIPS ISAs I, II, and III need
(at least) two instructions between the reads of HI/LO and
instructions which write them, and later ISAs do not. Contradicting
the MIPS specifications, some MIPS IV processor user manuals (e.g.
the UM for the NEC Vr5000) document needing the instructions between
HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
MIPS64 and later ISAs to have the interlocks, plus any specific
earlier-ISA CPUs for which CPU documentation declares that the
instructions are really interlocked. */
#define hilo_interlocks \
(mips_opts.isa == ISA_MIPS32 \
|| mips_opts.isa == ISA_MIPS32R2 \
|| mips_opts.isa == ISA_MIPS64 \
|| mips_opts.isa == ISA_MIPS64R2 \
|| mips_opts.arch == CPU_R4010 \
|| mips_opts.arch == CPU_R10000 \
|| mips_opts.arch == CPU_R12000 \
|| mips_opts.arch == CPU_RM7000 \
|| mips_opts.arch == CPU_SB1 \
|| mips_opts.arch == CPU_VR5500 \
)
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs after they are loaded from memory, and thus does not