2004-01-24 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (hilo_interlocks): Change definition so that MIPS32, MIPS64 and later ISAs are included, along with the already-included machines. Update comments.
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@ -1,3 +1,9 @@
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2004-01-24 Chris Demetriou <cgd@broadcom.com>
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* config/tc-mips.c (hilo_interlocks): Change definition
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so that MIPS32, MIPS64 and later ISAs are included, along with
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the already-included machines. Update comments.
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2004-01-23 Daniel Jacobowitz <drow@mvista.com>
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* config/tc-arm.c (tc_gen_reloc): Improve error message for
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@ -325,14 +325,29 @@ static int mips_32bitmode = 0;
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/* True if CPU has a ror instruction. */
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#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
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/* Whether the processor uses hardware interlocks to protect
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reads from the HI and LO registers, and thus does not
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require nops to be inserted. */
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/* True if mflo and mfhi can be immediately followed by instructions
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which write to the HI and LO registers.
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#define hilo_interlocks (mips_opts.arch == CPU_R4010 \
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|| mips_opts.arch == CPU_VR5500 \
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According to MIPS specifications, MIPS ISAs I, II, and III need
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(at least) two instructions between the reads of HI/LO and
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instructions which write them, and later ISAs do not. Contradicting
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the MIPS specifications, some MIPS IV processor user manuals (e.g.
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the UM for the NEC Vr5000) document needing the instructions between
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HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
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MIPS64 and later ISAs to have the interlocks, plus any specific
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earlier-ISA CPUs for which CPU documentation declares that the
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instructions are really interlocked. */
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#define hilo_interlocks \
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(mips_opts.isa == ISA_MIPS32 \
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|| mips_opts.isa == ISA_MIPS32R2 \
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|| mips_opts.isa == ISA_MIPS64 \
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|| mips_opts.isa == ISA_MIPS64R2 \
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|| mips_opts.arch == CPU_R4010 \
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|| mips_opts.arch == CPU_R10000 \
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|| mips_opts.arch == CPU_R12000 \
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|| mips_opts.arch == CPU_RM7000 \
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|| mips_opts.arch == CPU_SB1 \
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|| mips_opts.arch == CPU_VR5500 \
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)
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/* Whether the processor uses hardware interlocks to protect reads
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