* config/tc-arm.c (it_fsm_post_encode): New forward declaration.
(set_it_insn_type_nonvoid): New macro. (emit_thumb32_expr): New function. (thumb_insn_size): New function. (emit_insn): New function. (s_arm_elf_inst): New function. (md_pseudo_table): New pseudo-opcode entries added. * doc/c-arm.texi: New directive added. * gas/arm/inst-po.d: New testcase. * gas/arm/inst-po.s: New file. * gas/arm/inst-po-2.d: New testcase. * gas/arm/inst-po-2.s: New file. * gas/arm/inst-po-2.l: New file. * gas/arm/inst-po-3.d: New testcase. * gas/arm/inst-po-3.s: New file. * gas/arm/inst-po-be.d: New testcase.
This commit is contained in:
parent
a177aad3d7
commit
c921be7d91
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@ -1,3 +1,14 @@
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2009-07-09 Daniel Gutson <dgutson@codesourcery.com>
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* config/tc-arm.c (it_fsm_post_encode): New forward declaration.
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(set_it_insn_type_nonvoid): New macro.
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(emit_thumb32_expr): New function.
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(thumb_insn_size): New function.
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(emit_insn): New function.
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(s_arm_elf_inst): New function.
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(md_pseudo_table): New pseudo-opcode entries added.
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* doc/c-arm.texi: New directive added.
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2009-07-07 DJ Delorie <dj@redhat.com>
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* config/tc-mep.c (md_begin): Don't reset the coprocessor options
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2
gas/NEWS
2
gas/NEWS
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@ -1,4 +1,6 @@
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-*- text -*-
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* ARM assembler now supports .inst[.nw] pseudo-ops to insert opcodes specified
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in binary rather than text.
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* Add support for common symbol alignment to PE formats.
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File diff suppressed because it is too large
Load Diff
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@ -569,6 +569,15 @@ Must be preceded by a @code{.personality} or @code{.personalityindex}
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directive.
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@c IIIIIIIIIIIIIIIIIIIIIIIIII
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@cindex @code{.inst} directive, ARM
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@item .inst @var{opcode} [ , @dots{} ]
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@item .inst.n @var{opcode} [ , @dots{} ]
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@item .inst.w @var{opcode} [ , @dots{} ]
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Generates the instruction corresponding to the numerical value @var{opcode}.
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@code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
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specified explicitly, overriding the normal encoding rules.
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@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
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@c KKKKKKKKKKKKKKKKKKKKKKKKKK
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@c LLLLLLLLLLLLLLLLLLLLLLLLLL
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@ -1,3 +1,14 @@
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2009-07-09 Daniel Gutson <dgutson@codesourcery.com>
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* gas/arm/inst-po.d: New testcase.
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* gas/arm/inst-po.s: New file.
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* gas/arm/inst-po-2.d: New testcase.
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* gas/arm/inst-po-2.s: New file.
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* gas/arm/inst-po-2.l: New file.
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* gas/arm/inst-po-3.d: New testcase.
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* gas/arm/inst-po-3.s: New file.
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* gas/arm/inst-po-be.d: New testcase.
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2009-07-07 2009-07-04 Chung-Lin Tang <cltang@pllab.cs.nthu.edu.tw>
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* gas/arm/iwmmxt2.d: Fix insn pattern for torvsc,
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@ -0,0 +1,4 @@
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#name: .inst pseudo-opcode validations test
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#objdump: -d --prefix-addresses --show-raw-insn
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#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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#error-output: inst-po-2.l
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@ -0,0 +1,6 @@
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[^:]*: Assembler messages:
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[^:]*:7: Error: constant expression required
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[^:]*:10: Error: width suffixes are invalid in ARM mode
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[^:]*:11: Error: width suffixes are invalid in ARM mode
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[^:]*:14: Error: cannot determine Thumb instruction size. Use .inst.n/.inst.w instead
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[^:]*:15: Error: .inst.n operand too big. Use .inst.w instead
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@ -0,0 +1,16 @@
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.syntax unified
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.arch armv7a
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.arm
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.L1:
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moveq r1, r9
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.inst .L1
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.arm
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.inst.w 1
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.inst.n 1
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.thumb
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.inst 0xf000
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.inst.n 1<<31
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@ -0,0 +1,16 @@
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#name: .inst pseudo-opcode with automatic IT blocks test
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#as: -mimplicit-it=always
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#objdump: -d --prefix-addresses --show-raw-insn
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#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: +file format .*arm.*
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Disassembly of section .text:
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00000000 <.text> bf08 it eq
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00000002 <.text\+0x2> 4649 moveq r1, r9
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00000004 <.text\+0x4> 4649 mov r1, r9
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00000006 <.text\+0x6> 4649 mov r1, r9
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00000008 <.text\+0x8> 00001234 .word 0x00001234
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0000000c <.text\+0xc> bf0c ite eq
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0000000e <.text\+0xe> 4649 moveq r1, r9
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00000010 <.text\+0x10> 4649 movne r1, r9
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@ -0,0 +1,17 @@
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.syntax unified
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.arch armv7a
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.thumb
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@ it eq
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@ mov r1, r9
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@ mov r1, r9
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moveq r1, r9
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.inst 0x4649
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.inst 0x4649
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.word 0x1234
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@ ite eq
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@ moveq r1, r9
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@ movne r1, r9
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.inst 0xbf0b + 1, 0x4649, 0x4649
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@ -0,0 +1,21 @@
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#name: .inst pseudo-opcode test 1 - big endian version
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#as: -mbig-endian
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#objdump: -d --prefix-addresses --show-raw-insn
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#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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#source: inst-po.s
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.*: +file format .*arm.*
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Disassembly of section .text:
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00000000 <.text> 11a01009 movne r1, r9
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00000004 <.text\+0x4> bf0c ite eq
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00000006 <.text\+0x6> 4649 moveq r1, r9
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00000008 <.text\+0x8> 4649 movne r1, r9
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0000000a <.text\+0xa> 0000 .short 0x0000
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0000000c <.text\+0xc> 1234 .short 0x1234
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0000000e <.text\+0xe> bf0c ite eq
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00000010 <.text\+0x10> 4649 moveq r1, r9
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00000012 <.text\+0x12> 4649 movne r1, r9
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00000014 <.text\+0x14> 4649 mov r1, r9
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00000016 <.text\+0x16> ea4f 0109 mov.w r1, r9
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0000001a <.text\+0x1a> ea4f 0109 mov.w r1, r9
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@ -0,0 +1,19 @@
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#name: .inst pseudo-opcode test 1
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#objdump: -d --prefix-addresses --show-raw-insn
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#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: +file format .*arm.*
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Disassembly of section .text:
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00000000 <.text> 11a01009 movne r1, r9
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00000004 <.text\+0x4> bf0c ite eq
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00000006 <.text\+0x6> 4649 moveq r1, r9
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00000008 <.text\+0x8> 4649 movne r1, r9
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0000000a <.text\+0xa> 1234 .short 0x1234
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0000000c <.text\+0xc> 0000 .short 0x0000
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0000000e <.text\+0xe> bf0c ite eq
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00000010 <.text\+0x10> 4649 moveq r1, r9
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00000012 <.text\+0x12> 4649 movne r1, r9
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00000014 <.text\+0x14> 4649 mov r1, r9
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00000016 <.text\+0x16> ea4f 0109 mov.w r1, r9
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0000001a <.text\+0x1a> ea4f 0109 mov.w r1, r9
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@ -0,0 +1,27 @@
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.syntax unified
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.arch armv7a
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.arm
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@ movne r1,r9
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.inst 0x11a01009
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.thumb
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@ ite eq
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@ moveq r1, r9
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@ movne r1, r9
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.inst 0xbf0b + 1, 0x4649
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.inst 0x4649
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.word 0x1234
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@ ite eq
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@ moveq r1, r9
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@ movne r1, r9
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.inst.n 0xbf0b + 1, 0x4649, 0x4649
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.inst.n 0x4649
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@ mov.w r1, r9
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@ mov.w r1, r9
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.inst 0xea4f0109
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.inst.w 0xea4f0109
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