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* config/tc-arm.c (it_fsm_post_encode): New forward declaration. 

(set_it_insn_type_nonvoid): New macro.
        (emit_thumb32_expr): New function.
        (thumb_insn_size): New function.
        (emit_insn): New function.
        (s_arm_elf_inst): New function.
        (md_pseudo_table): New pseudo-opcode entries added.
        * doc/c-arm.texi: New directive added.

        * gas/arm/inst-po.d: New testcase.
        * gas/arm/inst-po.s: New file.
        * gas/arm/inst-po-2.d: New testcase.
        * gas/arm/inst-po-2.s: New file.
        * gas/arm/inst-po-2.l: New file.
        * gas/arm/inst-po-3.d: New testcase.
        * gas/arm/inst-po-3.s: New file.
        * gas/arm/inst-po-be.d: New testcase.
This commit is contained in:
Nick Clifton 2009-07-09 07:52:37 +00:00
parent a177aad3d7
commit c921be7d91
13 changed files with 611 additions and 273 deletions
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11
gas/ChangeLog
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@ -1,3 +1,14 @@
2009-07-09 Daniel Gutson <dgutson@codesourcery.com>
* config/tc-arm.c (it_fsm_post_encode): New forward declaration.
(set_it_insn_type_nonvoid): New macro.
(emit_thumb32_expr): New function.
(thumb_insn_size): New function.
(emit_insn): New function.
(s_arm_elf_inst): New function.
(md_pseudo_table): New pseudo-opcode entries added.
* doc/c-arm.texi: New directive added.
2009-07-07 DJ Delorie <dj@redhat.com>
* config/tc-mep.c (md_begin): Don't reset the coprocessor options

2
gas/NEWS
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@ -1,4 +1,6 @@
-*- text -*-
* ARM assembler now supports .inst[.nw] pseudo-ops to insert opcodes specified
in binary rather than text.
* Add support for common symbol alignment to PE formats.

725
gas/config/tc-arm.c
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File diff suppressed because it is too large Load Diff

9
gas/doc/c-arm.texi
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@ -569,6 +569,15 @@ Must be preceded by a @code{.personality} or @code{.personalityindex}
directive.
@c IIIIIIIIIIIIIIIIIIIIIIIIII
@cindex @code{.inst} directive, ARM
@item .inst @var{opcode} [ , @dots{} ]
@item .inst.n @var{opcode} [ , @dots{} ]
@item .inst.w @var{opcode} [ , @dots{} ]
Generates the instruction corresponding to the numerical value @var{opcode}.
@code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
specified explicitly, overriding the normal encoding rules.
@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
@c KKKKKKKKKKKKKKKKKKKKKKKKKK
@c LLLLLLLLLLLLLLLLLLLLLLLLLL

11
gas/testsuite/ChangeLog
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@ -1,3 +1,14 @@
2009-07-09 Daniel Gutson <dgutson@codesourcery.com>
* gas/arm/inst-po.d: New testcase.
* gas/arm/inst-po.s: New file.
* gas/arm/inst-po-2.d: New testcase.
* gas/arm/inst-po-2.s: New file.
* gas/arm/inst-po-2.l: New file.
* gas/arm/inst-po-3.d: New testcase.
* gas/arm/inst-po-3.s: New file.
* gas/arm/inst-po-be.d: New testcase.
2009-07-07 2009-07-04 Chung-Lin Tang <cltang@pllab.cs.nthu.edu.tw>
* gas/arm/iwmmxt2.d: Fix insn pattern for torvsc,

4
gas/testsuite/gas/arm/inst-po-2.d Normal file
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@ -0,0 +1,4 @@
#name: .inst pseudo-opcode validations test
#objdump: -d --prefix-addresses --show-raw-insn
#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
#error-output: inst-po-2.l

6
gas/testsuite/gas/arm/inst-po-2.l Normal file
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@ -0,0 +1,6 @@
[^:]*: Assembler messages:
[^:]*:7: Error: constant expression required
[^:]*:10: Error: width suffixes are invalid in ARM mode
[^:]*:11: Error: width suffixes are invalid in ARM mode
[^:]*:14: Error: cannot determine Thumb instruction size. Use .inst.n/.inst.w instead
[^:]*:15: Error: .inst.n operand too big. Use .inst.w instead

16
gas/testsuite/gas/arm/inst-po-2.s Normal file
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@ -0,0 +1,16 @@
.syntax unified
.arch armv7a
.arm
.L1:
moveq r1, r9
.inst .L1
.arm
.inst.w 1
.inst.n 1
.thumb
.inst 0xf000
.inst.n 1<<31

16
gas/testsuite/gas/arm/inst-po-3.d Normal file
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@ -0,0 +1,16 @@
#name: .inst pseudo-opcode with automatic IT blocks test
#as: -mimplicit-it=always
#objdump: -d --prefix-addresses --show-raw-insn
#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: +file format .*arm.*
Disassembly of section .text:
00000000 <.text> bf08 it eq
00000002 <.text\+0x2> 4649 moveq r1, r9
00000004 <.text\+0x4> 4649 mov r1, r9
00000006 <.text\+0x6> 4649 mov r1, r9
00000008 <.text\+0x8> 00001234 .word 0x00001234
0000000c <.text\+0xc> bf0c ite eq
0000000e <.text\+0xe> 4649 moveq r1, r9
00000010 <.text\+0x10> 4649 movne r1, r9

17
gas/testsuite/gas/arm/inst-po-3.s Normal file
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@ -0,0 +1,17 @@
.syntax unified
.arch armv7a
.thumb
@ it eq
@ mov r1, r9
@ mov r1, r9
moveq r1, r9
.inst 0x4649
.inst 0x4649
.word 0x1234
@ ite eq
@ moveq r1, r9
@ movne r1, r9
.inst 0xbf0b + 1, 0x4649, 0x4649

21
gas/testsuite/gas/arm/inst-po-be.d Normal file
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@ -0,0 +1,21 @@
#name: .inst pseudo-opcode test 1 - big endian version
#as: -mbig-endian
#objdump: -d --prefix-addresses --show-raw-insn
#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
#source: inst-po.s
.*: +file format .*arm.*
Disassembly of section .text:
00000000 <.text> 11a01009 movne r1, r9
00000004 <.text\+0x4> bf0c ite eq
00000006 <.text\+0x6> 4649 moveq r1, r9
00000008 <.text\+0x8> 4649 movne r1, r9
0000000a <.text\+0xa> 0000 .short 0x0000
0000000c <.text\+0xc> 1234 .short 0x1234
0000000e <.text\+0xe> bf0c ite eq
00000010 <.text\+0x10> 4649 moveq r1, r9
00000012 <.text\+0x12> 4649 movne r1, r9
00000014 <.text\+0x14> 4649 mov r1, r9
00000016 <.text\+0x16> ea4f 0109 mov.w r1, r9
0000001a <.text\+0x1a> ea4f 0109 mov.w r1, r9

19
gas/testsuite/gas/arm/inst-po.d Normal file
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@ -0,0 +1,19 @@
#name: .inst pseudo-opcode test 1
#objdump: -d --prefix-addresses --show-raw-insn
#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: +file format .*arm.*
Disassembly of section .text:
00000000 <.text> 11a01009 movne r1, r9
00000004 <.text\+0x4> bf0c ite eq
00000006 <.text\+0x6> 4649 moveq r1, r9
00000008 <.text\+0x8> 4649 movne r1, r9
0000000a <.text\+0xa> 1234 .short 0x1234
0000000c <.text\+0xc> 0000 .short 0x0000
0000000e <.text\+0xe> bf0c ite eq
00000010 <.text\+0x10> 4649 moveq r1, r9
00000012 <.text\+0x12> 4649 movne r1, r9
00000014 <.text\+0x14> 4649 mov r1, r9
00000016 <.text\+0x16> ea4f 0109 mov.w r1, r9
0000001a <.text\+0x1a> ea4f 0109 mov.w r1, r9

27
gas/testsuite/gas/arm/inst-po.s Normal file
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@ -0,0 +1,27 @@
.syntax unified
.arch armv7a
.arm
@ movne r1,r9
.inst 0x11a01009
.thumb
@ ite eq
@ moveq r1, r9
@ movne r1, r9
.inst 0xbf0b + 1, 0x4649
.inst 0x4649
.word 0x1234
@ ite eq
@ moveq r1, r9
@ movne r1, r9
.inst.n 0xbf0b + 1, 0x4649, 0x4649
.inst.n 0x4649
@ mov.w r1, r9
@ mov.w r1, r9
.inst 0xea4f0109
.inst.w 0xea4f0109