gas/
* config/bfin-defs.h (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. * config/bfin-parse.y (asm_1): Check illegal register move instructions. gas/testsuite/ * gas/bfin/expected_move_errors.s, gas/bfin/expected_move_errors.l: Add "LC1 = I0;". * gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W". opcodes/ * bfin-dis.c (IS_DREG): Define. (IS_PREG): Define. (IS_AREG): Define. (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. (decode_REGMV_0): Check illegal register move instructions.
This commit is contained in:
Jie Zhang
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1d3ad4d0b0
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c958a8a8fb
@ -1,3 +1,11 @@
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2009-09-03 Jie Zhang <jie.zhang@analog.com>
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* config/bfin-defs.h (IS_GENREG): Define.
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(IS_DAGREG): Define.
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(IS_SYSREG): Define.
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* config/bfin-parse.y (asm_1): Check illegal register move
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instructions.
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2009-09-03 Jie Zhang <jie.zhang@analog.com>
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* config/bfin-parse.y (asm_1): Fix a typo.
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@ -201,6 +201,25 @@ enum reg_class
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#define IS_CREG(r) ((r).regno == REG_LC0 || (r).regno == REG_LC1)
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#define IS_ALLREG(r) ((r).regno < T_NOGROUP)
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#define IS_GENREG(r) \
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(IS_DREG (r) || IS_PREG (r) \
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|| (r).regno == REG_A0x || (r).regno == REG_A0w \
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|| (r).regno == REG_A1x || (r).regno == REG_A1w)
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#define IS_DAGREG(r) \
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(IS_IREG (r) || IS_MREG (r) || IS_BREG (r) || IS_LREG (r))
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#define IS_SYSREG(r) \
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((r).regno == REG_ASTAT || (r).regno == REG_SEQSTAT \
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|| (r).regno == REG_SYSCFG || (r).regno == REG_RETI \
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|| (r).regno == REG_RETX || (r).regno == REG_RETN \
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|| (r).regno == REG_RETE || (r).regno == REG_RETS \
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|| (r).regno == REG_LC0 || (r).regno == REG_LC1 \
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|| (r).regno == REG_LT0 || (r).regno == REG_LT1 \
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|| (r).regno == REG_LB0 || (r).regno == REG_LB1 \
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|| (r).regno == REG_CYCLES || (r).regno == REG_CYCLES2 \
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|| (r).regno == REG_EMUDAT)
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/* Expression value macros. */
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typedef enum
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@ -1720,9 +1720,18 @@ asm_1:
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| REG ASSIGN REG
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{
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if (IS_ALLREG ($1) && IS_ALLREG ($3))
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if ((IS_GENREG ($1) && IS_GENREG ($3))
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|| (IS_GENREG ($1) && IS_DAGREG ($3))
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|| (IS_DAGREG ($1) && IS_GENREG ($3))
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|| (IS_DAGREG ($1) && IS_DAGREG ($3))
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|| (IS_GENREG ($1) && $3.regno == REG_USP)
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|| ($1.regno == REG_USP && IS_GENREG ($3))
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|| (IS_DREG ($1) && IS_SYSREG ($3))
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|| (IS_PREG ($1) && IS_SYSREG ($3))
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|| (IS_SYSREG ($1) && IS_DREG ($3))
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|| (IS_SYSREG ($1) && IS_PREG ($3))
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|| (IS_SYSREG ($1) && $3.regno == REG_USP))
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{
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notethat ("REGMV: allregs = allregs\n");
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$$ = bfin_gen_regmv (&$3, &$1);
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}
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else
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@ -1,3 +1,9 @@
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2009-09-03 Jie Zhang <jie.zhang@analog.com>
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* gas/bfin/expected_move_errors.s,
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gas/bfin/expected_move_errors.l: Add "LC1 = I0;".
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* gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W".
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2009-09-03 Jie Zhang <jie.zhang@analog.com>
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* gas/bfin/expected_comparison_errors.l: Expect error on Line 13.
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@ -3,3 +3,4 @@
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.*:4: Error: Cannot move A0 to high half of register. Input text was A0.
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.*:5: Error: Cannot move A1 to even register.
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.*:6: Error: Cannot move A0 to odd register.
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.*:7: Error: Register mismatch.
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@ -4,3 +4,4 @@
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R0.H = A0;
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R0 = A1;
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R1 = A0;
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LC1 = I0;
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@ -27,56 +27,56 @@ Disassembly of section .text:
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26: 96 31 R2 = CYCLES;
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28: 9f 31 R3 = CYCLES2;
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2a: cf 31 R1 = EMUDAT;
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2c: 31 3d CYCLES = A0.W;
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2e: 7f 38 RETS = FP;
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30: e0 3d LT1 = USP;
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32: 72 38 ASTAT = P2;
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34: 08 c4 [0|3][0|f] c0 A0 = A1;
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38: 08 c4 [0|3][0|f] e0 A1 = A0;
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3c: 09 c4 00 20 A0 = R0;
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40: 09 c4 08 a0 A1 = R1;
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44: 8b c0 00 39 R4 = A0 \(FU\);
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48: 2f c1 00 19 R5 = A1 \(ISS2\);
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4c: 0b c0 80 39 R6 = A0;
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50: 0f c0 80 19 R7 = A1;
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54: 0f c0 80 39 R7 = A1, R6 = A0;
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58: 8f c0 00 38 R1 = A1, R0 = A0 \(FU\);
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2c: 7f 38 RETS = FP;
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2e: e0 3d LT1 = USP;
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30: 72 38 ASTAT = P2;
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32: 08 c4 [0|3][0|f] c0 A0 = A1;
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36: 08 c4 [0|3][0|f] e0 A1 = A0;
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3a: 09 c4 00 20 A0 = R0;
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3e: 09 c4 08 a0 A1 = R1;
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42: 8b c0 00 39 R4 = A0 \(FU\);
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46: 2f c1 00 19 R5 = A1 \(ISS2\);
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4a: 0b c0 80 39 R6 = A0;
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4e: 0f c0 80 19 R7 = A1;
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52: 0f c0 80 39 R7 = A1, R6 = A0;
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56: 8f c0 00 38 R1 = A1, R0 = A0 \(FU\);
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0000005c <move_conditional>:
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5c: 6a 07 IF CC R5 = P2;
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5e: b0 06 IF !CC SP = R0;
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0000005a <move_conditional>:
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5a: 6a 07 IF CC R5 = P2;
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5c: b0 06 IF !CC SP = R0;
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00000060 <move_half_to_full_zero_extend>:
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60: fa 42 R2 = R7.L \(Z\);
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62: c8 42 R0 = R1.L \(Z\);
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0000005e <move_half_to_full_zero_extend>:
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5e: fa 42 R2 = R7.L \(Z\);
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60: c8 42 R0 = R1.L \(Z\);
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00000064 <move_half_to_full_sign_extend>:
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64: 8d 42 R5 = R1.L \(X\);
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66: 93 42 R3 = R2.L \(X\);
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00000062 <move_half_to_full_sign_extend>:
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62: 8d 42 R5 = R1.L \(X\);
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64: 93 42 R3 = R2.L \(X\);
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00000068 <move_register_half>:
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68: 09 c4 28 40 A0.X = R5.L;
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6c: 09 c4 10 c0 A1.X = R2.L;
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70: 0a c4 [0|3][0|6] 00 R0.L = A0.X;
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74: 0a c4 [0|3][0|6] 4e R7.L = A1.X;
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78: 09 c4 18 00 A0.L = R3.L;
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7c: 09 c4 20 80 A1.L = R4.L;
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80: 29 c4 30 00 A0.H = R6.H;
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84: 29 c4 28 80 A1.H = R5.H;
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88: 83 c1 00 38 R0.L = A0 \(IU\);
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8c: 27 c0 40 18 R1.H = A1 \(S2RND\);
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90: 07 c0 40 18 R1.H = A1;
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94: 67 c1 80 38 R2.H = A1, R2.L = A0 \(IH\);
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98: 07 c0 80 38 R2.H = A1, R2.L = A0;
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9c: 47 c0 00 38 R0.H = A1, R0.L = A0 \(T\);
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a0: 87 c0 00 38 R0.H = A1, R0.L = A0 \(FU\);
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a4: 07 c1 00 38 R0.H = A1, R0.L = A0 \(IS\);
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a8: 07 c0 00 38 R0.H = A1, R0.L = A0;
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00000066 <move_register_half>:
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66: 09 c4 28 40 A0.X = R5.L;
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6a: 09 c4 10 c0 A1.X = R2.L;
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6e: 0a c4 [0|3][0|6] 00 R0.L = A0.X;
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72: 0a c4 [0|3][0|6] 4e R7.L = A1.X;
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76: 09 c4 18 00 A0.L = R3.L;
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7a: 09 c4 20 80 A1.L = R4.L;
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7e: 29 c4 30 00 A0.H = R6.H;
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82: 29 c4 28 80 A1.H = R5.H;
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86: 83 c1 00 38 R0.L = A0 \(IU\);
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8a: 27 c0 40 18 R1.H = A1 \(S2RND\);
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8e: 07 c0 40 18 R1.H = A1;
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92: 67 c1 80 38 R2.H = A1, R2.L = A0 \(IH\);
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96: 07 c0 80 38 R2.H = A1, R2.L = A0;
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9a: 47 c0 00 38 R0.H = A1, R0.L = A0 \(T\);
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9e: 87 c0 00 38 R0.H = A1, R0.L = A0 \(FU\);
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a2: 07 c1 00 38 R0.H = A1, R0.L = A0 \(IS\);
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a6: 07 c0 00 38 R0.H = A1, R0.L = A0;
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000000ac <move_byte_zero_extend>:
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ac: 57 43 R7 = R2.B \(Z\);
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ae: 48 43 R0 = R1.B \(Z\);
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000000aa <move_byte_zero_extend>:
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aa: 57 43 R7 = R2.B \(Z\);
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ac: 48 43 R0 = R1.B \(Z\);
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000000b0 <move_byte_sign_extend>:
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b0: 4e 43 R6 = R1.B \(Z\);
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b2: 65 43 R5 = R4.B \(Z\);
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000000ae <move_byte_sign_extend>:
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ae: 4e 43 R6 = R1.B \(Z\);
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b0: 65 43 R5 = R4.B \(Z\);
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...
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@ -23,7 +23,6 @@ move_register:
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R2 = Cycles;
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R3 = Cycles2;
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r1 = emudat;
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CYCLES = A0.W;
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Rets = Fp;
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Lt1 = USP;
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ASTAT = P2;
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@ -1,3 +1,13 @@
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2009-09-03 Jie Zhang <jie.zhang@analog.com>
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* bfin-dis.c (IS_DREG): Define.
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(IS_PREG): Define.
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(IS_AREG): Define.
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(IS_GENREG): Define.
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(IS_DAGREG): Define.
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(IS_SYSREG): Define.
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(decode_REGMV_0): Check illegal register move instructions.
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2009-09-03 Dave Korn <dave.korn.cygwin@gmail.com>
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* Makefile.am (BUILD_LIBINTL): New variable.
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@ -432,9 +432,18 @@ static enum machine_registers decode_allregs[] =
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REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
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REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
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REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
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REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_LASTREG,
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REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
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REG_LASTREG,
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};
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#define IS_DREG(g,r) ((g) == 0)
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#define IS_PREG(g,r) ((g) == 1)
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#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
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#define IS_GENREG(g,r) ((g) == 0 || (g) == 1 || IS_AREG (g, r))
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#define IS_DAGREG(g,r) ((g) == 2 || (g) == 3)
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#define IS_SYSREG(g,r) \
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(((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
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#define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
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#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
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#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
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@ -1324,6 +1333,19 @@ decode_REGMV_0 (TIword iw0, disassemble_info *outf)
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int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
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int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
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if (!((IS_GENREG (gd, dst) && IS_GENREG (gs, src))
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|| (IS_GENREG (gd, dst) && IS_DAGREG (gs, src))
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|| (IS_DAGREG (gd, dst) && IS_GENREG (gs, src))
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|| (IS_DAGREG (gd, dst) && IS_DAGREG (gs, src))
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|| (IS_GENREG (gd, dst) && gs == 7 && src == 0)
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|| (gd == 7 && dst == 0 && IS_GENREG (gs, src))
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|| (IS_DREG (gd, dst) && IS_SYSREG (gs, src))
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|| (IS_PREG (gd, dst) && IS_SYSREG (gs, src))
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|| (IS_SYSREG (gd, dst) && IS_DREG (gs, src))
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|| (IS_SYSREG (gd, dst) && IS_PREG (gs, src))
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|| (IS_SYSREG (gd, dst) && gs == 7 && src == 0)))
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return 0;
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OUTS (outf, allregs (dst, gd));
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OUTS (outf, " = ");
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OUTS (outf, allregs (src, gs));
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