MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership
Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit instruction requiring a 64-bit ISA. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the SP-relative "sd"/$ra entry (SDRASP minor opcode). gas/ * testsuite/gas/mips/mips16-sdrasp.d: New test. * testsuite/gas/mips/mips16-sdrasp.l: New stderr output. * testsuite/gas/mips/mips16-sdrasp.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
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2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/mips16-sdrasp.d: New test.
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* testsuite/gas/mips/mips16-sdrasp.l: New stderr output.
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* testsuite/gas/mips/mips16-sdrasp.s: New test source.
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* testsuite/gas/mips/mips.exp: Run the new test.
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2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
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2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/mips.exp: Limit remaining tests that
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* testsuite/gas/mips/mips.exp: Limit remaining tests that
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@ -1313,6 +1313,7 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "mips16-intermix"
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run_dump_test "mips16-intermix"
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run_dump_test "mips16-extend"
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run_dump_test "mips16-extend"
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run_dump_test "mips16-sprel-swap"
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run_dump_test "mips16-sprel-swap"
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run_dump_test "mips16-sdrasp"
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run_dump_test "mips16-branch-unextended-1"
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run_dump_test "mips16-branch-unextended-1"
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run_dump_test "mips16-branch-unextended-2"
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run_dump_test "mips16-branch-unextended-2"
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#name: MIPS16 SDRASP opcode with 32-bit ISA
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#as: -32 -march=mips1
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#error-output: mips16-sdrasp.l
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.*: Assembler messages:
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.*:3: Error: opcode not supported on this processor: mips1 \(mips1\) `sd \$31,0\(\$29\)'
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.set mips16
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foo:
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sd $31, 0($29)
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# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
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.align 4, 0
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.space 16
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@ -1,3 +1,9 @@
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2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
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* mips16-opc.c (mips16_opcodes): Set membership to I3 rather
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than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
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opcode).
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2016-12-20 Andrew Waterman <andrew@sifive.com>
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2016-12-20 Andrew Waterman <andrew@sifive.com>
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* riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
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* riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
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@ -322,7 +322,7 @@ const struct mips_opcode mips16_opcodes[] =
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{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
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{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
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{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
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{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
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{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 },
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{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 },
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{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 },
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{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 },
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{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
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{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
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{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
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{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
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{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
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{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
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