RISC-V: Compress 3-operand beq/bne against x0.
This lets us accept an instruction like beq a2,x0,.Label and generate a compressed beqz. This will allow some future simplications to the gcc support, e.g. eliminating some duplicate patterns, and avoiding adding new duplicate patterns, since currently we have to handle signed and equality compares against zero specially. Tested with rv{32,64}-{elf,linux} cross builds and make checks for binutils and gcc. There were no regressions. gas/ * config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support. (riscv_ip) <'C'>: Add 'z' support. opcodes/ * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. <bne>: Likewise.
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@ -586,6 +586,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
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case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
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case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
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case 'w': break; /* RS1S, constrained to equal RD */
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case 'w': break; /* RS1S, constrained to equal RD */
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case 'x': break; /* RS2S, constrained to equal RD */
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case 'x': break; /* RS2S, constrained to equal RD */
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case 'z': break; /* RS2S, contrained to be x0 */
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case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
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case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
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case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
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case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
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case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
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case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
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@ -1472,6 +1473,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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|| regno != X_SP)
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|| regno != X_SP)
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break;
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break;
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continue;
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continue;
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case 'z': /* RS2, contrained to equal x0. */
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if (!reg_lookup (&s, RCLASS_GPR, ®no)
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|| regno != 0)
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break;
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continue;
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case '>':
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case '>':
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if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
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if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
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|| imm_expr->X_op != O_constant
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|| imm_expr->X_op != O_constant
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@ -247,6 +247,7 @@ const struct riscv_opcode riscv_opcodes[] =
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{"and", 0, {"I", 0}, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
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{"and", 0, {"I", 0}, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
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{"beqz", 0, {"C", 0}, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"beqz", 0, {"C", 0}, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"beqz", 0, {"I", 0}, "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"beqz", 0, {"I", 0}, "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"beq", 0, {"C", 0}, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"beq", 0, {"I", 0}, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH },
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{"beq", 0, {"I", 0}, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH },
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{"blez", 0, {"I", 0}, "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"blez", 0, {"I", 0}, "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"bgez", 0, {"I", 0}, "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"bgez", 0, {"I", 0}, "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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@ -262,6 +263,7 @@ const struct riscv_opcode riscv_opcodes[] =
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{"bgtu", 0, {"I", 0}, "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"bgtu", 0, {"I", 0}, "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"bnez", 0, {"C", 0}, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"bnez", 0, {"C", 0}, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"bnez", 0, {"I", 0}, "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"bnez", 0, {"I", 0}, "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"bne", 0, {"C", 0}, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"bne", 0, {"I", 0}, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH },
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{"bne", 0, {"I", 0}, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH },
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{"addi", 0, {"C", 0}, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
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{"addi", 0, {"C", 0}, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
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{"addi", 0, {"C", 0}, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
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{"addi", 0, {"C", 0}, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
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