* sparc-dis.c (print_insn_sparc): NUMOPCODES replaced with
sparc_num_opcodes. Update architecture enum values. * sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname. (sparc_opcode_lookup_arch): New function. (sparc_num_opcodes): Renamed from bfd_sparc_num_opcodes. (sparc_opcodes): Add v9a shutdown insn.
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b23b4cb58c
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ca4cb8bca2
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@ -1,3 +1,12 @@
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Thu Jan 25 03:39:10 1996 Doug Evans <dje@charmed.cygnus.com>
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* sparc-dis.c (print_insn_sparc): NUMOPCODES replaced with
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sparc_num_opcodes. Update architecture enum values.
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* sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname.
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(sparc_opcode_lookup_arch): New function.
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(sparc_num_opcodes): Renamed from bfd_sparc_num_opcodes.
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(sparc_opcodes): Add v9a shutdown insn.
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Mon Jan 22 08:29:59 1996 Doug Evans <dje@charmed.cygnus.com>
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Mon Jan 22 08:29:59 1996 Doug Evans <dje@charmed.cygnus.com>
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* sparc-dis.c (print_insn_sparc): Renamed from print_insn.
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* sparc-dis.c (print_insn_sparc): Renamed from print_insn.
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@ -28,16 +28,43 @@ Boston, MA 02111-1307, USA. */
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#include "ansidecl.h"
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#include "ansidecl.h"
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#include "opcode/sparc.h"
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#include "opcode/sparc.h"
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const char *architecture_pname[] = {
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/* Some defines to make life easy. */
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"v6",
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#define v6 SPARC_OPCODE_ARCH_V6
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"v7",
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#define v7 SPARC_OPCODE_ARCH_V7
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"v8",
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#define v8 SPARC_OPCODE_ARCH_V8
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"sparclite",
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#define sparclite SPARC_OPCODE_ARCH_SPARCLITE
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"v9",
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#define v9 SPARC_OPCODE_ARCH_V9
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"v9a", /* v9 with ultrasparc additions */
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#define v9a SPARC_OPCODE_ARCH_V9A
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NULL,
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/* Table of opcode architectures.
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The order is defined in opcode/sparc.h. */
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const struct sparc_opcode_arch sparc_opcode_archs[] = {
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{ "v6", 0 },
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{ "v7", 0 },
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{ "v8", 0 },
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{ "sparclite", (1 << v9) | (1 << v9a) },
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{ "v9", 1 << sparclite },
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{ "v9a", 1 << sparclite }, /* v9 with ultrasparc additions */
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{ NULL, 0 }
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};
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};
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/* Given NAME, return it's architecture entry. */
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const enum sparc_opcode_arch_val
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sparc_opcode_lookup_arch (name)
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const char *name;
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{
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const struct sparc_opcode_arch *p;
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for (p = &sparc_opcode_archs[0]; p->name; ++p)
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{
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if (strcmp (name, p->name) == 0)
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return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
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}
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return SPARC_OPCODE_ARCH_BAD;
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}
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/* Branch condition field. */
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/* Branch condition field. */
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#define COND(x) (((x)&0xf)<<25)
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#define COND(x) (((x)&0xf)<<25)
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@ -93,7 +120,7 @@ const char *architecture_pname[] = {
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#define XCC (1<<12) /* v9 */
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#define XCC (1<<12) /* v9 */
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#define FCC(x) (((x)&0x3)<<11) /* v9 */
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#define FCC(x) (((x)&0x3)<<11) /* v9 */
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#define FBFCC(x) (((x)&0x3)<<20) /* v9 */
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#define FBFCC(x) (((x)&0x3)<<20) /* v9 */
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/* The order of the opcodes in the table is significant:
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/* The order of the opcodes in the table is significant:
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* The assembler requires that all instances of the same mnemonic must
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* The assembler requires that all instances of the same mnemonic must
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@ -1460,9 +1487,13 @@ IMPDEP ("impdep2", 0x37),
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{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
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{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
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{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
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{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
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/* Ultrasparc extensions */
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/* FIXME: lots more to go */
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{ "shutdown", F3F(2, 0x36, 0x80), F3(~2, ~0x36, ~0x80)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a },
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};
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};
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const int bfd_sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
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const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
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/* Utilities for argument parsing. */
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/* Utilities for argument parsing. */
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