Add support for relaxation of bit manipulation instructions.
This commit is contained in:
Nick Clifton
parent
a94154757c
commit
ca9a79a174
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@ -1,6 +1,6 @@
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/* BFD back-end for Renesas H8/300 COFF binaries.
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Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2000, 2001, 2002, 2003
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2000, 2001, 2002, 2003, 2004
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Free Software Foundation, Inc.
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Written by Steve Chamberlain, <sac@cygnus.com>.
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@ -666,6 +666,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
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bfd_vma value;
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bfd_vma dot;
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int gap, tmp;
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unsigned char temp_code;
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switch (reloc->howto->type)
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{
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@ -947,8 +948,12 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
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if (data[dst_address - 2] != 0x6a)
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abort ();
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temp_code = data[src_address - 1];
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if ((temp_code & 0x10) != 0x10)
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temp_code &= 0xf0;
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/* Fix up the opcode. */
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switch (data[src_address - 1] & 0xf0)
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switch (temp_code)
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{
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case 0x00:
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data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x20;
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@ -956,6 +961,12 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
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case 0x80:
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data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x30;
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break;
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case 0x18:
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data[dst_address - 2] = 0x7f;
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break;
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case 0x10:
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data[dst_address - 2] = 0x7e;
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break;
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default:
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abort ();
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}
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@ -972,8 +983,12 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
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if (data[dst_address - 2] != 0x6a)
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abort ();
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temp_code = data[src_address - 1];
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if ((temp_code & 0x30) != 0x30)
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temp_code &= 0xf0;
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/* Fix up the opcode. */
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switch (data[src_address - 1] & 0xf0)
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switch (temp_code)
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{
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case 0x20:
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data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x20;
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@ -981,6 +996,12 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
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case 0xa0:
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data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x30;
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break;
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case 0x38:
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data[dst_address - 2] = 0x7f;
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break;
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case 0x30:
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data[dst_address - 2] = 0x7e;
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break;
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default:
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abort ();
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}
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@ -1010,6 +1010,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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if (value >= 0xffffff00u)
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{
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unsigned char code;
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unsigned char temp_code;
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/* Note that we've changed the relocs, section contents,
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etc. */
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@ -1024,18 +1025,29 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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if (code != 0x6a)
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abort ();
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code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
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temp_code = code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
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if ((temp_code & 0x10) != 0x10)
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temp_code &= 0xf0;
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if ((code & 0xf0) == 0x00)
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bfd_put_8 (abfd,
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(code & 0xf) | 0x20,
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contents + irel->r_offset - 2);
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else if ((code & 0xf0) == 0x80)
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bfd_put_8 (abfd,
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(code & 0xf) | 0x30,
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contents + irel->r_offset - 2);
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else
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abort ();
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switch (temp_code)
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{
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case 0x00:
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bfd_put_8 (abfd, (code & 0xf) | 0x20,
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contents + irel->r_offset - 2);
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break;
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case 0x80:
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bfd_put_8 (abfd, (code & 0xf) | 0x30,
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contents + irel->r_offset - 2);
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break;
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case 0x18:
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bfd_put_8 (abfd, 0x7f, contents + irel->r_offset - 2);
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break;
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case 0x10:
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bfd_put_8 (abfd, 0x7e, contents + irel->r_offset - 2);
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break;
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default:
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abort ();
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}
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/* Fix the relocation's type. */
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irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
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@ -1066,6 +1078,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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if (value >= 0xffffff00u)
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{
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unsigned char code;
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unsigned char temp_code;
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/* Note that we've changed the relocs, section contents,
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etc. */
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@ -1080,9 +1093,12 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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if (code != 0x6a)
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abort ();
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code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
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temp_code = code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
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switch (code & 0xf0)
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if ((temp_code & 0x30) != 0x30)
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temp_code &= 0xf0;
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switch (temp_code)
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{
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case 0x20:
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bfd_put_8 (abfd, (code & 0xf) | 0x20,
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@ -1092,8 +1108,14 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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bfd_put_8 (abfd, (code & 0xf) | 0x30,
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contents + irel->r_offset - 2);
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break;
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case 0x38:
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bfd_put_8 (abfd, 0x7f, contents + irel->r_offset - 2);
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break;
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case 0x30:
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bfd_put_8 (abfd, 0x7e, contents + irel->r_offset - 2);
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break;
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default:
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abort ();
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abort();
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}
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/* Fix the relocation's type. */
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@ -1113,7 +1135,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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}
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}
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/* FALLTHRU */
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/* Fall through. */
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/* This is a 24/32bit absolute address in a "mov" insn, which may
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become a 16-bit absolute address if it is in the right range. */
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@ -1,3 +1,8 @@
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2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
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* config/tc-h8300.c (build_bytes): Apply relaxation to bit
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manipulation insns.
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2004-01-12 Richard Sandiford <rsandifo@redhat.com>
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* config/tc-mips.c (macro_build_jalr): When adding an R_MIPS_JALR
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@ -1,6 +1,6 @@
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/* tc-h8300.c -- Assemble code for the Renesas H8/300
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Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
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2001, 2002, 2003 Free Software Foundation, Inc.
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2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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@ -1578,9 +1578,23 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
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for (i = 0; i < this_try->length; i++)
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output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1];
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/* Note if this is a movb instruction -- there's a special relaxation
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which only applies to them. */
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if (this_try->opcode->how == O (O_MOV, SB))
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/* Note if this is a movb or a bit manipulation instruction
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there is a special relaxation which only applies. */
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if ( this_try->opcode->how == O (O_MOV, SB)
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|| this_try->opcode->how == O (O_BCLR, SB)
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|| this_try->opcode->how == O (O_BAND, SB)
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|| this_try->opcode->how == O (O_BIAND, SB)
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|| this_try->opcode->how == O (O_BILD, SB)
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|| this_try->opcode->how == O (O_BIOR, SB)
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|| this_try->opcode->how == O (O_BIST, SB)
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|| this_try->opcode->how == O (O_BIXOR, SB)
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|| this_try->opcode->how == O (O_BLD, SB)
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|| this_try->opcode->how == O (O_BNOT, SB)
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|| this_try->opcode->how == O (O_BOR, SB)
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|| this_try->opcode->how == O (O_BSET, SB)
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|| this_try->opcode->how == O (O_BST, SB)
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|| this_try->opcode->how == O (O_BTST, SB)
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|| this_try->opcode->how == O (O_BXOR, SB))
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movb = 1;
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/* Output any fixes. */
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@ -1,3 +1,7 @@
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2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (BITOP): Pass MEMRELAX flag.
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2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
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@ -895,8 +895,8 @@ struct h8_opcode
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{code, AV_H8, 2, name, {{imm, RD8, E}}, {{op00, op01, imm, RD8, E}}}, \
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{code, AV_H8, 6, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, 0, E}}}, \
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{code, AV_H8, 6, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, 0, E}}}, \
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{code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \
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{code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | ABS32LIST, op00, op01, imm, op4, E}}}
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{code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \
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{code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}}
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#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
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{code, AV_H8SX, 0, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, op4, E}}}, \
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@ -1,3 +1,12 @@
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2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
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* ld-h8300/h8300-exp: Run the relax-4 test.
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* ld-h8300/relax-4.s: New file: Source for relax-4 test.
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* ld-h8300/relax-4.d: New file: Expected output and commands for
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assembling and linking the relax-4 test.
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* ld-h8300/relax-4-coff.d: New file: Variant for the COFF based
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toolchain.
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2004-01-09 H.J. Lu <hongjiu.lu@intel.com>
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* ld-selective/selective.exp: Skip ia64-*-*.
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@ -1,5 +1,5 @@
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# Expect script for ld-h8300 tests
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# Copyright 2002, 2003 Free Software Foundation, Inc.
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# Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
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#
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# This file is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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@ -29,6 +29,8 @@ run_dump_test relax
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if {[istarget *-elf]} {
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run_dump_test relax-2
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run_dump_test relax-3
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run_dump_test relax-4
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} else {
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run_dump_test relax-3-coff
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run_dump_test relax-4-coff
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}
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@ -0,0 +1,52 @@
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# name: H8300 Relaxation Test 4
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# source: relax-4.s
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# ld: --relax -m h8300s
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# objdump: -d --no-show-raw-insn
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.*: file format .*-h8300
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Disassembly of section .text:
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00000100 <_start>:
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100: f8 03 mov.b #0x3,r0l
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102: fa 05 mov.b #0x5,r2l
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104: 7f ff 60 80 bset r0l,@0xff:8
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108: 7f 00 60 a0 bset r2l,@0x0:8
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10c: 7e ff 63 a0 btst r2l,@0xff:8
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110: 7e 00 63 80 btst r0l,@0x0:8
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114: 6a 18 00 00 70 50 bset #0x5,@0x0:16
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11a: 6a 18 7f ff 70 50 bset #0x5,@0x7fff:16
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120: 6a 18 80 00 70 50 bset #0x5,@0x8000:16
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126: 6a 18 fe ff 70 50 bset #0x5,@0xfeff:16
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12c: 7f 00 70 50 bset #0x5,@0x0:8
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130: 7f ff 70 50 bset #0x5,@0xff:8
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134: 6a 10 00 00 76 50 band #0x5,@0x0:16
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13a: 6a 10 7f ff 76 50 band #0x5,@0x7fff:16
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140: 6a 10 80 00 76 50 band #0x5,@0x8000:16
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146: 6a 10 fe ff 76 50 band #0x5,@0xfeff:16
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14c: 7e 00 76 50 band #0x5,@0x0:8
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150: 7e ff 76 50 band #0x5,@0xff:8
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154: 7f ff 60 a0 bset r2l,@0xff:8
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158: 7f 00 60 80 bset r0l,@0x0:8
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15c: 7e ff 63 80 btst r0l,@0xff:8
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160: 7e 00 63 a0 btst r2l,@0x0:8
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164: 6a 18 00 00 70 60 bset #0x6,@0x0:16
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16a: 6a 18 7f ff 70 60 bset #0x6,@0x7fff:16
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170: 6a 38 00 00 80 00 70 60 bset #0x6,@0x8000:32
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178: 6a 38 00 00 ff 00 70 60 bset #0x6,@0xff00:32
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180: 6a 38 00 ff ff 00 70 60 bset #0x6,@0xffff00:32
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188: 6a 38 ff ff 7f ff 70 60 bset #0x6,@0xffff7fff:32
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190: 6a 18 80 00 70 60 bset #0x6,@0x8000:16
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196: 6a 18 fe ff 70 60 bset #0x6,@0xfeff:16
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19c: 7f 00 70 60 bset #0x6,@0x0:8
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1a0: 7f ff 70 60 bset #0x6,@0xff:8
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1a4: 6a 10 00 00 76 60 band #0x6,@0x0:16
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1aa: 6a 10 7f ff 76 60 band #0x6,@0x7fff:16
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1b0: 6a 30 00 00 80 00 76 60 band #0x6,@0x8000:32
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1b8: 6a 30 00 00 ff 00 76 60 band #0x6,@0xff00:32
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1c0: 6a 30 00 ff ff 00 76 60 band #0x6,@0xffff00:32
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1c8: 6a 30 ff ff 7f ff 76 60 band #0x6,@0xffff7fff:32
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1d0: 6a 10 80 00 76 60 band #0x6,@0x8000:16
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1d6: 6a 10 fe ff 76 60 band #0x6,@0xfeff:16
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1dc: 7e 00 76 60 band #0x6,@0x0:8
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1e0: 7e ff 76 60 band #0x6,@0xff:8
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@ -0,0 +1,51 @@
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# name: H8300 Relaxation Test 4
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# ld: --relax -m h8300self
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# objdump: -d --no-show-raw-insn
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.*: file format .*-h8300
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Disassembly of section .text:
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00000100 <_start>:
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100: f8 03 mov.b #0x3,r0l
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102: fa 05 mov.b #0x5,r2l
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104: 7f ff 60 80 bset r0l,@0xff:8
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108: 7f 00 60 a0 bset r2l,@0x0:8
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10c: 7e ff 63 a0 btst r2l,@0xff:8
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110: 7e 00 63 80 btst r0l,@0x0:8
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114: 6a 18 00 00 70 50 bset #0x5,@0x0:16
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11a: 6a 18 7f ff 70 50 bset #0x5,@0x7fff:16
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120: 6a 18 80 00 70 50 bset #0x5,@0x8000:16
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126: 6a 18 fe ff 70 50 bset #0x5,@0xfeff:16
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12c: 7f 00 70 50 bset #0x5,@0x0:8
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130: 7f ff 70 50 bset #0x5,@0xff:8
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134: 6a 10 00 00 76 50 band #0x5,@0x0:16
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13a: 6a 10 7f ff 76 50 band #0x5,@0x7fff:16
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140: 6a 10 80 00 76 50 band #0x5,@0x8000:16
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146: 6a 10 fe ff 76 50 band #0x5,@0xfeff:16
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14c: 7e 00 76 50 band #0x5,@0x0:8
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150: 7e ff 76 50 band #0x5,@0xff:8
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154: 7f ff 60 a0 bset r2l,@0xff:8
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158: 7f 00 60 80 bset r0l,@0x0:8
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15c: 7e ff 63 80 btst r0l,@0xff:8
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160: 7e 00 63 a0 btst r2l,@0x0:8
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164: 6a 18 00 00 70 60 bset #0x6,@0x0:16
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16a: 6a 18 7f ff 70 60 bset #0x6,@0x7fff:16
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170: 6a 38 00 00 80 00 70 60 bset #0x6,@0x8000:32
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178: 6a 38 00 00 ff 00 70 60 bset #0x6,@0xff00:32
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180: 6a 38 00 ff ff 00 70 60 bset #0x6,@0xffff00:32
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||||
188: 6a 38 ff ff 7f ff 70 60 bset #0x6,@0xffff7fff:32
|
||||
190: 6a 18 80 00 70 60 bset #0x6,@0x8000:16
|
||||
196: 6a 18 fe ff 70 60 bset #0x6,@0xfeff:16
|
||||
19c: 7f 00 70 60 bset #0x6,@0x0:8
|
||||
1a0: 7f ff 70 60 bset #0x6,@0xff:8
|
||||
1a4: 6a 10 00 00 76 60 band #0x6,@0x0:16
|
||||
1aa: 6a 10 7f ff 76 60 band #0x6,@0x7fff:16
|
||||
1b0: 6a 30 00 00 80 00 76 60 band #0x6,@0x8000:32
|
||||
1b8: 6a 30 00 00 ff 00 76 60 band #0x6,@0xff00:32
|
||||
1c0: 6a 30 00 ff ff 00 76 60 band #0x6,@0xffff00:32
|
||||
1c8: 6a 30 ff ff 7f ff 76 60 band #0x6,@0xffff7fff:32
|
||||
1d0: 6a 10 80 00 76 60 band #0x6,@0x8000:16
|
||||
1d6: 6a 10 fe ff 76 60 band #0x6,@0xfeff:16
|
||||
1dc: 7e 00 76 60 band #0x6,@0x0:8
|
||||
1e0: 7e ff 76 60 band #0x6,@0xff:8
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
; Relaxation is possible for following bit manipulation instructions
|
||||
; BAND, BCLR, BIAND, BILD, BIOR, BIST, BIXOR, BLD, BNOT, BOR, BSET, BST, BTST, BXOR
|
||||
.h8300s
|
||||
.globl _start
|
||||
_start:
|
||||
# s3-s6 aren't valid 16-bit addresses.
|
||||
mov.b #0x3,r0l
|
||||
mov.b #0x5,r2l
|
||||
;
|
||||
; Relaxation of aa:16
|
||||
;
|
||||
bset r0l,@s10:16
|
||||
bset r2l,@s9:16
|
||||
btst r2l,@s10:16
|
||||
btst r0l,@s9:16
|
||||
|
||||
bset #5,@s1:16
|
||||
bset #5,@s2:16
|
||||
bset #5,@s7:16
|
||||
bset #5,@s8:16
|
||||
bset #5,@s9:16
|
||||
bset #5,@s10:16
|
||||
|
||||
band #5,@s1:16
|
||||
band #5,@s2:16
|
||||
band #5,@s7:16
|
||||
band #5,@s8:16
|
||||
band #5,@s9:16
|
||||
band #5,@s10:16
|
||||
;
|
||||
; Relaxation of aa:32
|
||||
;
|
||||
bset r2l,@s10:32
|
||||
bset r0l,@s9:32
|
||||
btst r0l,@s10:32
|
||||
btst r2l,@s9:32
|
||||
|
||||
bset #6,@s1:32
|
||||
bset #6,@s2:32
|
||||
bset #6,@s3:32
|
||||
bset #6,@s4:32
|
||||
bset #6,@s5:32
|
||||
bset #6,@s6:32
|
||||
bset #6,@s7:32
|
||||
bset #6,@s8:32
|
||||
bset #6,@s9:32
|
||||
bset #6,@s10:32
|
||||
|
||||
band #6,@s1:32
|
||||
band #6,@s2:32
|
||||
band #6,@s3:32
|
||||
band #6,@s4:32
|
||||
band #6,@s5:32
|
||||
band #6,@s6:32
|
||||
band #6,@s7:32
|
||||
band #6,@s8:32
|
||||
band #6,@s9:32
|
||||
band #6,@s10:32
|
||||
|
||||
.equ s1,0
|
||||
.equ s2,0x7fff
|
||||
.equ s3,0x8000
|
||||
.equ s4,0xff00
|
||||
.equ s5,0xffff00
|
||||
.equ s6,0xffff7fff
|
||||
.equ s7,0xffff8000
|
||||
.equ s8,0xfffffeff
|
||||
.equ s9,0xffffff00
|
||||
.equ s10,0xffffffff
|
||||
|
||||
.end
|
||||
|
||||
Loading…
Reference in New Issue