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2012-09-24 Steve Ellcey <sellcey@mips.com> 

* mips/basic.exp: Add mips*-mti-elf* target.
	* configure.ac: Add mips*-mti-elf* target.
	* configure: Regenerate.
This commit is contained in:
Steve Ellcey 2012-09-24 18:03:18 +00:00
parent b4aa388a20
commit cc2202431b
3 changed files with 11 additions and 3 deletions
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6
sim/mips/configure vendored
View File

@ -5312,6 +5312,7 @@ case "${target}" in
mips64vr*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
mips*tx39*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
mips*-sde-elf*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mips*-mti-elf*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mipsisa32*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mipsisa64*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
*) SIM_SUBTARGET="";;
@ -5389,6 +5390,7 @@ fi
mips_addr_bitsize=
case "${target}" in
mips*-sde-elf*) mips_bitsize=64 ; mips_msb=63 ;;
mips*-mti-elf*) mips_bitsize=64 ; mips_msb=63 ;;
mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mipsisa32*-*-*) mips_bitsize=32 ; mips_msb=31 ;;
@ -5466,6 +5468,7 @@ mips_fpu_bitsize=
case "${target}" in
mips*tx39*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;;
mips*-sde-elf*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
mips*-mti-elf*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
mipsisa32*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
@ -5571,7 +5574,8 @@ case "${target}" in
vr5500:mipsIV,vr5500:32,64,f:mips5500"
sim_multi_default=mips5000
;;
mips*-sde-elf*) sim_gen=M16
mips*-sde-elf* | mips*-mti-elf*)
sim_gen=M16
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips"
sim_m16_machine="-M mips16,mips16e,mips64r2"
sim_igen_filter="32,64,f"

6
sim/mips/configure.ac
View File

@ -22,6 +22,7 @@ case "${target}" in
mips64vr*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
mips*tx39*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
mips*-sde-elf*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mips*-mti-elf*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mipsisa32*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mipsisa64*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
*) SIM_SUBTARGET="";;
@ -55,6 +56,7 @@ SIM_AC_OPTION_ENDIAN($mips_endian,$default_endian)
mips_addr_bitsize=
case "${target}" in
mips*-sde-elf*) mips_bitsize=64 ; mips_msb=63 ;;
mips*-mti-elf*) mips_bitsize=64 ; mips_msb=63 ;;
mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mipsisa32*-*-*) mips_bitsize=32 ; mips_msb=31 ;;
@ -74,6 +76,7 @@ mips_fpu_bitsize=
case "${target}" in
mips*tx39*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;;
mips*-sde-elf*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
mips*-mti-elf*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
mipsisa32*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
@ -135,7 +138,8 @@ case "${target}" in
vr5500:mipsIV,vr5500:32,64,f:mips5500"
sim_multi_default=mips5000
;;
mips*-sde-elf*) sim_gen=M16
mips*-sde-elf* | mips*-mti-elf*)
sim_gen=M16
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips"
sim_m16_machine="-M mips16,mips16e,mips64r2"
sim_igen_filter="32,64,f"

2
sim/testsuite/sim/mips/basic.exp
View File

@ -47,7 +47,7 @@ if {[istarget mips*-*-elf]} {
set submodels "mips1 mips2 mips3 mips4"
append dspmodels " mips32r2 mips64r2"
append mdmxmodels " mips64 mips32r2 mips64r2"
} elseif {[istarget mips*-sde-elf*]} {
} elseif {[istarget mips*-sde-elf*] || [istarget mips*-mti-elf*]} {
set models "mips32 mips64 mips32r2 mips64r2"
set submodels ""
append dspmodels " mips32r2 mips64r2"