* config/obj-coff.c: Fix formatting.
* config/obj-elf.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-h8300.c: Likewise. * config/tc-hppa.c: Likewise.
This commit is contained in:
Kazu Hirata
parent
2b9c82010f
commit
cc8a6dd09b
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@ -1,3 +1,14 @@
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2002-05-09 Kazu Hirata <kazu@cs.umass.edu>
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* config/obj-coff.c: Fix formatting.
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* config/obj-elf.c: Likewise.
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* config/tc-alpha.c: Likewise.
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* config/tc-arm.c: Likewise.
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* config/tc-d10v.c: Likewise.
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* config/tc-d30v.c: Likewise.
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* config/tc-h8300.c: Likewise.
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* config/tc-hppa.c: Likewise.
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2002-05-09 Alan Modra <amodra@bigpond.net.au>
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* config/tc-i386.c (md_estimate_size_before_relax) Don't lose
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@ -568,7 +568,7 @@ obj_coff_loc (ignore)
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if (listing)
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{
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lineno += coff_line_base - 1;
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lineno += coff_line_base - 1;
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listing_source_line (lineno);
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}
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}
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@ -716,7 +716,7 @@ obj_coff_endef (ignore)
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name = S_GET_NAME (def_symbol_in_progress);
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if (name[0] == '.' && name[2] == 'f' && name[3] == '\0')
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{
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{
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switch (name[1])
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{
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case 'b':
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@ -842,16 +842,16 @@ obj_coff_endef (ignore)
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|| S_GET_SEGMENT (def_symbol_in_progress) == absolute_section
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|| ! symbol_constant_p (def_symbol_in_progress)
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|| (symbolP = symbol_find_base (S_GET_NAME (def_symbol_in_progress),
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DO_NOT_STRIP)) == NULL
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DO_NOT_STRIP)) == NULL
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|| SF_GET_TAG (def_symbol_in_progress) != SF_GET_TAG (symbolP))
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{
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/* If it already is at the end of the symbol list, do nothing */
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if (def_symbol_in_progress != symbol_lastP)
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{
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{
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symbol_remove (def_symbol_in_progress, &symbol_rootP, &symbol_lastP);
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symbol_append (def_symbol_in_progress, symbol_lastP, &symbol_rootP,
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&symbol_lastP);
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}
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}
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}
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else
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{
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@ -1504,13 +1504,13 @@ obj_coff_section (ignore)
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sections so adjust_reloc_syms in write.c will correctly handle
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relocs which refer to non-local symbols in these sections. */
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if (strncmp (name, ".gnu.linkonce", sizeof (".gnu.linkonce") - 1) == 0)
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flags |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD;
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flags |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD;
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#endif
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if (! bfd_set_section_flags (stdoutput, sec, flags))
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as_warn (_("error setting flags for \"%s\": %s"),
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bfd_section_name (stdoutput, sec),
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bfd_errmsg (bfd_get_error ()));
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as_warn (_("error setting flags for \"%s\": %s"),
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bfd_section_name (stdoutput, sec),
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bfd_errmsg (bfd_get_error ()));
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}
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else if (flags != SEC_NO_FLAGS)
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{
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@ -1564,7 +1564,7 @@ coff_frob_section (sec)
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fragp = seg_info (sec)->frchainP->frch_root;
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last = seg_info (sec)->frchainP->frch_last;
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while (fragp->fr_next != last)
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fragp = fragp->fr_next;
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fragp = fragp->fr_next;
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last->fr_address = size;
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fragp->fr_offset += new_size - size;
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}
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@ -1,6 +1,6 @@
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/* ELF object file format
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Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
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Free Software Foundation, Inc.
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Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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2001, 2002 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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@ -608,13 +608,13 @@ static struct special_section const special_sections[] =
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.section .init_array
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*/
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{ ".init_array",SHT_INIT_ARRAY, SHF_ALLOC + SHF_WRITE },
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{ ".init_array",SHT_INIT_ARRAY, SHF_ALLOC + SHF_WRITE },
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{ ".fini_array",SHT_FINI_ARRAY, SHF_ALLOC + SHF_WRITE },
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{ ".preinit_array",SHT_PREINIT_ARRAY, SHF_ALLOC + SHF_WRITE },
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{ ".preinit_array",SHT_PREINIT_ARRAY, SHF_ALLOC + SHF_WRITE },
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#else
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{ ".init_array",SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
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{ ".init_array",SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
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{ ".fini_array",SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
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{ ".preinit_array",SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
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{ ".preinit_array",SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
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#endif
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#ifdef ELF_TC_SPECIAL_SECTIONS
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@ -1,6 +1,6 @@
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/* tc-alpha.c - Processor-specific code for the DEC Alpha AXP CPU.
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Copyright 1989, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
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Free Software Foundation, Inc.
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Copyright 1989, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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2001, 2002 Free Software Foundation, Inc.
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Contributed by Carnegie Mellon University, 1993.
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Written by Alessandro Forin, based on earlier gas-1.38 target CPU files.
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Modified by Ken Raeburn for gas-2.x and ECOFF support.
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@ -1894,7 +1894,7 @@ tokenize_arguments (str, tok, ntok)
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goto err;
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++input_line_pointer;
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SKIP_WHITESPACE ();
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SKIP_WHITESPACE ();
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p = input_line_pointer;
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c = get_symbol_end ();
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@ -1917,7 +1917,7 @@ tokenize_arguments (str, tok, ntok)
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}
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*input_line_pointer = c;
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SKIP_WHITESPACE ();
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SKIP_WHITESPACE ();
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if (*input_line_pointer != '!')
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{
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if (r->require_seq)
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@ -2377,7 +2377,7 @@ assemble_insn (opcode, tok, ntok, insn, reloc)
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abort ();
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/* There is one special case for which an insn receives two
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relocations, and thus the user-supplied reloc does not
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relocations, and thus the user-supplied reloc does not
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override the operand reloc. */
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if (operand->default_reloc == BFD_RELOC_ALPHA_HINT)
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{
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@ -521,7 +521,7 @@ struct vfp_reg
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unsigned long regno;
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};
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static const struct vfp_reg vfp_regs[] =
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static const struct vfp_reg vfp_regs[] =
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{
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{"fpsid", 0x00000000},
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{"FPSID", 0x00000000},
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@ -842,7 +842,7 @@ static void do_mav_binops_3a PARAMS ((char *));
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static void do_mav_binops_3b PARAMS ((char *));
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static void do_mav_binops_3c PARAMS ((char *));
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static void do_mav_binops_3d PARAMS ((char *));
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static void do_mav_triple PARAMS ((char *, int, enum arm_reg_type,
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static void do_mav_triple PARAMS ((char *, int, enum arm_reg_type,
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enum arm_reg_type,
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enum arm_reg_type));
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static void do_mav_triple_4a PARAMS ((char *));
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@ -855,7 +855,7 @@ static void do_mav_triple_5e PARAMS ((char *));
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static void do_mav_triple_5f PARAMS ((char *));
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static void do_mav_triple_5g PARAMS ((char *));
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static void do_mav_triple_5h PARAMS ((char *));
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static void do_mav_quad PARAMS ((char *, int, enum arm_reg_type,
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static void do_mav_quad PARAMS ((char *, int, enum arm_reg_type,
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enum arm_reg_type,
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enum arm_reg_type,
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enum arm_reg_type));
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@ -1106,7 +1106,7 @@ static const struct asm_opcode insns[] =
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{"strh", 0xe00000b0, 3, ARM_EXT_V4, do_ldstv4},
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/* ARM Architecture 4T. */
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/* Note: bx (and blx) are required on V5, even if the processor does
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/* Note: bx (and blx) are required on V5, even if the processor does
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not support Thumb. */
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{"bx", 0xe12fff10, 2, ARM_EXT_V4T | ARM_EXT_V5, do_bx},
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@ -2165,14 +2165,14 @@ add_to_lit_pool ()
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break;
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if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
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&& inst.reloc.exp.X_op == O_symbol
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&& (literals[lit_count].exp.X_add_number
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&& inst.reloc.exp.X_op == O_symbol
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&& (literals[lit_count].exp.X_add_number
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== inst.reloc.exp.X_add_number)
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&& (literals[lit_count].exp.X_add_symbol
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&& (literals[lit_count].exp.X_add_symbol
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== inst.reloc.exp.X_add_symbol)
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&& (literals[lit_count].exp.X_op_symbol
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&& (literals[lit_count].exp.X_op_symbol
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== inst.reloc.exp.X_op_symbol))
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break;
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break;
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lit_count++;
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}
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@ -2624,9 +2624,9 @@ opcode_select (width)
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thumb_mode = 0;
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if (!need_pass_2)
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frag_align (2, 0, 0);
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frag_align (2, 0, 0);
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record_alignment (now_seg, 1);
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record_alignment (now_seg, 1);
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}
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break;
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@ -3450,13 +3450,13 @@ ld_mode_required_here (string)
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}
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else /* [Rn] */
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{
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skip_whitespace (str);
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skip_whitespace (str);
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if (* str == '!')
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{
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str ++;
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inst.instruction |= WRITE_BACK;
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}
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if (* str == '!')
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{
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str ++;
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inst.instruction |= WRITE_BACK;
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}
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inst.instruction |= INDEX_UP | HWOFFSET_IMM;
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pre_inc = 1;
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@ -4027,10 +4027,10 @@ do_blx (str)
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{
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/* This must be is BLX <target address>, no condition allowed. */
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if (inst.instruction != COND_ALWAYS)
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{
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inst.error = BAD_COND;
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{
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inst.error = BAD_COND;
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return;
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}
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}
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inst.instruction = 0xfafffffe;
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@ -4088,7 +4088,7 @@ do_t_blx (str)
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BKPT <16 bit unsigned immediate>
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Instruction is not conditional.
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The bit pattern given in insns[] has the COND_ALWAYS condition,
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and it is an error if the caller tried to override that. */
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and it is an error if the caller tried to override that. */
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static void
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do_bkpt (str)
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|
@ -4331,7 +4331,7 @@ do_ldrd (str)
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|| (rn = ld_mode_required_here (& str)) == FAIL)
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||||
{
|
||||
if (!inst.error)
|
||||
inst.error = BAD_ARGS;
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||||
inst.error = BAD_ARGS;
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -4514,7 +4514,7 @@ my_get_expression (ep, str)
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|||
return 0;
|
||||
}
|
||||
|
||||
/* We handle all bad expressions here, so that we can report the faulty
|
||||
/* We handle all bad expressions here, so that we can report the faulty
|
||||
instruction in the error message. */
|
||||
void
|
||||
md_operand (expr)
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||||
|
|
@ -5543,7 +5543,7 @@ do_ldstv4 (str)
|
|||
end_of_line (str);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
value = validate_immediate (~ inst.reloc.exp.X_add_number);
|
||||
|
||||
if (value != FAIL)
|
||||
|
|
@ -6729,7 +6729,7 @@ vfp_psr_parse (str)
|
|||
/* Mark it. */
|
||||
*--p = 0;
|
||||
|
||||
for (vreg = vfp_regs + 0;
|
||||
for (vreg = vfp_regs + 0;
|
||||
vreg < vfp_regs + sizeof (vfp_regs) / sizeof (struct vfp_reg);
|
||||
vreg++)
|
||||
{
|
||||
|
|
@ -7929,11 +7929,11 @@ mav_reg_required_here (str, shift, regtype)
|
|||
|
||||
/* Restore the start point. */
|
||||
*str = start;
|
||||
|
||||
|
||||
/* In the few cases where we might be able to accept something else
|
||||
this error can be overridden. */
|
||||
inst.error = _(all_reg_maps[regtype].expected);
|
||||
|
||||
|
||||
return FAIL;
|
||||
}
|
||||
|
||||
|
|
@ -8181,7 +8181,7 @@ do_mav_quad_6b (str)
|
|||
REG_TYPE_MVFX);
|
||||
}
|
||||
|
||||
/* cfmvsc32<cond> DSPSC,MVFX[15:0]. */
|
||||
/* cfmvsc32<cond> DSPSC,MVFX[15:0]. */
|
||||
static void
|
||||
do_mav_dspsc_1 (str)
|
||||
char * str;
|
||||
|
|
@ -9095,7 +9095,7 @@ create_register_alias (newname, p)
|
|||
*p = c;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
set_constant_flonums ()
|
||||
{
|
||||
|
|
@ -10487,7 +10487,7 @@ md_assemble (str)
|
|||
|
||||
/* md_parse_option
|
||||
Invocation line includes a switch not recognized by the base assembler.
|
||||
See if it's a processor-specific option.
|
||||
See if it's a processor-specific option.
|
||||
|
||||
This routine is somewhat complicated by the need for backwards
|
||||
compatibility (since older releases of gcc can't be changed).
|
||||
|
|
@ -10505,7 +10505,7 @@ md_assemble (str)
|
|||
-mthumb Start in Thumb mode
|
||||
-mthumb-interwork Code supports ARM/Thumb interworking
|
||||
|
||||
For now we will also provide support for
|
||||
For now we will also provide support for
|
||||
|
||||
-mapcs-32 32-bit Program counter
|
||||
-mapcs-26 26-bit Program counter
|
||||
|
|
@ -10581,7 +10581,7 @@ struct arm_option_table
|
|||
char *deprecated; /* If non-null, print this message. */
|
||||
};
|
||||
|
||||
struct arm_option_table arm_opts[] =
|
||||
struct arm_option_table arm_opts[] =
|
||||
{
|
||||
{"k", N_("generate PIC code"), &pic_code, 1, NULL},
|
||||
{"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
|
||||
|
|
@ -10789,7 +10789,7 @@ static struct arm_cpu_option_table arm_cpus[] =
|
|||
{"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_NONE},
|
||||
{NULL, 0, 0}
|
||||
};
|
||||
|
||||
|
||||
struct arm_arch_option_table
|
||||
{
|
||||
char *name;
|
||||
|
|
@ -11046,7 +11046,7 @@ md_parse_option (c, arg)
|
|||
#endif
|
||||
|
||||
case 'a':
|
||||
/* Listing option. Just ignore these, we don't support additional
|
||||
/* Listing option. Just ignore these, we don't support additional
|
||||
ones. */
|
||||
return 0;
|
||||
|
||||
|
|
@ -11073,10 +11073,10 @@ md_parse_option (c, arg)
|
|||
|
||||
for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
|
||||
{
|
||||
/* These options are expected to have an argument. */
|
||||
/* These options are expected to have an argument. */
|
||||
if (c == lopt->option[0]
|
||||
&& arg != NULL
|
||||
&& strncmp (arg, lopt->option + 1,
|
||||
&& strncmp (arg, lopt->option + 1,
|
||||
strlen (lopt->option + 1)) == 0)
|
||||
{
|
||||
#if WARN_DEPRECATED
|
||||
|
|
@ -11248,7 +11248,7 @@ arm_frob_label (sym)
|
|||
lsl r3, r3, #2
|
||||
ldr r2, [r3, r2]
|
||||
mov pc, r2
|
||||
|
||||
|
||||
.Lbbb: .word .Lxxx
|
||||
.Lccc: .word .Lyyy
|
||||
..etc...
|
||||
|
|
@ -11258,7 +11258,7 @@ arm_frob_label (sym)
|
|||
The second instruction converts a table index into a byte offset.
|
||||
The third instruction gets the jump address out of the table.
|
||||
The fourth instruction performs the jump.
|
||||
|
||||
|
||||
If the address stored at .Laaa is that of a symbol which has the
|
||||
Thumb_Func bit set, then the linker will arrange for this address
|
||||
to have the bottom bit set, which in turn would mean that the
|
||||
|
|
@ -11307,7 +11307,7 @@ arm_adjust_symtab ()
|
|||
as_bad (_("%s: unexpected function type: %d"),
|
||||
S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
|
||||
}
|
||||
else switch (S_GET_STORAGE_CLASS (sym))
|
||||
else switch (S_GET_STORAGE_CLASS (sym))
|
||||
{
|
||||
case C_EXT:
|
||||
S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
|
||||
|
|
@ -11609,17 +11609,17 @@ arm_handle_align (fragP)
|
|||
int bytes, fix, noop_size;
|
||||
char * p;
|
||||
const char * noop;
|
||||
|
||||
|
||||
if (fragP->fr_type != rs_align_code)
|
||||
return;
|
||||
|
||||
bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
|
||||
p = fragP->fr_literal + fragP->fr_fix;
|
||||
fix = 0;
|
||||
|
||||
|
||||
if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
|
||||
bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
|
||||
|
||||
|
||||
if (fragP->tc_frag_data)
|
||||
{
|
||||
if (target_big_endian)
|
||||
|
|
@ -11636,7 +11636,7 @@ arm_handle_align (fragP)
|
|||
noop = arm_noop;
|
||||
noop_size = sizeof (arm_noop);
|
||||
}
|
||||
|
||||
|
||||
if (bytes & (noop_size - 1))
|
||||
{
|
||||
fix = bytes & (noop_size - 1);
|
||||
|
|
@ -11652,7 +11652,7 @@ arm_handle_align (fragP)
|
|||
bytes -= noop_size;
|
||||
fix += noop_size;
|
||||
}
|
||||
|
||||
|
||||
fragP->fr_fix += fix;
|
||||
fragP->fr_var = noop_size;
|
||||
}
|
||||
|
|
@ -11671,7 +11671,7 @@ arm_frag_align_code (n, max)
|
|||
to support alignments greater than 32 bytes. */
|
||||
if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
|
||||
as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
|
||||
|
||||
|
||||
p = frag_var (rs_align_code,
|
||||
MAX_MEM_FOR_RS_ALIGN_CODE,
|
||||
1,
|
||||
|
|
|
|||
|
|
@ -99,9 +99,9 @@ static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1
|
|||
struct d10v_opcode *opcode2, unsigned long insn2,
|
||||
packing_type exec_type));
|
||||
|
||||
static void check_resource_conflict PARAMS ((struct d10v_opcode *opcode1,
|
||||
unsigned long insn1,
|
||||
struct d10v_opcode *opcode2,
|
||||
static void check_resource_conflict PARAMS ((struct d10v_opcode *opcode1,
|
||||
unsigned long insn1,
|
||||
struct d10v_opcode *opcode2,
|
||||
unsigned long insn2));
|
||||
|
||||
static symbolS * find_symbol_matching_register PARAMS ((expressionS *));
|
||||
|
|
@ -670,8 +670,8 @@ build_insn (opcode, opers, insn)
|
|||
insn = insn | (number << shift);
|
||||
}
|
||||
|
||||
/* kludge: for DIVS, we need to put the operands in twice on the second
|
||||
pass, format is changed to LONG_R to force the second set of operands
|
||||
/* kludge: for DIVS, we need to put the operands in twice on the second
|
||||
pass, format is changed to LONG_R to force the second set of operands
|
||||
to not be shifted over 15. */
|
||||
if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L))
|
||||
insn = build_insn (opcode, opers, insn);
|
||||
|
|
@ -728,8 +728,8 @@ write_1_short (opcode, insn, fx)
|
|||
if (opcode->exec_type & PARONLY)
|
||||
as_fatal (_("Instruction must be executed in parallel with another instruction."));
|
||||
|
||||
/* The other container needs to be NOP.
|
||||
According to 4.3.1: for FM=00, sub-instructions performed only by IU
|
||||
/* The other container needs to be NOP.
|
||||
According to 4.3.1: for FM=00, sub-instructions performed only by IU
|
||||
cannot be encoded in L-container. */
|
||||
if (opcode->unit == IU)
|
||||
insn |= FM00 | (NOP << 15); /* Right container. */
|
||||
|
|
@ -944,7 +944,7 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
|
|||
/* If this is auto parallization, and either instruction is a branch,
|
||||
don't parallel. */
|
||||
if (exec_type == PACK_UNSPEC
|
||||
&& (op1->exec_type & (ALONE | BRANCH)
|
||||
&& (op1->exec_type & (ALONE | BRANCH)
|
||||
|| op2->exec_type & (ALONE | BRANCH)))
|
||||
return 0;
|
||||
|
||||
|
|
@ -963,8 +963,8 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
|
|||
and the second reads the PSW (which includes C, F0, and F1), then
|
||||
they cannot operate safely in parallel. */
|
||||
|
||||
/* The bitmasks (mod and used) look like this (bit 31 = MSB).
|
||||
r0-r15 0-15
|
||||
/* The bitmasks (mod and used) look like this (bit 31 = MSB).
|
||||
r0-r15 0-15
|
||||
a0-a1 16-17
|
||||
cr (not psw) 18
|
||||
psw 19
|
||||
|
|
@ -1051,7 +1051,7 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
|
|||
/* Determine if there are any resource conflicts among two manually
|
||||
parallelized instructions. Some of this was lifted from parallel_ok. */
|
||||
|
||||
static void
|
||||
static void
|
||||
check_resource_conflict (op1, insn1, op2, insn2)
|
||||
struct d10v_opcode *op1, *op2;
|
||||
unsigned long insn1, insn2;
|
||||
|
|
@ -1127,35 +1127,35 @@ check_resource_conflict (op1, insn1, op2, insn2)
|
|||
if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
|
||||
regno += 16;
|
||||
else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
|
||||
{
|
||||
{
|
||||
if (regno == 0)
|
||||
regno = 19;
|
||||
else
|
||||
regno = 18;
|
||||
regno = 18;
|
||||
}
|
||||
else if (flags & OPERAND_FFLAG)
|
||||
regno = 22;
|
||||
else if (flags & OPERAND_CFLAG)
|
||||
regno = 21;
|
||||
|
||||
if ( flags & OPERAND_DEST )
|
||||
|
||||
if ( flags & OPERAND_DEST )
|
||||
{
|
||||
mod[j] |= 1 << regno;
|
||||
if (flags & OPERAND_EVEN)
|
||||
mod[j] |= 1 << (regno + 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
used[j] |= 1 << regno ;
|
||||
if (flags & OPERAND_EVEN)
|
||||
used[j] |= 1 << (regno + 1);
|
||||
else
|
||||
{
|
||||
used[j] |= 1 << regno ;
|
||||
if (flags & OPERAND_EVEN)
|
||||
used[j] |= 1 << (regno + 1);
|
||||
|
||||
/* Auto inc/dec also modifies the register. */
|
||||
if (op->operands[i+1] != 0
|
||||
&& (d10v_operands[op->operands[i+1]].flags
|
||||
& (OPERAND_PLUS | OPERAND_MINUS)) != 0)
|
||||
mod[j] |= 1 << regno;
|
||||
}
|
||||
/* Auto inc/dec also modifies the register. */
|
||||
if (op->operands[i+1] != 0
|
||||
&& (d10v_operands[op->operands[i+1]].flags
|
||||
& (OPERAND_PLUS | OPERAND_MINUS)) != 0)
|
||||
mod[j] |= 1 << regno;
|
||||
}
|
||||
}
|
||||
else if (flags & OPERAND_ATMINUS)
|
||||
{
|
||||
|
|
@ -1294,7 +1294,7 @@ md_assemble (str)
|
|||
d10v_cleanup ();
|
||||
|
||||
if (prev_opcode
|
||||
&& (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
|
||||
&& (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
|
||||
fixups)))
|
||||
{
|
||||
/* No instructions saved. */
|
||||
|
|
@ -1520,7 +1520,7 @@ find_opcode (opcode, myops)
|
|||
}
|
||||
|
||||
match = 0;
|
||||
|
||||
|
||||
/* Now search the opcode table table for one with operands
|
||||
that matches what we've got. */
|
||||
while (!match)
|
||||
|
|
@ -1562,19 +1562,19 @@ find_opcode (opcode, myops)
|
|||
break;
|
||||
}
|
||||
|
||||
/* Unfortunatly, for the indirect operand in instructions such
|
||||
as ``ldb r1, @(c,r14)'' this function can be passed
|
||||
X_op == O_register (because 'c' is a valid register name).
|
||||
However we cannot just ignore the case when X_op == O_register
|
||||
but flags & OPERAND_REG is null, so we check to see if a symbol
|
||||
of the same name as the register exists. If the symbol does
|
||||
exist, then the parser was unable to distinguish the two cases
|
||||
/* Unfortunatly, for the indirect operand in instructions such
|
||||
as ``ldb r1, @(c,r14)'' this function can be passed
|
||||
X_op == O_register (because 'c' is a valid register name).
|
||||
However we cannot just ignore the case when X_op == O_register
|
||||
but flags & OPERAND_REG is null, so we check to see if a symbol
|
||||
of the same name as the register exists. If the symbol does
|
||||
exist, then the parser was unable to distinguish the two cases
|
||||
and we fix things here. (Ref: PR14826) */
|
||||
|
||||
if (!(flags & OPERAND_REG) && (X_op == O_register))
|
||||
{
|
||||
symbolS * sym;
|
||||
|
||||
|
||||
sym = find_symbol_matching_register (& myops[i]);
|
||||
|
||||
if (sym != NULL)
|
||||
|
|
@ -1672,9 +1672,9 @@ tc_gen_reloc (seg, fixp)
|
|||
if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|
||||
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
|
||||
reloc->address = fixp->fx_offset;
|
||||
|
||||
|
||||
reloc->addend = fixp->fx_addnumber;
|
||||
|
||||
|
||||
return reloc;
|
||||
}
|
||||
|
||||
|
|
@ -1769,13 +1769,13 @@ md_apply_fix3 (fixP, valP, seg)
|
|||
XXX - Do we have to worry about branches to a symbol + offset ? */
|
||||
if (fixP->fx_addsy != NULL
|
||||
&& S_IS_EXTERN (fixP->fx_addsy) )
|
||||
{
|
||||
segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
|
||||
segment_info_type *segf = seg_info(fseg);
|
||||
{
|
||||
segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
|
||||
segment_info_type *segf = seg_info(fseg);
|
||||
|
||||
if ( segf && segf->sym != fixP->fx_addsy)
|
||||
value = 0;
|
||||
}
|
||||
}
|
||||
/* Drop through. */
|
||||
case BFD_RELOC_D10V_18:
|
||||
/* Instruction addresses are always right-shifted by 2. */
|
||||
|
|
@ -1789,9 +1789,9 @@ md_apply_fix3 (fixP, valP, seg)
|
|||
rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep");
|
||||
repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi");
|
||||
if ((insn & FM11) == FM11
|
||||
&& ((repi != NULL
|
||||
&& ((repi != NULL
|
||||
&& (insn & repi->mask) == (unsigned) repi->opcode)
|
||||
|| (rep != NULL
|
||||
|| (rep != NULL
|
||||
&& (insn & rep->mask) == (unsigned) rep->opcode))
|
||||
&& value < 4)
|
||||
as_fatal
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* tc-d30v.c -- Assembler code for the Mitsubishi D30V
|
||||
Copyright 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
|
||||
Copyright 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
|
|
@ -246,7 +246,7 @@ check_range (num, bits, flags)
|
|||
if (bits == 32)
|
||||
{
|
||||
if (sizeof (unsigned long) * CHAR_BIT == 32)
|
||||
return 0;
|
||||
return 0;
|
||||
|
||||
/* We don't record signed or unsigned for 32-bit quantities.
|
||||
Allow either. */
|
||||
|
|
@ -1211,7 +1211,7 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
|
|||
return 0;
|
||||
}
|
||||
else
|
||||
if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0)
|
||||
if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0)
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* tc-h8300.c -- Assemble code for the Hitachi H8/300
|
||||
Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001
|
||||
Free Software Foundation, Inc.
|
||||
Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
|
||||
2001, 2002 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
|
|
@ -1491,7 +1491,7 @@ md_section_align (seg, size)
|
|||
valueT size;
|
||||
{
|
||||
return ((size + (1 << section_alignment[(int) seg]) - 1)
|
||||
& (-1 << section_alignment[(int) seg]));
|
||||
& (-1 << section_alignment[(int) seg]));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1289,10 +1289,10 @@ pa_undefine_label ()
|
|||
{
|
||||
if (1
|
||||
#ifdef OBJ_SOM
|
||||
&& current_space == label_chain->lss_space && label_chain->lss_label
|
||||
&& current_space == label_chain->lss_space && label_chain->lss_label
|
||||
#endif
|
||||
#ifdef OBJ_ELF
|
||||
&& now_seg == label_chain->lss_segment && label_chain->lss_label
|
||||
&& now_seg == label_chain->lss_segment && label_chain->lss_label
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
|
@ -2334,16 +2334,16 @@ pa_ip (str)
|
|||
args++;
|
||||
switch (*args)
|
||||
{
|
||||
/* Handle FP compare conditions. */
|
||||
case 'f':
|
||||
cond = pa_parse_fp_cmp_cond (&s);
|
||||
INSERT_FIELD_AND_CONTINUE (opcode, cond, 0);
|
||||
/* Handle FP compare conditions. */
|
||||
case 'f':
|
||||
cond = pa_parse_fp_cmp_cond (&s);
|
||||
INSERT_FIELD_AND_CONTINUE (opcode, cond, 0);
|
||||
|
||||
/* Handle an add condition. */
|
||||
case 'A':
|
||||
case 'a':
|
||||
cmpltr = 0;
|
||||
flag = 0;
|
||||
cmpltr = 0;
|
||||
flag = 0;
|
||||
if (*s == ',')
|
||||
{
|
||||
s++;
|
||||
|
|
@ -4240,8 +4240,8 @@ tc_gen_reloc (section, fixp)
|
|||
case R_N0SEL:
|
||||
case R_N1SEL:
|
||||
/* There is no symbol or addend associated with these fixups. */
|
||||
relocs[i]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
|
||||
*relocs[i]->sym_ptr_ptr = symbol_get_bfdsym (dummy_symbol);
|
||||
relocs[i]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
|
||||
*relocs[i]->sym_ptr_ptr = symbol_get_bfdsym (dummy_symbol);
|
||||
relocs[i]->addend = 0;
|
||||
break;
|
||||
|
||||
|
|
@ -4249,8 +4249,8 @@ tc_gen_reloc (section, fixp)
|
|||
case R_ENTRY:
|
||||
case R_EXIT:
|
||||
/* There is no symbol associated with these fixups. */
|
||||
relocs[i]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
|
||||
*relocs[i]->sym_ptr_ptr = symbol_get_bfdsym (dummy_symbol);
|
||||
relocs[i]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
|
||||
*relocs[i]->sym_ptr_ptr = symbol_get_bfdsym (dummy_symbol);
|
||||
relocs[i]->addend = fixp->fx_offset;
|
||||
break;
|
||||
|
||||
|
|
@ -5227,7 +5227,7 @@ pa_get_absolute_expression (insn, strp)
|
|||
input_line_pointer = *strp;
|
||||
s = *strp;
|
||||
while (*s != ',' && *s != ' ' && *s != '\t')
|
||||
s++;
|
||||
s++;
|
||||
|
||||
c = *s;
|
||||
*s = 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue