Add support for the Q extension to the RISCV ISA.
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
extension.
(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
enabled and no other ABI is specified.
include * opcode/riscv-opc.h: Add support for the "q" ISA extension.
opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
extension.
* riscv-opcodes/all-opcodes: Likewise.
This commit is contained in:
Kito Cheng
Nick Clifton
parent
de1010f408
commit
cc917fd93d
@ -1,3 +1,10 @@
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
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extension.
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(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
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enabled and no other ABI is specified.
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2017-01-03 Dimitar Dimitrov <dimitar@dinux.eu>
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* config/tc-pru.c (md_number_to_chars): Fix parameter to be
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@ -197,6 +197,12 @@ riscv_set_arch (const char *s)
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all_subsets++;
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p++;
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}
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else if (*p == 'q')
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{
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const char subset[] = {*p, 0};
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riscv_add_subset (subset);
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p++;
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}
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else
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as_fatal ("-march=%s: unsupported ISA subset `%c'", s, *p);
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}
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@ -1817,8 +1823,12 @@ riscv_after_parse_args (void)
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float_abi = FLOAT_ABI_SOFT;
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for (subset = riscv_subsets; subset != NULL; subset = subset->next)
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if (strcasecmp (subset->name, "D") == 0)
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float_abi = FLOAT_ABI_DOUBLE;
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{
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if (strcasecmp (subset->name, "D") == 0)
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float_abi = FLOAT_ABI_DOUBLE;
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if (strcasecmp (subset->name, "Q") == 0)
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float_abi = FLOAT_ABI_QUAD;
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}
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}
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/* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
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@ -1,3 +1,7 @@
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* opcode/riscv-opc.h: Add support for the "q" ISA extension.
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2017-01-03 Nick Clifton <nickc@redhat.com>
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* dwarf2.def: Sync with mainline gcc sources
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@ -285,6 +285,34 @@
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#define MASK_FCVT_D_S 0xfff0007f
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#define MATCH_FSQRT_D 0x5a000053
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#define MASK_FSQRT_D 0xfff0007f
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#define MATCH_FADD_Q 0x6000053
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#define MASK_FADD_Q 0xfe00007f
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#define MATCH_FSUB_Q 0xe000053
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#define MASK_FSUB_Q 0xfe00007f
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#define MATCH_FMUL_Q 0x16000053
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#define MASK_FMUL_Q 0xfe00007f
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#define MATCH_FDIV_Q 0x1e000053
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#define MASK_FDIV_Q 0xfe00007f
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#define MATCH_FSGNJ_Q 0x26000053
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#define MASK_FSGNJ_Q 0xfe00707f
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#define MATCH_FSGNJN_Q 0x26001053
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#define MASK_FSGNJN_Q 0xfe00707f
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#define MATCH_FSGNJX_Q 0x26002053
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#define MASK_FSGNJX_Q 0xfe00707f
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#define MATCH_FMIN_Q 0x2e000053
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#define MASK_FMIN_Q 0xfe00707f
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#define MATCH_FMAX_Q 0x2e001053
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#define MASK_FMAX_Q 0xfe00707f
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#define MATCH_FCVT_S_Q 0x40300053
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#define MASK_FCVT_S_Q 0xfff0007f
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#define MATCH_FCVT_Q_S 0x46000053
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#define MASK_FCVT_Q_S 0xfff0007f
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#define MATCH_FCVT_D_Q 0x42300053
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#define MASK_FCVT_D_Q 0xfff0007f
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#define MATCH_FCVT_Q_D 0x46100053
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#define MASK_FCVT_Q_D 0xfff0007f
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#define MATCH_FSQRT_Q 0x5e000053
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#define MASK_FSQRT_Q 0xfff0007f
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#define MATCH_FLE_S 0xa0000053
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#define MASK_FLE_S 0xfe00707f
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#define MATCH_FLT_S 0xa0001053
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@ -297,6 +325,12 @@
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#define MASK_FLT_D 0xfe00707f
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#define MATCH_FEQ_D 0xa2002053
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#define MASK_FEQ_D 0xfe00707f
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#define MATCH_FLE_Q 0xa6000053
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#define MASK_FLE_Q 0xfe00707f
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#define MATCH_FLT_Q 0xa6001053
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#define MASK_FLT_Q 0xfe00707f
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#define MATCH_FEQ_Q 0xa6002053
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#define MASK_FEQ_Q 0xfe00707f
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#define MATCH_FCVT_W_S 0xc0000053
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#define MASK_FCVT_W_S 0xfff0007f
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#define MATCH_FCVT_WU_S 0xc0100053
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@ -321,6 +355,18 @@
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#define MASK_FMV_X_D 0xfff0707f
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#define MATCH_FCLASS_D 0xe2001053
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#define MASK_FCLASS_D 0xfff0707f
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#define MATCH_FCVT_W_Q 0xc6000053
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#define MASK_FCVT_W_Q 0xfff0007f
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#define MATCH_FCVT_WU_Q 0xc6100053
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#define MASK_FCVT_WU_Q 0xfff0007f
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#define MATCH_FCVT_L_Q 0xc6200053
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#define MASK_FCVT_L_Q 0xfff0007f
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#define MATCH_FCVT_LU_Q 0xc6300053
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#define MASK_FCVT_LU_Q 0xfff0007f
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#define MATCH_FMV_X_Q 0xe6000053
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#define MASK_FMV_X_Q 0xfff0707f
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#define MATCH_FCLASS_Q 0xe6001053
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#define MASK_FCLASS_Q 0xfff0707f
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#define MATCH_FCVT_S_W 0xd0000053
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#define MASK_FCVT_S_W 0xfff0007f
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#define MATCH_FCVT_S_WU 0xd0100053
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@ -341,14 +387,28 @@
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#define MASK_FCVT_D_LU 0xfff0007f
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#define MATCH_FMV_D_X 0xf2000053
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#define MASK_FMV_D_X 0xfff0707f
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#define MATCH_FCVT_Q_W 0xd6000053
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#define MASK_FCVT_Q_W 0xfff0007f
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#define MATCH_FCVT_Q_WU 0xd6100053
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#define MASK_FCVT_Q_WU 0xfff0007f
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#define MATCH_FCVT_Q_L 0xd6200053
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#define MASK_FCVT_Q_L 0xfff0007f
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#define MATCH_FCVT_Q_LU 0xd6300053
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#define MASK_FCVT_Q_LU 0xfff0007f
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#define MATCH_FMV_Q_X 0xf6000053
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#define MASK_FMV_Q_X 0xfff0707f
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#define MATCH_FLW 0x2007
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#define MASK_FLW 0x707f
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#define MATCH_FLD 0x3007
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#define MASK_FLD 0x707f
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#define MATCH_FLQ 0x4007
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#define MASK_FLQ 0x707f
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#define MATCH_FSW 0x2027
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#define MASK_FSW 0x707f
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#define MATCH_FSD 0x3027
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#define MASK_FSD 0x707f
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#define MATCH_FSQ 0x4027
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#define MASK_FSQ 0x707f
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#define MATCH_FMADD_S 0x43
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#define MASK_FMADD_S 0x600007f
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#define MATCH_FMSUB_S 0x47
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@ -365,6 +425,14 @@
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#define MASK_FNMSUB_D 0x600007f
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#define MATCH_FNMADD_D 0x200004f
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#define MASK_FNMADD_D 0x600007f
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#define MATCH_FMADD_Q 0x6000043
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#define MASK_FMADD_Q 0x600007f
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#define MATCH_FMSUB_Q 0x6000047
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#define MASK_FMSUB_Q 0x600007f
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#define MATCH_FNMSUB_Q 0x600004b
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#define MASK_FNMSUB_Q 0x600007f
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#define MATCH_FNMADD_Q 0x600004f
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#define MASK_FNMADD_Q 0x600007f
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#define MATCH_C_ADDI4SPN 0x0
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#define MASK_C_ADDI4SPN 0xe003
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#define MATCH_C_FLD 0x2000
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@ -844,12 +912,29 @@ DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
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DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
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DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
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DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
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DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
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DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
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DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
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DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
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DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)
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DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)
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DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)
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DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
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DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
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DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)
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DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
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DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
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DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
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DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
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DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
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DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
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DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
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DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
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DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
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DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
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DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
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DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
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DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
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DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
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DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
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DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
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@ -862,6 +947,12 @@ DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
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DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
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DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
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DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
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DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
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DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
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DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
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DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
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DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
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DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
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DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
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DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
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DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
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@ -872,10 +963,17 @@ DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
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DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
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DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
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DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
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DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
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DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
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DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
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DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
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DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
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DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
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DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
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DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
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DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
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DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
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DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
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DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
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DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
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DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
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@ -884,6 +982,10 @@ DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
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DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
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DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
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DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
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DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
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DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
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DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
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DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
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DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
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DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
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DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
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@ -323,8 +323,10 @@ enum
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M_SD,
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M_FLW,
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M_FLD,
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M_FLQ,
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M_FSW,
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M_FSD,
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M_FSQ,
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M_CALL,
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M_J,
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M_LI,
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@ -1,3 +1,9 @@
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
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extension.
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* riscv-opcodes/all-opcodes: Likewise.
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2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
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* riscv-dis.c (print_insn_args): Add fall through comment.
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@ -547,6 +547,66 @@ const struct riscv_opcode riscv_opcodes[] =
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{"fcvt.d.lu", "64D", "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
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{"fcvt.d.lu", "64D", "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
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/* Quad-precision floating-point instruction subset */
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{"flq", "Q", "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, 0 },
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{"flq", "Q", "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO },
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{"fsq", "Q", "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, 0 },
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{"fsq", "Q", "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO },
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{"fmv.q", "Q", "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
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{"fneg.q", "Q", "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
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{"fabs.q", "Q", "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
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{"fsgnj.q", "Q", "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
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{"fsgnjn.q", "Q", "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
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{"fsgnjx.q", "Q", "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
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{"fadd.q", "Q", "D,S,T", MATCH_FADD_Q | MASK_RM, MASK_FADD_Q | MASK_RM, match_opcode, 0 },
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{"fadd.q", "Q", "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
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{"fsub.q", "Q", "D,S,T", MATCH_FSUB_Q | MASK_RM, MASK_FSUB_Q | MASK_RM, match_opcode, 0 },
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{"fsub.q", "Q", "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
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{"fmul.q", "Q", "D,S,T", MATCH_FMUL_Q | MASK_RM, MASK_FMUL_Q | MASK_RM, match_opcode, 0 },
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{"fmul.q", "Q", "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
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{"fdiv.q", "Q", "D,S,T", MATCH_FDIV_Q | MASK_RM, MASK_FDIV_Q | MASK_RM, match_opcode, 0 },
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{"fdiv.q", "Q", "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
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{"fsqrt.q", "Q", "D,S", MATCH_FSQRT_Q | MASK_RM, MASK_FSQRT_Q | MASK_RM, match_opcode, 0 },
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{"fsqrt.q", "Q", "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
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{"fmin.q", "Q", "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
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{"fmax.q", "Q", "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
|
||||
{"fmadd.q", "Q", "D,S,T,R", MATCH_FMADD_Q | MASK_RM, MASK_FMADD_Q | MASK_RM, match_opcode, 0 },
|
||||
{"fmadd.q", "Q", "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
|
||||
{"fnmadd.q", "Q", "D,S,T,R", MATCH_FNMADD_Q | MASK_RM, MASK_FNMADD_Q | MASK_RM, match_opcode, 0 },
|
||||
{"fnmadd.q", "Q", "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
|
||||
{"fmsub.q", "Q", "D,S,T,R", MATCH_FMSUB_Q | MASK_RM, MASK_FMSUB_Q | MASK_RM, match_opcode, 0 },
|
||||
{"fmsub.q", "Q", "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
|
||||
{"fnmsub.q", "Q", "D,S,T,R", MATCH_FNMSUB_Q | MASK_RM, MASK_FNMSUB_Q | MASK_RM, match_opcode, 0 },
|
||||
{"fnmsub.q", "Q", "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
|
||||
{"fcvt.w.q", "Q", "d,S", MATCH_FCVT_W_Q | MASK_RM, MASK_FCVT_W_Q | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.w.q", "Q", "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
|
||||
{"fcvt.wu.q", "Q", "d,S", MATCH_FCVT_WU_Q | MASK_RM, MASK_FCVT_WU_Q | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.wu.q", "Q", "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
|
||||
{"fcvt.q.w", "Q", "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.q.wu", "Q", "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.q.s", "Q", "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.q.d", "Q", "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.s.q", "Q", "D,S", MATCH_FCVT_S_Q | MASK_RM, MASK_FCVT_S_Q | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.s.q", "Q", "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
|
||||
{"fcvt.d.q", "Q", "D,S", MATCH_FCVT_D_Q | MASK_RM, MASK_FCVT_D_Q | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.d.q", "Q", "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
|
||||
{"fclass.q", "Q", "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
|
||||
{"feq.q", "Q", "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
|
||||
{"flt.q", "Q", "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
|
||||
{"fle.q", "Q", "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
|
||||
{"fgt.q", "Q", "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
|
||||
{"fge.q", "Q", "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
|
||||
{"fmv.x.q", "64Q", "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
|
||||
{"fmv.q.x", "64Q", "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
|
||||
{"fcvt.l.q", "64Q", "d,S", MATCH_FCVT_L_Q | MASK_RM, MASK_FCVT_L_Q | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.l.q", "64Q", "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
|
||||
{"fcvt.lu.q", "64Q", "d,S", MATCH_FCVT_LU_Q | MASK_RM, MASK_FCVT_LU_Q | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.lu.q", "64Q", "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
|
||||
{"fcvt.q.l", "64Q", "D,s", MATCH_FCVT_Q_L | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.q.l", "64Q", "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
|
||||
{"fcvt.q.lu", "64Q", "D,s", MATCH_FCVT_Q_LU | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.q.lu", "64Q", "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
|
||||
|
||||
/* Compressed instructions. */
|
||||
{"c.ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
|
||||
{"c.jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user