[AArch64] Rename +bitperm to +sve2-bitperm
After some discussion, we've decided to rename the +bitperm feature flag to +sve2-bitperm, so that it's consistent with the other SVE2 feature flags. The associated internal macros already used "SVE2_BITPERM", so only the feature flag itself needs to change. 2019-07-19 Richard Sandiford <richard.sandiford@arm.com> gas/ * doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm. * config/tc-aarch64.c (aarch64_features): Likewise. * testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly. * testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise. * testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise. * testsuite/gas/aarch64/illegal-sve2.d: Likewise. * testsuite/gas/aarch64/sve2.d: Likewise.
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@ -1,3 +1,13 @@
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2019-07-19 Richard Sandiford <richard.sandiford@arm.com>
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* doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm.
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* config/tc-aarch64.c (aarch64_features): Likewise.
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* testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly.
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* testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise.
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* testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise.
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* testsuite/gas/aarch64/illegal-sve2.d: Likewise.
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* testsuite/gas/aarch64/sve2.d: Likewise.
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2019-07-19 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
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@ -8963,7 +8963,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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{"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_SVE2
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| AARCH64_FEATURE_SHA3, 0)},
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{"bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0),
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{"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)},
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{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
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};
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@ -198,7 +198,7 @@ automatically cause those extensions to be disabled.
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@tab Enable Transactional Memory Extensions.
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@item @code{sve2} @tab ARMv8-A @tab No
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@tab Enable the SVE2 Extension.
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@item @code{bitperm} @tab ARMv8-A @tab No
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@item @code{sve2-bitperm} @tab ARMv8-A @tab No
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@tab Enable SVE2 BITPERM Extension.
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@item @code{sve2-sm4} @tab ARMv8-A @tab No
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@tab Enable SVE2 SM4 Extension.
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@ -1,5 +1,5 @@
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#name: Missing SVE2 AES argument
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#as: -march=armv8-a+sve2+sve2-sm4+sve2-sha3+bitperm
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#as: -march=armv8-a+sve2+sve2-sm4+sve2-sha3+sve2-bitperm
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#source: sve2.s
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#error: [^ :]+: Assembler messages:
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `aesd z17\.b,z17\.b,z21\.b'
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@ -1,5 +1,5 @@
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#name: Missing SVE2 SHA3 argument
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#as: -march=armv8-a+sve2+sve2-sm4+sve2-aes+bitperm
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#as: -march=armv8-a+sve2+sve2-sm4+sve2-aes+sve2-bitperm
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#source: sve2.s
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#error: [^ :]+: Assembler messages:
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `rax1 z17\.d,z21\.d,z27\.d'
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@ -1,5 +1,5 @@
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#name: Missing SVE2 SM4 argument
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#as: -march=armv8-a+sve2+sve2-sha3+sve2-aes+bitperm
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#as: -march=armv8-a+sve2+sve2-sha3+sve2-aes+sve2-bitperm
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#source: sve2.s
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#error: [^ :]+: Assembler messages:
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `sm4e z17\.s,z17\.s,z21\.s'
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@ -1,4 +1,4 @@
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#name: Illegal SVE2
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#as: -march=armv8-a+sve2+sve2-aes+sve2-sm4+sve2-sha3+bitperm
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#as: -march=armv8-a+sve2+sve2-aes+sve2-sm4+sve2-sha3+sve2-bitperm
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#source: illegal-sve2.s
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#error_output: illegal-sve2.l
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@ -1,4 +1,4 @@
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#as: -march=armv8-a+sve2+sve2-aes+sve2-sm4+sve2-sha3+bitperm
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#as: -march=armv8-a+sve2+sve2-aes+sve2-sm4+sve2-sha3+sve2-bitperm
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#objdump: -dr
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[^:]+: file format .*
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