[binutils][arm] Arm CDE CX*A instructions allow condition code
The implementation of the Arm CDE CX*A instructions doesn't allow a condition code on the instructions but does allow the instruction in an ITBlock. The specification has been recently updated, though this is yet to be published. The instructions now should allow a suffix, and should behave in the standard way around ITBlocks. This patch removes the custom pred_instruction_type and handling for these instructions, and uses the standard INSIDE_IT_INSN predication type to describe the new instructions. gas/ChangeLog: 2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (enum pred_instruction_type): Remove NEUTRAL_IT_NO_VPT_INSN predication type. (cxn_handle_predication): Modify to require condition suffixes. (handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases. * testsuite/gas/arm/cde-scalar.s: Update test. * testsuite/gas/arm/cde-warnings.l: Update test. * testsuite/gas/arm/cde-warnings.s: Update test.
This commit is contained in:
Matthew Malcomson
parent
0dce428051
commit
cceb53b884
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@ -1,3 +1,13 @@
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2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com>
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* config/tc-arm.c (enum pred_instruction_type): Remove
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NEUTRAL_IT_NO_VPT_INSN predication type.
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(cxn_handle_predication): Modify to require condition suffixes.
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(handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases.
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* testsuite/gas/arm/cde-scalar.s: Update test.
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* testsuite/gas/arm/cde-warnings.l: Update test.
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* testsuite/gas/arm/cde-warnings.s: Update test.
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2020-02-26 Alan Modra <amodra@gmail.com>
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* config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use
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@ -506,8 +506,6 @@ enum pred_instruction_type
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MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
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a predication code. */
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MVE_UNPREDICABLE_INSN, /* MVE instruction that is non-predicable. */
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NEUTRAL_IT_NO_VPT_INSN, /* Instruction that can be either inside or outside
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an IT block, but must not be in a VPT block. */
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};
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/* The maximum number of operands we need. */
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@ -21674,15 +21672,13 @@ cde_handle_coproc (void)
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static void
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cxn_handle_predication (bfd_boolean is_accum)
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{
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/* This function essentially checks for a suffix, not whether the instruction
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is inside an IT block or not.
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The CX* instructions should never have a conditional suffix -- this is not
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mentioned in the syntax. */
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if (conditional_insn ())
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if (is_accum && conditional_insn ())
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set_pred_insn_type (INSIDE_IT_INSN);
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else if (conditional_insn ())
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/* conditional_insn essentially checks for a suffix, not whether the
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instruction is inside an IT block or not.
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The non-accumulator versions should not have suffixes. */
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inst.error = BAD_SYNTAX;
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/* Here we ensure that if the current element */
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else if (is_accum)
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set_pred_insn_type (NEUTRAL_IT_NO_VPT_INSN);
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else
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set_pred_insn_type (OUTSIDE_PRED_INSN);
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}
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@ -22980,7 +22976,6 @@ handle_pred_state (void)
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gas_assert (0);
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case IF_INSIDE_IT_LAST_INSN:
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case NEUTRAL_IT_INSN:
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case NEUTRAL_IT_NO_VPT_INSN:
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break;
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case VPT_INSN:
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@ -23044,12 +23039,6 @@ handle_pred_state (void)
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close_automatic_it_block ();
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break;
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case NEUTRAL_IT_NO_VPT_INSN:
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if (now_pred.type == VECTOR_PRED)
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{
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inst.error = BAD_NO_VPT;
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break;
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}
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/* Fallthrough. */
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case NEUTRAL_IT_INSN:
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now_pred.block_length++;
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@ -23234,13 +23223,6 @@ handle_pred_state (void)
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}
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break;
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case NEUTRAL_IT_NO_VPT_INSN:
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if (now_pred.type == VECTOR_PRED)
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{
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inst.error = BAD_NO_VPT;
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break;
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}
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/* Fallthrough. */
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case NEUTRAL_IT_INSN:
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/* The BKPT instruction is unconditional even in a IT or VPT
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block. */
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@ -37,7 +37,7 @@ cx1a p0, APSR_nzcv, #0
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cx1a p0, r9, #0
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it ne
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cx1a p0, r0, #0
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cx1ane p0, r0, #0
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# cx1d{a} encoding of following form:
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# 111a111000iiiiiidddd0pppi1iiiiii
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@ -65,7 +65,7 @@ cx1da p7, r0, r1, #0
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cx1da p0, r10, r11, #0
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it ne
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cx1da p0, r0, r1, #0
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cx1dane p0, r0, r1, #0
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# cx2{a} Has arguments of the following form:
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@ -100,7 +100,7 @@ cx2a p0, r0, APSR_nzcv, #0
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cx2a p0, r0, r9, #0
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it ne
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cx2a p0, r0, r0, #0
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cx2ane p0, r0, r0, #0
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# cx2d{a} encoding has following form:
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# 111a111001iinnnndddd0pppi1iiiiii
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@ -168,7 +168,7 @@ cx3a p0, r0, r0, APSR_nzcv, #0
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cx3a p0, r0, r0, r9, #0
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it ne
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cx3a p0, r0, r0, r0, #0
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cx3ane p0, r0, r0, r0, #0
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# cx3d{a} encoding has following form:
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# 111a11101iiinnnnmmmm0pppi1iidddd
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@ -11,7 +11,8 @@
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[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx1a p0,r13,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx1 p0,r0,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx1ne p0,r0,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx1ane p0,r0,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx1a p0,r0,#0'
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[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx1aeq p0,r0,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx1 p1,r0,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx1a p1,r0,#0'
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[^ :]+:[0-9]+: Error: constant expression required -- `cx1 p0,r0,r0,#0'
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@ -35,8 +36,9 @@
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[^ :]+:[0-9]+: Error: Register must be an even register between r0-r10\. -- `cx1d p0,r13,r14,#0'
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[^ :]+:[0-9]+: Error: Register must be an even register between r0-r10\. -- `cx1da p0,r13,r14,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx1d p0,r0,r1,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx1da p0,r0,r1,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx1dne p0,r0,r1,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx1dane p0,r0,r1,#0'
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[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx1daeq p0,r0,r1,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx1d p1,r0,r1,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx1da p1,r0,r1,#0'
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[^ :]+:[0-9]+: Error: cx1d requires consecutive destination registers\. -- `cx1d p0,r0,r2,#0'
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@ -60,8 +62,9 @@
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[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx2 p0,r0,r13,#0'
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[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx2a p0,r0,r13,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx2 p0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx2a p0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx2ne p0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx2ane p0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx2aeq p0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx2 p1,r0,r0,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx2a p1,r0,r0,#0'
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[^ :]+:[0-9]+: Error: constant expression required -- `cx2 p0,r0,r0,r0,#0'
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@ -93,8 +96,9 @@
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[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx2d p0,r0,r1,r15,#0'
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[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx2da p0,r0,r1,r15,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx2d p0,r0,r1,r0,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx2da p0,r0,r1,r0,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx2dne p0,r0,r1,r0,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx2dane p0,r0,r1,r0,#0'
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[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx2daeq p0,r0,r1,r0,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx2d p1,r0,r1,r0,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx2da p1,r0,r1,r0,#0'
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[^ :]+:[0-9]+: Error: cx2d requires consecutive destination registers\. -- `cx2d p0,r0,r2,r0,#0'
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@ -122,8 +126,9 @@
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[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx3 p0,r0,r0,r13,#0'
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[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx3a p0,r0,r0,r13,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx3 p0,r0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx3a p0,r0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx3ne p0,r0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx3ane p0,r0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx3aeq p0,r0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx3 p1,r0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx3a p1,r0,r0,r0,#0'
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[^ :]+:[0-9]+: Error: constant expression required -- `cx3 p0,r0,r0,r0,r0,#0'
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@ -163,8 +168,9 @@
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[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx3d p0,r0,r1,r0,r15,#0'
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[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx3da p0,r0,r1,r0,r15,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx3d p0,r0,r1,r0,r0,#0'
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[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx3da p0,r0,r1,r0,r0,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx3dne p0,r0,r1,r0,r0,#0'
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[^ :]+:[0-9]+: Error: syntax error -- `cx3dane p0,r0,r1,r0,r0,#0'
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[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx3daeq p0,r0,r1,r0,r0,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx3d p1,r0,r1,r0,r0,#0'
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[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx3da p1,r0,r1,r0,r0,#0'
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[^ :]+:[0-9]+: Error: cx3d requires consecutive destination registers\. -- `cx3d p0,r0,r2,r0,r0,#0'
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@ -23,10 +23,11 @@ cx1a p0, r16, #0
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cx1 p0, r13, #0
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cx1a p0, r13, #0
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ittt ne
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itttt ne
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cx1 p0, r0, #0
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cx1ne p0, r0, #0
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cx1ane p0, r0, #0
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cx1a p0, r0, #0
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cx1aeq p0, r0, #0
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cx1 p1, r0, #0
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cx1a p1, r0, #0
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@ -73,10 +74,11 @@ cx1da p0, r9, r10, #0
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cx1d p0, r13, r14, #0
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cx1da p0, r13, r14, #0
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ittt ne
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itttt ne
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cx1d p0, r0, r1, #0
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cx1da p0, r0, r1, #0
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cx1dne p0, r0, r1, #0
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cx1dane p0, r0, r1, #0
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cx1daeq p0, r0, r1, #0
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cx1d p1, r0, r1, #0
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cx1da p1, r0, r1, #0
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@ -122,10 +124,11 @@ cx2a p0, r13, r0, #0
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cx2 p0, r0, r13, #0
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cx2a p0, r0, r13, #0
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ittt ne
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itttt ne
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cx2 p0, r0, r0, #0
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cx2a p0, r0, r0, #0
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cx2ne p0, r0, r0, #0
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cx2ane p0, r0, r0, #0
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cx2aeq p0, r0, r0, #0
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cx2 p1, r0, r0, #0
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cx2a p1, r0, r0, #0
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@ -184,10 +187,11 @@ cx2da p0, r0, r1, r13, #0
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cx2d p0, r0, r1, r15, #0
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cx2da p0, r0, r1, r15, #0
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ittt ne
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itttt ne
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cx2d p0, r0, r1, r0, #0
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cx2da p0, r0, r1, r0, #0
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cx2dne p0, r0, r1, r0, #0
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cx2dane p0, r0, r1, r0, #0
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cx2daeq p0, r0, r1, r0, #0
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cx2d p1, r0, r1, r0, #0
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cx2da p1, r0, r1, r0, #0
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@ -240,10 +244,11 @@ cx3a p0, r0, r13, r0, #0
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cx3 p0, r0, r0, r13, #0
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cx3a p0, r0, r0, r13, #0
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ittt ne
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itttt ne
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cx3 p0, r0, r0, r0, #0
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cx3a p0, r0, r0, r0, #0
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cx3ne p0, r0, r0, r0, #0
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cx3ane p0, r0, r0, r0, #0
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cx3aeq p0, r0, r0, r0, #0
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cx3 p1, r0, r0, r0, #0
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cx3a p1, r0, r0, r0, #0
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@ -317,10 +322,11 @@ cx3da p0, r0, r1, r15, r0, #0
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cx3d p0, r0, r1, r0, r15, #0
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cx3da p0, r0, r1, r0, r15, #0
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ittt ne
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itttt ne
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cx3d p0, r0, r1, r0, r0, #0
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cx3da p0, r0, r1, r0, r0, #0
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cx3dne p0, r0, r1, r0, r0, #0
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cx3dane p0, r0, r1, r0, r0, #0
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cx3daeq p0, r0, r1, r0, r0, #0
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cx3d p1, r0, r1, r0, r0, #0
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cx3da p1, r0, r1, r0, r0, #0
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