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sim: bfin: pass up result2/errcode with libgloss syscalls 

Now that the Blackfin libgloss code extracts the 2nd result and the
error code from the R1/R2 registers, have the sim fill them up.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2011-06-22 04:21:29 +00:00
parent 8eebce8e67
commit ce2486ab20
2 changed files with 7 additions and 2 deletions
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5
sim/bfin/ChangeLog
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@ -1,3 +1,8 @@
2011-06-22 Mike Frysinger <vapier@gentoo.org>
* interp.c (bfin_syscall): Delete old comment. Set dreg 1 to
sc.result2 and dreg 2 to sc.errcode.
2011-06-18 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32shift_0): Clear ASTAT[AV] if val is 0,

4
sim/bfin/interp.c
View File

@ -594,8 +594,8 @@ bfin_syscall (SIM_CPU *cpu)
{
tbuf += sprintf (tbuf, "%lu (error = %i)", sc.result, sc.errcode);
SET_DREG (0, sc.result);
/* Blackfin libgloss only expects R0 to be updated, not R1. */
/*SET_DREG (1, sc.errcode);*/
SET_DREG (1, sc.result2);
SET_DREG (2, sc.errcode);
}
TRACE_SYSCALL (cpu, "%s", _tbuf);