* gas/tic80/{float.d, float.lst, float.s}: New tests for
simple floating point operands. * gas/tic80/tic80.exp: Run the float test.
This commit is contained in:
Fred Fish
parent
d3ecee3912
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cf502a8d9b
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@ -1,4 +1,10 @@
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start-sanitize-tic80
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Wed Feb 26 20:36:46 1997 Fred Fish <fnf@cygnus.com>
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* gas/tic80/{float.d, float.lst, float.s}: New tests for
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simple floating point operands.
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* gas/tic80/tic80.exp: Run the float test.
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Wed Feb 26 15:16:04 1997 Fred Fish <fnf@cygnus.com>
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* gas/tic80/{regops2.d, regops2.lst, regops2.s, regops3.d,
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@ -0,0 +1,72 @@
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#objdump: -d
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#name: TIc80 simple floating point operands
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.*: +file format .*tic80.*
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Disassembly of section .text:
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00000000 <.text>:
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0: 80 12 be 51.*
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4: 16 68 a9 65.*
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8: 00 12 be 51.*
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c: 16 68 a9 e5.*
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10: 00 10 be 51.*
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14: 9a 6d 41 19.*
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18: 80 b0 3e 52.*
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1c: 9a 6d 41 99.*
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20: 00 b0 3e 52.*
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24: 00 00 00 00.*
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28: 80 72 be 51.*
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2c: 00 00 00 40.*
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30: 00 72 be 51.*
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34: 00 00 00 3f.*
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38: 00 70 be 51.*
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3c: 00 00 80 45.*
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40: 80 52 be 51.*
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44: 00 00 80 c5.*
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48: 00 52 be 51.*
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4c: 00 00 00 40.*
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50: 00 50 be 51.*
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54: 00 00 00 40.*
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58: 80 93 3e 40.*
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5c: 00 00 00 40.*
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60: 80 95 3e 40.*
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64: 00 00 00 40.*
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68: 80 91 3e 40.*
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6c: 00 00 00 40.*
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70: 80 97 3e 40.*
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74: 00 00 00 40.*
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78: 00 92 3e 40.*
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7c: 00 00 00 40.*
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80: 00 94 3e 40.*
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84: 00 00 00 40.*
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88: 00 90 3e 40.*
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90: 00 96 3e 40.*
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98: 00 93 3e 40.*
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9c: 00 00 00 40.*
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a0: 00 95 3e 40.*
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a4: 00 00 00 40.*
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a8: 00 91 3e 40.*
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ac: 00 00 00 40.*
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b0: 00 97 3e 40.*
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b4: 00 00 00 40.*
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b8: 80 92 3e 40.*
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bc: 00 00 00 40.*
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c0: 80 94 3e 40.*
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c4: 00 00 00 40.*
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c8: 80 90 3e 40.*
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cc: 00 00 00 40.*
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d0: 80 96 3e 40.*
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d4: 00 00 00 40.*
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d8: 00 f2 3e 50.*
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dc: 00 00 00 40.*
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e0: 00 f0 3e 50.*
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e4: 00 00 00 40.*
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e8: 80 32 be 51.*
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ec: 00 00 00 40.*
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f0: 00 32 be 51.*
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f4: 00 00 00 40.*
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f8: 00 30 be 51.*
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fc: 00 00 00 40.*
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@ -0,0 +1,76 @@
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MVP MP Macro Assembler Version 1.13 Wed Feb 26 22:09:09 1997
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Copyright (c) 1993-1995 Texas Instruments Incorporated
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float.s PAGE 1
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1 00000000 51BE1280 fadd.sdd 1.0E23,r6,r10 ; Immediate form
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00000004 65A96816
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2 00000008 51BE1200 fadd.ssd -1.0E23,r6,r10 ; Immediate form
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0000000C E5A96816
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3 00000010 51BE1000 fadd.sss 1.0E-23,r6,r10 ; Immediate form
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00000014 19416D9A
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4 00000018 523EB080 fcmp.sd -1.0E-23,r8,r10 ; Immediate form
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0000001C 99416D9A
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5 00000020 523EB000 fcmp.ss 0.0,r8,r10 ; Immediate form
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00000024 00000000
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6 00000028 51BE7280 fdiv.sdd 2.0,r6,r10 ; Immediate form
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0000002C 40000000
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7 00000030 51BE7200 fdiv.ssd 0.5,r6,r10 ; Immediate form
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00000034 3F000000
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8 00000038 51BE7000 fdiv.sss 4096.0,r6,r10 ; Immediate form
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0000003C 45800000
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9 00000040 51BE5280 fmpy.sdd -4096.0,r6,r10 ; Immediate form
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00000044 C5800000
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10 00000048 51BE5200 fmpy.ssd 2.0,r6,r10 ; Immediate form
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0000004C 40000000
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11 00000050 51BE5000 fmpy.sss 2.0,r6,r10 ; Immediate form
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00000054 40000000
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12 00000058 403E9380 frndm.sd 2.0,r8 ; Immediate form
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0000005C 40000000
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13 00000060 403E9580 frndm.si 2.0,r8 ; Immediate form
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00000064 40000000
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14 00000068 403E9180 frndm.ss 2.0,r8 ; Immediate form
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0000006C 40000000
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15 00000070 403E9780 frndm.su 2.0,r8 ; Immediate form
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00000074 40000000
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16 00000078 403E9200 frndn.sd 2.0,r8 ; Immediate form
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0000007C 40000000
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17 00000080 403E9400 frndn.si 2.0,r8 ; Immediate form
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00000084 40000000
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18 00000088 403E9000 frndn.ss 2.0,r8 ; Immediate form
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0000008C 40000000
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19 00000090 403E9600 frndn.su 2.0,r8 ; Immediate form
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00000094 40000000
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20 00000098 403E9300 frndp.sd 2.0,r8 ; Immediate form
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0000009C 40000000
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21 000000A0 403E9500 frndp.si 2.0,r8 ; Immediate form
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000000A4 40000000
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22 000000A8 403E9100 frndp.ss 2.0,r8 ; Immediate form
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000000AC 40000000
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23 000000B0 403E9700 frndp.su 2.0,r8 ; Immediate form
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000000B4 40000000
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24 000000B8 403E9280 frndz.sd 2.0,r8 ; Immediate form
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000000BC 40000000
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25 000000C0 403E9480 frndz.si 2.0,r8 ; Immediate form
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000000C4 40000000
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26 000000C8 403E9080 frndz.ss 2.0,r8 ; Immediate form
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000000CC 40000000
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27 000000D0 403E9680 frndz.su 2.0,r8 ; Immediate form
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000000D4 40000000
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28 000000D8 503EF200 fsqrt.sd 2.0,r10 ; Immediate form
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MVP MP Macro Assembler Version 1.13 Wed Feb 26 22:09:09 1997
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Copyright (c) 1993-1995 Texas Instruments Incorporated
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float.s PAGE 2
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000000DC 40000000
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29 000000E0 503EF000 fsqrt.ss 2.0,r10 ; Immediate form
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000000E4 40000000
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30 000000E8 51BE3280 fsub.sdd 2.0,r6,r10 ; Immediate form
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000000EC 40000000
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31 000000F0 51BE3200 fsub.ssd 2.0,r6,r10 ; Immediate form
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000000F4 40000000
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32 000000F8 51BE3000 fsub.sss 2.0,r6,r10 ; Immediate form
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000000FC 40000000
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No Errors, No Warnings
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@ -0,0 +1,32 @@
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fadd.sdd 0f1.0E23,r6,r10 ; Immediate form
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fadd.ssd 0f-1.0E23,r6,r10 ; Immediate form
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fadd.sss 0f1.0E-23,r6,r10 ; Immediate form
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fcmp.sd 0f-1.0E-23,r8,r10 ; Immediate form
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fcmp.ss 0f0.0,r8,r10 ; Immediate form
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fdiv.sdd 0f2.0,r6,r10 ; Immediate form
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fdiv.ssd 0f0.5,r6,r10 ; Immediate form
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fdiv.sss 0f4096.0,r6,r10 ; Immediate form
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fmpy.sdd 0f-4096.0,r6,r10 ; Immediate form
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fmpy.ssd 0f2.0,r6,r10 ; Immediate form
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fmpy.sss 0f2.0,r6,r10 ; Immediate form
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frndm.sd 0f2.0,r8 ; Immediate form
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frndm.si 0f2.0,r8 ; Immediate form
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frndm.ss 0f2.0,r8 ; Immediate form
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frndm.su 0f2.0,r8 ; Immediate form
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frndn.sd 0f2.0,r8 ; Immediate form
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frndn.si 0f2.0,r8 ; Immediate form
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frndn.ss 0f2.0,r8 ; Immediate form
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frndn.su 0f2.0,r8 ; Immediate form
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frndp.sd 0f2.0,r8 ; Immediate form
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frndp.si 0f2.0,r8 ; Immediate form
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frndp.ss 0f2.0,r8 ; Immediate form
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frndp.su 0f2.0,r8 ; Immediate form
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frndz.sd 0f2.0,r8 ; Immediate form
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frndz.si 0f2.0,r8 ; Immediate form
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frndz.ss 0f2.0,r8 ; Immediate form
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frndz.su 0f2.0,r8 ; Immediate form
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fsqrt.sd 0f2.0,r10 ; Immediate form
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fsqrt.ss 0f2.0,r10 ; Immediate form
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fsub.sdd 0f2.0,r6,r10 ; Immediate form
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fsub.ssd 0f2.0,r6,r10 ; Immediate form
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fsub.sss 0f2.0,r6,r10 ; Immediate form
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@ -8,6 +8,7 @@ if [istarget tic80*-*-*] then {
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run_dump_test "regops3"
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run_dump_test "regops4"
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run_dump_test "cregops"
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run_dump_test "float"
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run_dump_test "endmask"
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run_dump_test "bitnum"
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run_dump_test "ccode"
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