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Update check conditions for illegal placed instructions. 

ARC cpus do not accept any jump or instructions with long immediate
into the delay slots.

gas/
2017-06-07  Claudiu Zissulescu  <claziss@synopsys.com>

	* /config/tc-arc.c (is_br_jmp_insn_p): Update macro with known
	instructions to be accounted as jumps.
	(assemble_insn): Check for limms into the delay slots.  Emit an
	error if so.
	* testsuite/gas/arc/asm-errors-3.d: New file.
	* testsuite/gas/arc/asm-errors-3.err: Likewise.
	* testsuite/gas/arc/asm-errors-3.s: Likewise.
This commit is contained in:
claziss 2017-06-07 15:57:56 +02:00
parent 46adbd1740
commit cf9bdae906
5 changed files with 50 additions and 2 deletions
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10
gas/ChangeLog
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@ -1,3 +1,13 @@
2017-06-26 Claudiu Zissulescu <claziss@synopsys.com>
* /config/tc-arc.c (is_br_jmp_insn_p): Update macro with known
instructions to be accounted as jumps.
(assemble_insn): Check for limms into the delay slots. Emit an
error if so.
* testsuite/gas/arc/asm-errors-3.d: New file.
* testsuite/gas/arc/asm-errors-3.err: Likewise.
* testsuite/gas/arc/asm-errors-3.s: Likewise.
2017-06-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
* NEWS: Mention support of ARM Cortex-R52 processor.

19
gas/config/tc-arc.c
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@ -107,8 +107,18 @@ enum arc_rlx_types
#define is_spfp_p(op) (((sc) == SPX))
#define is_dpfp_p(op) (((sc) == DPX))
#define is_fpuda_p(op) (((sc) == DPA))
#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
|| (op)->insn_class == JUMP))
#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
|| (op)->insn_class == JUMP \
|| (op)->insn_class == BRCC \
|| (op)->insn_class == BBIT0 \
|| (op)->insn_class == BBIT1 \
|| (op)->insn_class == BI \
|| (op)->insn_class == EI \
|| (op)->insn_class == ENTER \
|| (op)->insn_class == JLI \
|| (op)->insn_class == LOOP \
|| (op)->insn_class == LEAVE \
))
#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
#define is_nps400_p(op) (((sc) == NPS400))
@ -4107,6 +4117,11 @@ assemble_insn (const struct arc_opcode *opcode,
as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
arc_last_insns[1].opcode->name,
arc_last_insns[0].opcode->name);
if (arc_last_insns[1].has_delay_slot
&& arc_last_insns[0].has_limm)
as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
arc_last_insns[1].opcode->name,
arc_last_insns[0].opcode->name);
}
void

2
gas/testsuite/gas/arc/asm-errors-3.d Normal file
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@ -0,0 +1,2 @@
#as:
#error-output: asm-errors-3.err

7
gas/testsuite/gas/arc/asm-errors-3.err Normal file
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@ -0,0 +1,7 @@
[^:]*: Assembler messages:
[^:]*:4: Error: Insn bl has an instruction st with limm in its delay slot.
[^:]*:6: Error: Insn bl has an instruction st with limm in its delay slot.
[^:]*:8: Error: Insn bl has a jump/branch instruction breq in its delay slot.
[^:]*:10: Error: Insn bl has a jump/branch instruction bl in its delay slot.
[^:]*:12: Error: Insn bl has a jump/branch instruction bbit0 in its delay slot.
[^:]*:14: Error: Insn bl has a jump/branch instruction ei_s in its delay slot.

14
gas/testsuite/gas/arc/asm-errors-3.s Normal file
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@ -0,0 +1,14 @@
.cpu ARCHS
.L1:
bl.d @foo
st 1,[@a]
bl.d @foo
st @a,[r1]
bl.d @foo
breq r0,r1,@.L1
bl.d @foo
bl @foo
bl.d @foo
bbit0 r0,r1,@.L1
bl.d @foo
ei_s 1