* doc/internals.texi (CPU backend): Fix typo in md_section_align
description. start-sanitize-tic80 * config/tc-tic80.h (NEED_FX_R_TYPE): Define. * config/tc-tic80.c (find_opcode): Add code to support O_symbol operands. (build_insn): Grab a frag early so we can use the address in fixups. Take one's complement of BITNUM values before insertion in opcode. Add code to support O_symbol operands. (md_apply_fix): Replace unimplemented warning with implementation. (md_pcrel_from): Ditto. (tc_coff_fix2rtype): Ditto. end-sanitize-tic80
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@ -1,3 +1,18 @@
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Sat Feb 22 20:53:01 1997 Fred Fish <fnf@cygnus.com>
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* doc/internals.texi (CPU backend): Fix typo in md_section_align
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description.
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start-sanitize-tic80
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* config/tc-tic80.h (NEED_FX_R_TYPE): Define.
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* config/tc-tic80.c (find_opcode): Add code to support O_symbol
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operands.
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(build_insn): Grab a frag early so we can use the address in
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fixups. Take one's complement of BITNUM values before insertion
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in opcode. Add code to support O_symbol operands.
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(md_apply_fix): Replace unimplemented warning with implementation.
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(md_pcrel_from): Ditto.
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(tc_coff_fix2rtype): Ditto.
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end-sanitize-tic80
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Fri Feb 21 14:34:31 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
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start-sanitize-d30v
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* config/tc-d30v.c (parallel_ok): New function.
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@ -381,9 +381,28 @@ find_opcode (opcode, myops)
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match = 0;
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}
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break;
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case O_symbol:
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if ((bits < 32) && (flags & TIC80_OPERAND_PCREL))
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{
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/* For now we only allow PC relative relocations in the
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short immediate fields, like the TI assembler.
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FIXME: Should be able to choose "best-fit". */
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}
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else if ((bits == 32) && (flags & TIC80_OPERAND_BASEREL))
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{
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/* For now we only allow base relative relocations in
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the long immediate fields, like the TI assembler.
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FIXME: Should be able to choose "best-fit". */
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}
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else
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{
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/* Symbols that don't match one of the above cases are
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rejected as an operand. */
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match = 0;
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}
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break;
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case O_illegal:
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case O_absent:
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case O_symbol:
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case O_symbol_rva:
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case O_big:
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case O_uminus:
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@ -524,6 +543,11 @@ build_insn (opcode, opers)
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/* Start with the raw opcode bits from the opcode table. */
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insn[0] = opcode -> opcode;
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/* We are going to insert at least one 32 bit opcode so get the
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frag now. */
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f = frag_more (4);
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/* For each operand expression, insert the appropriate bits into the
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instruction . */
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for (expi = 0, opi = -1; opers[expi].X_op != O_illegal; expi++)
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@ -576,6 +600,11 @@ build_insn (opcode, opers)
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/* Endmask values of 0 and 32 give identical results */
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num = 0;
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}
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else if ((flags & TIC80_OPERAND_BITNUM))
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{
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/* BITNUM values are stored in one's complement form */
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num = (~num & 0x1F);
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}
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/* Mask off upper bits, just it case it is signed and is negative */
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if (bits < 32)
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{
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@ -588,9 +617,33 @@ build_insn (opcode, opers)
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insn[1] = num;
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}
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break;
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case O_symbol:
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if (flags & TIC80_OPERAND_PCREL)
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{
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fix_new_exp (frag_now,
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f - (frag_now -> fr_literal),
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4, /* FIXME! how is this used? */
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&opers[expi],
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1,
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R_MPPCR);
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}
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else if (flags & TIC80_OPERAND_BASEREL)
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{
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extended++;
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fix_new_exp (frag_now,
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(f + 4) - (frag_now -> fr_literal),
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4,
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&opers[expi],
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0, /* FIXME! should allow pcrel */
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R_RELLONGX); /* FIXME! should be the right reloc type */
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}
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else
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{
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internal_error ("symbol reloc that is not PC or BASEREG relative");
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}
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break;
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case O_illegal:
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case O_absent:
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case O_symbol:
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case O_symbol_rva:
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case O_big:
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case O_uminus:
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@ -624,7 +677,6 @@ build_insn (opcode, opers)
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/* Write out the instruction, either 4 or 8 bytes. */
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f = frag_more (4);
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md_number_to_chars (f, insn[0], 4);
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if (extended)
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{
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@ -814,22 +866,38 @@ md_apply_fix (fixP, val)
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fixS *fixP;
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long val;
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{
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internal_error ("md_apply_fix() not implemented yet");
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abort ();
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char *dest = fixP -> fx_frag -> fr_literal + fixP -> fx_where;
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switch (fixP -> fx_r_type)
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{
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case R_RELLONGX:
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md_number_to_chars (dest, (valueT) val, 4);
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break;
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case R_MPPCR:
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/* FIXME! - should check for overflow of the 15 bit field */
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*dest++ = val >> 2;
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*dest = (*dest & 0x80) | val >> 10;
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break;
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default:
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internal_error_a ("unhandled relocation type in fixup", fixP -> fx_r_type);
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break;
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}
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}
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/* Functions concerning relocs. */
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/* The location from which a PC relative jump should be calculated,
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given a PC relative reloc. */
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given a PC relative reloc.
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For the TIc80, this is the address of the 32 bit opcode containing
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the PC relative field. */
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long
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md_pcrel_from (fixP)
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fixS *fixP;
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{
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internal_error ("md_pcrel_from() not implemented yet");
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abort ();
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return (fixP -> fx_frag -> fr_address + fixP -> fx_where) ;
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}
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/*
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tc_coff_fix2rtype (fixP)
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fixS *fixP;
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{
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internal_error ("tc_coff_fix2rtype() not implemented yet");
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abort ();
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return (fixP -> fx_r_type);
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}
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#endif /* OBJ_COFF */
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@ -26,6 +26,10 @@
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#define TARGET_FORMAT "coff-tic80"
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#define BFD_ARCH TARGET_ARCH
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/* We need the extra field in the fixup struct to put the relocation in. */
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#define NEED_FX_R_TYPE
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/* Define md_number_to_chars as the appropriate standard big endian or
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little endian function. Should we someday support endianness as a
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runtime decision, this will need to change. */
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