x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit mode
Update x86 disassembler to ignore the EVEX.W bit in EVEX vcvt[u]si2s[sd] instructions in 32-bit mode. gas/ PR binutils/23655 * testsuite/gas/i386/evex.d: New file. * testsuite/gas/i386/evex.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex. opcodes/ PR binutils/23655 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ. * i386-dis.c (Edqa): New. (dqa_mode): Likewise. (intel_operand_size): Handle dqa_mode as m_mode. (OP_E_register): Handle dqa_mode as dq_mode. (OP_E_memory): Set shift for dqa_mode based on address_mode.
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5074ad8a66
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@ -1,3 +1,10 @@
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2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/23655
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* testsuite/gas/i386/evex.d: New file.
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* testsuite/gas/i386/evex.s: Likewise.
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* testsuite/gas/i386/i386.exp: Run evex.
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2018-09-10 Lifang Xia <lifang_xia@c-sky.com>
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* config/tc-csky.c (md_apply_fix): Transmit BFD_RELOC_32_PCREL to
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@ -0,0 +1,16 @@
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#objdump: -dw -Msuffix
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#name: i386 EVX insns
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
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+[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sdl %eax,\{rd-sae\},%xmm5,%xmm6
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+[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ssl %eax,%xmm5,%xmm6
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+[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
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+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
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+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,\{rd-sae\},%xmm5,%xmm6
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#pass
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@ -0,0 +1,11 @@
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# Check EVEX instructions
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.allow_index_reg
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.text
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_start:
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.byte 0x62, 0xf1, 0xd6, 0x38, 0x2a, 0xf0
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.byte 0x62, 0xf1, 0xd7, 0x38, 0x2a, 0xf0
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.byte 0x62, 0xf1, 0xd6, 0x08, 0x7b, 0xf0
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.byte 0x62, 0xf1, 0xd7, 0x08, 0x7b, 0xf0
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.byte 0x62, 0xf1, 0xd6, 0x38, 0x7b, 0xf0
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.byte 0x62, 0xf1, 0xd7, 0x38, 0x7b, 0xf0
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@ -226,6 +226,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "avx512er-intel"
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run_dump_test "avx512pf"
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run_dump_test "avx512pf-intel"
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run_dump_test "evex"
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run_dump_test "evex-lig256"
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run_dump_test "evex-lig512"
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run_dump_test "evex-lig256-intel"
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@ -1,3 +1,14 @@
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2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/23655
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* i386-dis-evex.h (evex_table): Replace Eq with Edqa for
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vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
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* i386-dis.c (Edqa): New.
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(dqa_mode): Likewise.
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(intel_operand_size): Handle dqa_mode as m_mode.
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(OP_E_register): Handle dqa_mode as dq_mode.
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(OP_E_memory): Set shift for dqa_mode based on address_mode.
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2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (OP_E_memory): Reformat.
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@ -3046,12 +3046,12 @@ static const struct dis386 evex_table[][256] = {
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/* EVEX_W_0F2A_P_1 */
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{
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{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 },
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{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 },
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{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 },
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},
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/* EVEX_W_0F2A_P_3 */
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{
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{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 },
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{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 },
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{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 },
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},
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/* EVEX_W_0F2B_P_0 */
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{
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@ -3383,7 +3383,7 @@ static const struct dis386 evex_table[][256] = {
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/* EVEX_W_0F7B_P_1 */
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{
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{ "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 },
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{ "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 },
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{ "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 },
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},
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/* EVEX_W_0F7B_P_2 */
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{
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@ -3393,7 +3393,7 @@ static const struct dis386 evex_table[][256] = {
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/* EVEX_W_0F7B_P_3 */
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{
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{ "vcvtusi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 },
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{ "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 },
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{ "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 },
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},
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/* EVEX_W_0F7E_P_1 */
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{
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@ -260,6 +260,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define Edb { OP_E, db_mode }
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#define Edw { OP_E, dw_mode }
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#define Edqd { OP_E, dqd_mode }
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#define Edqa { OP_E, dqa_mode }
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#define Eq { OP_E, q_mode }
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#define indirEv { OP_indirE, indir_v_mode }
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#define indirEp { OP_indirE, f_mode }
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@ -591,6 +592,8 @@ enum
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dw_mode,
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/* registers like dq_mode, memory like d_mode. */
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dqd_mode,
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/* operand size depends on the W bit as well as address mode. */
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dqa_mode,
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/* normal vex mode */
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vex_mode,
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/* 128bit vex mode */
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@ -14805,6 +14808,7 @@ intel_operand_size (int bytemode, int sizeflag)
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case q_swap_mode:
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oappend ("QWORD PTR ");
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break;
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case dqa_mode:
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case m_mode:
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if (address_mode == mode_64bit)
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oappend ("QWORD PTR ");
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@ -15163,6 +15167,7 @@ OP_E_register (int bytemode, int sizeflag)
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case dqb_mode:
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case dqd_mode:
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case dqw_mode:
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case dqa_mode:
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USED_REX (REX_W);
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if (rex & REX_W)
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names = names64;
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@ -15305,6 +15310,9 @@ OP_E_memory (int bytemode, int sizeflag)
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case xmm_mb_mode:
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shift = 0;
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break;
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case dqa_mode:
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shift = address_mode == mode_64bit ? 3 : 2;
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break;
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default:
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abort ();
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}
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