* mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1
(sqrt.s): Likewise.
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@ -1,3 +1,24 @@
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start-sanitize-r5900
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Mon Jun 1 10:27:26 1998 Jeffrey A Law (law@cygnus.com)
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* mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1
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(sqrt.s): Likewise.
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end-sanitize-r5900
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start-sanitize-vr5400
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Thu May 28 08:46:09 1998 Catherine Moore <clm@cygnus.com>
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* mips-opc.c (macc, maccu, macchi, macchiu, msac, msacu, msachi, msachiu):
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Change pinfo to use WR_HILO.
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end-sanitize-vr5400
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start-sanitize-d30v
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Wed May 27 15:29:13 1998 Nick Clifton <nickc@cygnus.com>
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* d30v-opc.c: Add new operand: Ra3. Change SHORT_B3, SHORT_B3b,
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LONG_2, LONG_2b formats to use this new operand.
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end-sanitize-d30v
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Tue May 26 20:47:48 1998 Stan Cox <scox@cygnus.com>
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* sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le.
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@ -7,6 +28,7 @@ Tue May 26 20:45:33 1998 Mark Alexander <marka@cygnus.com>
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* sparc-dis.c (print_insn_sparc): big endian instruction / little
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endian data support.
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start-sanitize-d30v
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Tue May 26 16:14:39 1998 Nick Clifton <nickc@cygnus.com>
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* d30v-opc.c (d30v_format_table): Change definition of SHORT_B3
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@ -17,6 +39,7 @@ Tue May 26 16:14:39 1998 Nick Clifton <nickc@cygnus.com>
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Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension
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to existing 1.1.1 parallelisation prohibition procedure.
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end-sanitize-d30v
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Fri May 22 16:00:00 1998 Doug Evans <devans@canuck.cygnus.com>
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* cgen-asm.in (insert_normal): Handle empty fields and 64 bit hosts.
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@ -80,10 +103,12 @@ Tue May 12 13:39:51 1998 Nick Clifton <nickc@cygnus.com>
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insns.
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end-sanitize-m32rx
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start-sanitize-d30v
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Tue May 12 11:46:31 1998 Richard Henderson <rth@cygnus.com>
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* d30v-opc.c (pre_defined_register): Remove alias for r0.
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end-sanitize-d30v
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start-sanitize-r5900
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Mon May 11 13:12:15 1998 Frank Ch. Eigler <fche@cygnus.com>
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@ -548,25 +548,25 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"macc", "d,s,t", 0x000000A8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
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{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5},
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/* end-sanitize-vr5400 */
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/* start-sanitize-vr4320 */
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{"maccu", "d,s,t", 0x000000E8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
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{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5},
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/* end-sanitize-vr5400 */
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/* start-sanitize-vr4320 */
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{"macchi", "d,s,t", 0x000002A8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
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{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5},
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/* end-sanitize-vr5400 */
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/* start-sanitize-vr4320 */
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{"macchiu", "d,s,t", 0x000002E8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
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{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5},
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/* end-sanitize-vr5400 */
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{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
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{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
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@ -677,10 +677,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 },
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{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 },
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/* start-sanitize-vr5400 */
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{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d, N5 },
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{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d, N5 },
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{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d, N5 },
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{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d, N5 },
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{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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/* end-sanitize-vr5400 */
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/* move is at the top of the table. */
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{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
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{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1},
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{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1},
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/* start-sanitize-r5900 */
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{"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5},
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{"multu1", "d,s,t", 0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5},
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/* end-sanitize-r5900 */
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{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
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@ -932,7 +933,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 },
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{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 },
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/* start-sanitize-r5900 */
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{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, T5 },
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{"rsqrt.s", "D,S,T", 0x46000016, 0xffe0003f, WR_D|RD_S|FP_S, T5 },
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/* end-sanitize-r5900 */
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{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
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{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 },
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@ -995,6 +996,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"sq", "t,o(b)", 0x7c000000, 0xfc000000, SM|RD_t|RD_b, T5 },
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/* end-sanitize-r5900 */
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{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 },
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/* start-sanitize-r5900 */
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{"sqrt.s", "D,T", 0x46000004, 0xffe0f83f, WR_D|RD_S|FP_S, T5 },
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/* end-sanitize-r5900 */
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{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 },
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{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
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{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */
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