gas/
* config/tc-arm.c (parse_psr): Add LHS argument. Improve support for *APSR bitmasks. (operand_parse_code): Replace OP_PSR with OP_wPSR and OP_rPSR. Remove OP_RVC_PSR. (parse_operands): Likewise. (do_mrs): Tweak error message for constraint. (do_t_mrs): Update constraints for changes to APSR support. (do_t_msr): Likewise. Don't set PSR_f flag here. (psrs): Remove "g", "nzcvq", "nzcvqg". (insns): Tweak entries for msr and mrs instructions. opcodes/ * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX. (print_insn_thumb32): Add APSR bitmask support. gas/testsuite/ * gas/arm/mrs-msr-thumb-v7-m.s: New. * gas/arm/mrs-msr-thumb-v7-m.d: New. * gas/arm/mrs-msr-thumb-v7-m-bad.d: New. * gas/arm/mrs-msr-thumb-v7-m-bad.l: New. * gas/arm/mrs-msr-thumb-v7-m-bad.s: New. * gas/arm/mrs-msr-thumb-v7e-m.d: New. * gas/arm/mrs-msr-thumb-v7e-m.s: New. * gas/arm/mrs-msr-arm-v7-a-bad.d: New. * gas/arm/mrs-msr-arm-v7-a-bad.l: New. * gas/arm/mrs-msr-arm-v7-a-bad.s: New. * gas/arm/mrs-msr-arm-v7-a.d: New. * gas/arm/mrs-msr-arm-v7-a.s: New. * gas/arm/mrs-msr-arm-v6.d: New. * gas/arm/mrs-msr-arm-v6.s: New. * gas/arm/mrs-msr-thumb-v6t2.d: New. * gas/arm/mrs-msr-thumb-v6t2.s: New. * gas/arm/arch7.d: Fix typo in disassembly for BASEPRI_MAX, bitmasks for IAPSR etc. * gas/arm/arch7.s: Specify bitmask for APSR writes. * gas/arm/archv6m.s: Likewise. * msr-imm-bad.l: Tweak expected disassembly in error message. * msr-reg-bad.l: Likewise. * msr-imm.d: Tweak expected disassembly. * msr-reg.d: Likewise. * msr-reg-thumb.d: Likewise. * msr-imm.s: Specify bitmask on APSR writes. * msr-reg.s: Add comment about deprecated usage.
This commit is contained in:
parent
4a57f2cf9c
commit
d2cd120565
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@ -1,3 +1,16 @@
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2011-04-11 Julian Brown <julian@codesourcery.com>
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* config/tc-arm.c (parse_psr): Add LHS argument. Improve support
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for *APSR bitmasks.
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(operand_parse_code): Replace OP_PSR with OP_wPSR and OP_rPSR.
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Remove OP_RVC_PSR.
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(parse_operands): Likewise.
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(do_mrs): Tweak error message for constraint.
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(do_t_mrs): Update constraints for changes to APSR support.
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(do_t_msr): Likewise. Don't set PSR_f flag here.
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(psrs): Remove "g", "nzcvq", "nzcvqg".
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(insns): Tweak entries for msr and mrs instructions.
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2011-04-11 Kai Tietz <ktietz@redhat.com>
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2011-04-11 Kai Tietz <ktietz@redhat.com>
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* config/tc-i386.c (x86_cons): Initialize adjust with zero.
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* config/tc-i386.c (x86_cons): Initialize adjust with zero.
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@ -5347,39 +5347,79 @@ parse_half (char **str)
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/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
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/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
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or a bitmask suitable to be or-ed into the ARM msr instruction. */
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or a bitmask suitable to be or-ed into the ARM msr instruction. */
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static int
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static int
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parse_psr (char **str)
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parse_psr (char **str, bfd_boolean lhs)
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{
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{
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char *p;
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char *p;
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unsigned long psr_field;
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unsigned long psr_field;
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const struct asm_psr *psr;
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const struct asm_psr *psr;
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char *start;
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char *start;
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bfd_boolean is_apsr = FALSE;
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bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m);
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/* CPSR's and SPSR's can now be lowercase. This is just a convenience
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/* CPSR's and SPSR's can now be lowercase. This is just a convenience
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feature for ease of use and backwards compatibility. */
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feature for ease of use and backwards compatibility. */
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p = *str;
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p = *str;
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if (strncasecmp (p, "SPSR", 4) == 0)
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if (strncasecmp (p, "SPSR", 4) == 0)
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{
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if (m_profile)
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goto unsupported_psr;
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psr_field = SPSR_BIT;
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psr_field = SPSR_BIT;
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else if (strncasecmp (p, "CPSR", 4) == 0
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}
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|| (strncasecmp (p, "APSR", 4) == 0
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else if (strncasecmp (p, "CPSR", 4) == 0)
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&& !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)))
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{
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if (m_profile)
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goto unsupported_psr;
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psr_field = 0;
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psr_field = 0;
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else
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}
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else if (strncasecmp (p, "APSR", 4) == 0)
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{
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/* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
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and ARMv7-R architecture CPUs. */
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is_apsr = TRUE;
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psr_field = 0;
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}
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else if (m_profile)
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{
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{
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start = p;
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start = p;
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do
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do
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p++;
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p++;
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while (ISALNUM (*p) || *p == '_');
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while (ISALNUM (*p) || *p == '_');
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if (strncasecmp (start, "iapsr", 5) == 0
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|| strncasecmp (start, "eapsr", 5) == 0
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|| strncasecmp (start, "xpsr", 4) == 0
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|| strncasecmp (start, "psr", 3) == 0)
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p = start + strcspn (start, "rR") + 1;
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psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
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psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
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p - start);
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p - start);
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if (!psr)
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if (!psr)
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return FAIL;
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return FAIL;
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*str = p;
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/* If APSR is being written, a bitfield may be specified. Note that
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return psr->field;
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APSR itself is handled above. */
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if (psr->field <= 3)
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{
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psr_field = psr->field;
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is_apsr = TRUE;
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goto check_suffix;
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}
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}
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*str = p;
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/* M-profile MSR instructions have the mask field set to "10", except
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*PSR variants which modify APSR, which may use a different mask (and
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have been handled already). Do that by setting the PSR_f field
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here. */
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return psr->field | (lhs ? PSR_f : 0);
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}
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else
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goto unsupported_psr;
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p += 4;
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p += 4;
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check_suffix:
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if (*p == '_')
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if (*p == '_')
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{
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{
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/* A suffix follows. */
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/* A suffix follows. */
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@ -5390,6 +5430,72 @@ parse_psr (char **str)
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p++;
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p++;
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while (ISALNUM (*p) || *p == '_');
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while (ISALNUM (*p) || *p == '_');
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if (is_apsr)
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{
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/* APSR uses a notation for bits, rather than fields. */
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unsigned int nzcvq_bits = 0;
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unsigned int g_bit = 0;
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char *bit;
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for (bit = start; bit != p; bit++)
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{
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switch (TOLOWER (*bit))
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{
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case 'n':
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nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
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break;
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case 'z':
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nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
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break;
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case 'c':
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nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
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break;
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case 'v':
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nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
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break;
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case 'q':
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nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
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break;
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case 'g':
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g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
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break;
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default:
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inst.error = _("unexpected bit specified after APSR");
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return FAIL;
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}
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}
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if (nzcvq_bits == 0x1f)
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psr_field |= PSR_f;
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if (g_bit == 0x1)
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{
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if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
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{
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inst.error = _("selected processor does not "
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"support DSP extension");
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return FAIL;
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}
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psr_field |= PSR_s;
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}
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if ((nzcvq_bits & 0x20) != 0
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|| (nzcvq_bits != 0x1f && nzcvq_bits != 0)
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|| (g_bit & 0x2) != 0)
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{
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inst.error = _("bad bitmask specified after APSR");
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return FAIL;
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}
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}
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else
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{
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psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
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psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
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p - start);
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p - start);
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if (!psr)
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if (!psr)
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@ -5397,16 +5503,33 @@ parse_psr (char **str)
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psr_field |= psr->field;
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psr_field |= psr->field;
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}
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}
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}
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else
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else
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{
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{
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if (ISALNUM (*p))
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if (ISALNUM (*p))
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goto error; /* Garbage after "[CS]PSR". */
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goto error; /* Garbage after "[CS]PSR". */
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/* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
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is deprecated, but allow it anyway. */
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if (is_apsr && lhs)
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{
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psr_field |= PSR_f;
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as_tsktsk (_("writing to APSR without specifying a bitmask is "
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"deprecated"));
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}
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else if (!m_profile)
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/* These bits are never right for M-profile devices: don't set them
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(only code paths which read/write APSR reach here). */
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psr_field |= (PSR_c | PSR_f);
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psr_field |= (PSR_c | PSR_f);
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}
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}
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*str = p;
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*str = p;
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return psr_field;
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return psr_field;
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unsupported_psr:
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inst.error = _("selected processor does not support requested special "
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"purpose register");
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return FAIL;
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error:
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error:
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inst.error = _("flag for {c}psr instruction expected");
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inst.error = _("flag for {c}psr instruction expected");
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return FAIL;
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return FAIL;
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@ -5932,11 +6055,11 @@ enum operand_parse_code
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OP_CPSF, /* CPS flags */
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OP_CPSF, /* CPS flags */
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OP_ENDI, /* Endianness specifier */
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OP_ENDI, /* Endianness specifier */
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OP_PSR, /* CPSR/SPSR mask for msr */
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OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
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OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
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OP_COND, /* conditional code */
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OP_COND, /* conditional code */
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OP_TB, /* Table branch. */
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OP_TB, /* Table branch. */
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OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */
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OP_APSR_RR, /* ARM register or "APSR_nzcv". */
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OP_APSR_RR, /* ARM register or "APSR_nzcv". */
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OP_RRnpc_I0, /* ARM register or literal 0 */
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OP_RRnpc_I0, /* ARM register or literal 0 */
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@ -6402,7 +6525,6 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_CPSF: val = parse_cps_flags (&str); break;
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case OP_CPSF: val = parse_cps_flags (&str); break;
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case OP_ENDI: val = parse_endian_specifier (&str); break;
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case OP_ENDI: val = parse_endian_specifier (&str); break;
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case OP_oROR: val = parse_ror (&str); break;
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case OP_oROR: val = parse_ror (&str); break;
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case OP_PSR: val = parse_psr (&str); break;
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case OP_COND: val = parse_cond (&str); break;
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case OP_COND: val = parse_cond (&str); break;
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case OP_oBARRIER_I15:
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case OP_oBARRIER_I15:
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po_barrier_or_imm (str); break;
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po_barrier_or_imm (str); break;
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@ -6411,11 +6533,8 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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goto failure;
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goto failure;
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break;
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break;
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case OP_RVC_PSR:
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case OP_wPSR:
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po_reg_or_goto (REG_TYPE_VFC, try_banked_reg);
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case OP_rPSR:
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inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
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break;
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try_banked_reg:
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po_reg_or_goto (REG_TYPE_RNB, try_psr);
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po_reg_or_goto (REG_TYPE_RNB, try_psr);
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
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{
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{
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@ -6425,7 +6544,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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}
|
}
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break;
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break;
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try_psr:
|
try_psr:
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val = parse_psr (&str);
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val = parse_psr (&str, op_parse_code == OP_wPSR);
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break;
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break;
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|
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case OP_APSR_RR:
|
case OP_APSR_RR:
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|
@ -6583,8 +6702,8 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_CPSF:
|
case OP_CPSF:
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case OP_ENDI:
|
case OP_ENDI:
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case OP_oROR:
|
case OP_oROR:
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case OP_PSR:
|
case OP_wPSR:
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case OP_RVC_PSR:
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case OP_rPSR:
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case OP_COND:
|
case OP_COND:
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case OP_oBARRIER_I15:
|
case OP_oBARRIER_I15:
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case OP_REGLST:
|
case OP_REGLST:
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|
@ -7912,7 +8031,7 @@ do_mrs (void)
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/* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
|
/* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
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constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
|
constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
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!= (PSR_c|PSR_f),
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!= (PSR_c|PSR_f),
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_("'CPSR' or 'SPSR' expected"));
|
_("'APSR', 'CPSR' or 'SPSR' expected"));
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br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
|
br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
|
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}
|
}
|
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|
|
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|
@ -10828,21 +10947,14 @@ do_t_mrs (void)
|
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{
|
{
|
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int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
|
int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
|
||||||
|
|
||||||
if (flags == 0)
|
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
|
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{
|
constraint (flags != 0, _("selected processor does not support "
|
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
|
|
||||||
_("selected processor does not support "
|
|
||||||
"requested special purpose register"));
|
"requested special purpose register"));
|
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}
|
|
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else
|
else
|
||||||
{
|
/* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
|
||||||
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
|
devices). */
|
||||||
_("selected processor does not support "
|
|
||||||
"requested special purpose register"));
|
|
||||||
/* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
|
|
||||||
constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
|
constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
|
||||||
_("'CPSR' or 'SPSR' expected"));
|
_("'APSR', 'CPSR' or 'SPSR' expected"));
|
||||||
}
|
|
||||||
|
|
||||||
inst.instruction |= (flags & SPSR_BIT) >> 2;
|
inst.instruction |= (flags & SPSR_BIT) >> 2;
|
||||||
inst.instruction |= inst.operands[1].imm & 0xff;
|
inst.instruction |= inst.operands[1].imm & 0xff;
|
||||||
|
@ -10867,19 +10979,20 @@ do_t_msr (void)
|
||||||
else
|
else
|
||||||
flags = inst.operands[0].imm;
|
flags = inst.operands[0].imm;
|
||||||
|
|
||||||
if (flags & ~0xff)
|
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
|
||||||
{
|
{
|
||||||
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
|
int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
|
||||||
_("selected processor does not support "
|
|
||||||
"requested special purpose register"));
|
constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
|
||||||
|
&& (bits & ~(PSR_s | PSR_f)) != 0)
|
||||||
|
|| (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
|
||||||
|
&& bits != PSR_f),
|
||||||
|
_("selected processor does not support requested special "
|
||||||
|
"purpose register"));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
constraint ((flags & 0xff) != 0, _("selected processor does not support "
|
||||||
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
|
|
||||||
_("selected processor does not support "
|
|
||||||
"requested special purpose register"));
|
"requested special purpose register"));
|
||||||
flags |= PSR_f;
|
|
||||||
}
|
|
||||||
|
|
||||||
Rn = inst.operands[1].reg;
|
Rn = inst.operands[1].reg;
|
||||||
reject_bad_reg (Rn);
|
reject_bad_reg (Rn);
|
||||||
|
@ -16440,7 +16553,6 @@ static const struct asm_psr psrs[] =
|
||||||
{"c", PSR_c},
|
{"c", PSR_c},
|
||||||
{"x", PSR_x},
|
{"x", PSR_x},
|
||||||
{"s", PSR_s},
|
{"s", PSR_s},
|
||||||
{"g", PSR_s},
|
|
||||||
|
|
||||||
/* Combinations of flags. */
|
/* Combinations of flags. */
|
||||||
{"fs", PSR_f | PSR_s},
|
{"fs", PSR_f | PSR_s},
|
||||||
|
@ -16503,10 +16615,6 @@ static const struct asm_psr psrs[] =
|
||||||
{"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
|
{"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
|
||||||
{"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
|
{"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
|
||||||
{"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
|
{"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
|
||||||
|
|
||||||
/* APSR flags */
|
|
||||||
{"nzcvq", PSR_f},
|
|
||||||
{"nzcvqg", PSR_s | PSR_f}
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Table of V7M psr names. */
|
/* Table of V7M psr names. */
|
||||||
|
@ -16955,8 +17063,8 @@ static const struct asm_opcode insns[] =
|
||||||
#undef THUMB_VARIANT
|
#undef THUMB_VARIANT
|
||||||
#define THUMB_VARIANT & arm_ext_msr
|
#define THUMB_VARIANT & arm_ext_msr
|
||||||
|
|
||||||
TCE("mrs", 1000000, f3e08000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
|
TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
|
||||||
TCE("msr", 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
|
TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
|
||||||
|
|
||||||
#undef ARM_VARIANT
|
#undef ARM_VARIANT
|
||||||
#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
|
#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
|
||||||
|
|
|
@ -1,3 +1,33 @@
|
||||||
|
2011-04-11 Julian Brown <julian@codesourcery.com>
|
||||||
|
|
||||||
|
* gas/arm/mrs-msr-thumb-v7-m.s: New.
|
||||||
|
* gas/arm/mrs-msr-thumb-v7-m.d: New.
|
||||||
|
* gas/arm/mrs-msr-thumb-v7-m-bad.d: New.
|
||||||
|
* gas/arm/mrs-msr-thumb-v7-m-bad.l: New.
|
||||||
|
* gas/arm/mrs-msr-thumb-v7-m-bad.s: New.
|
||||||
|
* gas/arm/mrs-msr-thumb-v7e-m.d: New.
|
||||||
|
* gas/arm/mrs-msr-thumb-v7e-m.s: New.
|
||||||
|
* gas/arm/mrs-msr-arm-v7-a-bad.d: New.
|
||||||
|
* gas/arm/mrs-msr-arm-v7-a-bad.l: New.
|
||||||
|
* gas/arm/mrs-msr-arm-v7-a-bad.s: New.
|
||||||
|
* gas/arm/mrs-msr-arm-v7-a.d: New.
|
||||||
|
* gas/arm/mrs-msr-arm-v7-a.s: New.
|
||||||
|
* gas/arm/mrs-msr-arm-v6.d: New.
|
||||||
|
* gas/arm/mrs-msr-arm-v6.s: New.
|
||||||
|
* gas/arm/mrs-msr-thumb-v6t2.d: New.
|
||||||
|
* gas/arm/mrs-msr-thumb-v6t2.s: New.
|
||||||
|
* gas/arm/arch7.d: Fix typo in disassembly for BASEPRI_MAX,
|
||||||
|
bitmasks for IAPSR etc.
|
||||||
|
* gas/arm/arch7.s: Specify bitmask for APSR writes.
|
||||||
|
* gas/arm/archv6m.s: Likewise.
|
||||||
|
* msr-imm-bad.l: Tweak expected disassembly in error message.
|
||||||
|
* msr-reg-bad.l: Likewise.
|
||||||
|
* msr-imm.d: Tweak expected disassembly.
|
||||||
|
* msr-reg.d: Likewise.
|
||||||
|
* msr-reg-thumb.d: Likewise.
|
||||||
|
* msr-imm.s: Specify bitmask on APSR writes.
|
||||||
|
* msr-reg.s: Add comment about deprecated usage.
|
||||||
|
|
||||||
2011-04-11 Dan McDonald <dan@wellkeeper.com>
|
2011-04-11 Dan McDonald <dan@wellkeeper.com>
|
||||||
|
|
||||||
PR gas/12296
|
PR gas/12296
|
||||||
|
|
|
@ -57,13 +57,13 @@ Disassembly of section .text:
|
||||||
0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
|
0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
|
||||||
0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
|
0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
|
||||||
0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
|
0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
|
||||||
0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MASK
|
0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MAX
|
||||||
0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
|
0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
|
||||||
0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
|
0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
|
||||||
0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR), r0
|
0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR_nzcvq), r0
|
||||||
0+0dc <[^>]*> f380 8801 msr IAPSR, r0
|
0+0dc <[^>]*> f380 8801 msr IAPSR_nzcvq, r0
|
||||||
0+0e0 <[^>]*> f380 8802 msr EAPSR, r0
|
0+0e0 <[^>]*> f380 8802 msr EAPSR_nzcvq, r0
|
||||||
0+0e4 <[^>]*> f380 8803 msr PSR, r0
|
0+0e4 <[^>]*> f380 8803 msr PSR_nzcvq, r0
|
||||||
0+0e8 <[^>]*> f380 8805 msr IPSR, r0
|
0+0e8 <[^>]*> f380 8805 msr IPSR, r0
|
||||||
0+0ec <[^>]*> f380 8806 msr EPSR, r0
|
0+0ec <[^>]*> f380 8806 msr EPSR, r0
|
||||||
0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
|
0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
|
||||||
|
@ -71,9 +71,9 @@ Disassembly of section .text:
|
||||||
0+0f8 <[^>]*> f380 8809 msr PSP, r0
|
0+0f8 <[^>]*> f380 8809 msr PSP, r0
|
||||||
0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
|
0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
|
||||||
0+100 <[^>]*> f380 8811 msr BASEPRI, r0
|
0+100 <[^>]*> f380 8811 msr BASEPRI, r0
|
||||||
0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0
|
0+104 <[^>]*> f380 8812 msr BASEPRI_MAX, r0
|
||||||
0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
|
0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
|
||||||
0+10c <[^>]*> f380 8814 msr CONTROL, r0
|
0+10c <[^>]*> f380 8814 msr CONTROL, r0
|
||||||
0+110 <[^>]*> f3ef 8003 mrs r0, PSR
|
0+110 <[^>]*> f3ef 8003 mrs r0, PSR
|
||||||
0+114 <[^>]*> f380 8803 msr PSR, r0
|
0+114 <[^>]*> f380 8803 msr PSR_nzcvq, r0
|
||||||
0+118 <[^>]*> df00 svc 0
|
0+118 <[^>]*> df00 svc 0
|
||||||
|
|
|
@ -63,10 +63,10 @@ label2:
|
||||||
mrs r0, basepri_max
|
mrs r0, basepri_max
|
||||||
mrs r0, faultmask
|
mrs r0, faultmask
|
||||||
mrs r0, control
|
mrs r0, control
|
||||||
msr apsr, r0
|
msr apsr_nzcvq, r0
|
||||||
msr iapsr, r0
|
msr iapsr_nzcvq, r0
|
||||||
msr eapsr, r0
|
msr eapsr_nzcvq, r0
|
||||||
msr psr, r0
|
msr psr_nzcvq, r0
|
||||||
msr ipsr, r0
|
msr ipsr, r0
|
||||||
msr epsr, r0
|
msr epsr, r0
|
||||||
msr iepsr, r0
|
msr iepsr, r0
|
||||||
|
@ -78,6 +78,6 @@ label2:
|
||||||
msr faultmask, r0
|
msr faultmask, r0
|
||||||
msr control, r0
|
msr control, r0
|
||||||
mrs r0, xpsr
|
mrs r0, xpsr
|
||||||
msr xpsr, r0
|
msr xpsr_nzcvq, r0
|
||||||
|
|
||||||
svc 0
|
svc 0
|
||||||
|
|
|
@ -5,7 +5,7 @@
|
||||||
.align 2
|
.align 2
|
||||||
.global foo
|
.global foo
|
||||||
foo:
|
foo:
|
||||||
msr apsr,r6
|
msr apsr_nzcvq,r6
|
||||||
msr epsr,r9
|
msr epsr,r9
|
||||||
mrs r2, iapsr
|
mrs r2, iapsr
|
||||||
yield
|
yield
|
||||||
|
|
|
@ -0,0 +1,16 @@
|
||||||
|
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||||
|
#name: MRS/MSR test, architecture v6, ARM mode
|
||||||
|
|
||||||
|
.*: file format .*
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section .text:
|
||||||
|
0+00 <[^>]*> e10f4000 mrs r4, CPSR
|
||||||
|
0+04 <[^>]*> e10f5000 mrs r5, CPSR
|
||||||
|
0+08 <[^>]*> e14f6000 mrs r6, SPSR
|
||||||
|
0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 ; 0x40000000
|
||||||
|
0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
|
||||||
|
0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
|
||||||
|
0+18 <[^>]*> e128f004 msr CPSR_f, r4
|
||||||
|
0+1c <[^>]*> e128f005 msr CPSR_f, r5
|
||||||
|
0+20 <[^>]*> e169f006 msr SPSR_fc, r6
|
|
@ -0,0 +1,13 @@
|
||||||
|
.arch armv6
|
||||||
|
.text
|
||||||
|
.arm
|
||||||
|
|
||||||
|
mrs r4, apsr
|
||||||
|
mrs r5, cpsr
|
||||||
|
mrs r6, spsr
|
||||||
|
msr apsr_nzcvq, #0x40000000
|
||||||
|
msr cpsr_f, #0x20000000
|
||||||
|
msr spsr, #0x10000000
|
||||||
|
msr apsr_nzcvq, r4
|
||||||
|
msr cpsr_f, r5
|
||||||
|
msr spsr, r6
|
|
@ -0,0 +1,2 @@
|
||||||
|
# name: MRS/MSR negative test, architecture v7-A, ARM mode
|
||||||
|
# error-output: mrs-msr-arm-v7-a-bad.l
|
|
@ -0,0 +1,5 @@
|
||||||
|
[^:]*: Assembler messages:
|
||||||
|
[^:]*:5: Error: 'APSR', 'CPSR' or 'SPSR' expected -- `mrs r4,apsr_nzcvq'
|
||||||
|
[^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,iapsr'
|
||||||
|
[^:]*:7: Error: selected processor does not support requested special purpose register -- `msr iapsr,r4'
|
||||||
|
[^:]*:8: writing to APSR without specifying a bitmask is deprecated
|
|
@ -0,0 +1,8 @@
|
||||||
|
.arch armv7-a
|
||||||
|
.text
|
||||||
|
.arm
|
||||||
|
|
||||||
|
mrs r4, apsr_nzcvq
|
||||||
|
mrs r5, iapsr
|
||||||
|
msr iapsr, r4
|
||||||
|
msr apsr, r5
|
|
@ -0,0 +1,16 @@
|
||||||
|
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||||
|
#name: MRS/MSR test, architecture v7-A, ARM mode
|
||||||
|
|
||||||
|
.*: file format .*
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section .text:
|
||||||
|
0+00 <[^>]*> e10f4000 mrs r4, CPSR
|
||||||
|
0+04 <[^>]*> e10f5000 mrs r5, CPSR
|
||||||
|
0+08 <[^>]*> e14f6000 mrs r6, SPSR
|
||||||
|
0+0c <[^>]*> e32cf101 msr CPSR_fs, #1073741824 ; 0x40000000
|
||||||
|
0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
|
||||||
|
0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
|
||||||
|
0+18 <[^>]*> e128f004 msr CPSR_f, r4
|
||||||
|
0+1c <[^>]*> e128f005 msr CPSR_f, r5
|
||||||
|
0+20 <[^>]*> e169f006 msr SPSR_fc, r6
|
|
@ -0,0 +1,13 @@
|
||||||
|
.arch armv7-a
|
||||||
|
.text
|
||||||
|
.arm
|
||||||
|
|
||||||
|
mrs r4, apsr
|
||||||
|
mrs r5, cpsr
|
||||||
|
mrs r6, spsr
|
||||||
|
msr apsr_nzcvqg, #0x40000000
|
||||||
|
msr cpsr_f, #0x20000000
|
||||||
|
msr spsr, #0x10000000
|
||||||
|
msr apsr_nzcvq, r4
|
||||||
|
msr cpsr_f, r5
|
||||||
|
msr spsr, r6
|
|
@ -0,0 +1,13 @@
|
||||||
|
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||||
|
#name: MRS/MSR test, architecture v6t2, Thumb mode
|
||||||
|
|
||||||
|
.*: file format .*
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section .text:
|
||||||
|
0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
|
||||||
|
0+04 <[^>]*> f3ef 8500 mrs r5, CPSR
|
||||||
|
0+08 <[^>]*> f3ff 8600 mrs r6, SPSR
|
||||||
|
0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
|
||||||
|
0+10 <[^>]*> f385 8800 msr CPSR_f, r5
|
||||||
|
0+14 <[^>]*> f396 8900 msr SPSR_fc, r6
|
|
@ -0,0 +1,10 @@
|
||||||
|
.arch armv6t2
|
||||||
|
.text
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
mrs r4, apsr
|
||||||
|
mrs r5, cpsr
|
||||||
|
mrs r6, spsr
|
||||||
|
msr apsr_nzcvqg, r4
|
||||||
|
msr cpsr_f, r5
|
||||||
|
msr spsr, r6
|
|
@ -0,0 +1,2 @@
|
||||||
|
# name: MRS/MSR negative test, architecture v7-M, Thumb mode
|
||||||
|
# error-output: mrs-msr-thumb-v7-m-bad.l
|
|
@ -0,0 +1,10 @@
|
||||||
|
[^:]*: Assembler messages:
|
||||||
|
[^:]*:5: Error: selected processor does not support requested special purpose register -- `mrs r4,cpsr'
|
||||||
|
[^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,spsr'
|
||||||
|
[^:]*:7: Error: selected processor does not support DSP extension -- `msr apsr_nzcvqg,r4'
|
||||||
|
[^:]*:8: Error: selected processor does not support DSP extension -- `msr iapsr_nzcvqg,r5'
|
||||||
|
[^:]*:9: Error: bad bitmask specified after APSR -- `msr xpsr_nncvq,r6'
|
||||||
|
[^:]*:10: Error: bad bitmask specified after APSR -- `msr xpsr_nzcv,r7'
|
||||||
|
[^:]*:11: Error: selected processor does not support requested special purpose register -- `msr cpsr_f,r7'
|
||||||
|
[^:]*:12: Error: selected processor does not support requested special purpose register -- `msr spsr,r8'
|
||||||
|
[^:]*:13: Error: syntax error -- `msr primask_nzcvq,r9'
|
|
@ -0,0 +1,13 @@
|
||||||
|
.arch armv7-m
|
||||||
|
.text
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
mrs r4, cpsr
|
||||||
|
mrs r5, spsr
|
||||||
|
msr apsr_nzcvqg, r4
|
||||||
|
msr iapsr_nzcvqg, r5
|
||||||
|
msr xpsr_nncvq, r6
|
||||||
|
msr xpsr_nzcv, r7
|
||||||
|
msr cpsr_f, r7
|
||||||
|
msr spsr, r8
|
||||||
|
msr primask_nzcvq, r9
|
|
@ -0,0 +1,15 @@
|
||||||
|
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||||
|
#name: MRS/MSR test, architecture v7-M, Thumb mode
|
||||||
|
|
||||||
|
|
||||||
|
.*: file format .*
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section .text:
|
||||||
|
0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
|
||||||
|
0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
|
||||||
|
0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
|
||||||
|
0+0c <[^>]*> f383 8803 msr PSR_nzcvq, r3
|
||||||
|
0+10 <[^>]*> f384 8800 msr CPSR_f, r4
|
||||||
|
0+14 <[^>]*> f385 8801 msr IAPSR_nzcvq, r5
|
||||||
|
0+18 <[^>]*> f386 8810 msr PRIMASK, r6
|
|
@ -0,0 +1,11 @@
|
||||||
|
.arch armv7-m
|
||||||
|
.text
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
mrs r4, apsr
|
||||||
|
mrs r5, eapsr
|
||||||
|
mrs r6, primask
|
||||||
|
msr xpsr_nzcvq, r3
|
||||||
|
msr apsr_nzcvq, r4
|
||||||
|
msr iapsr_nzcvq, r5
|
||||||
|
msr primask, r6
|
|
@ -0,0 +1,13 @@
|
||||||
|
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||||
|
#name: MRS/MSR test, architecture v7e-M, Thumb mode
|
||||||
|
|
||||||
|
.*: file format .*
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section .text:
|
||||||
|
0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
|
||||||
|
0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
|
||||||
|
0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
|
||||||
|
0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
|
||||||
|
0+10 <[^>]*> f385 8401 msr IAPSR_g, r5
|
||||||
|
0+14 <[^>]*> f386 8812 msr BASEPRI_MAX, r6
|
|
@ -0,0 +1,10 @@
|
||||||
|
.arch armv7e-m
|
||||||
|
.text
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
mrs r4, apsr
|
||||||
|
mrs r5, eapsr
|
||||||
|
mrs r6, primask
|
||||||
|
msr apsr_nzcvqg, r4
|
||||||
|
msr iapsr_g, r5
|
||||||
|
msr basepri_max, r6
|
|
@ -1,5 +1,5 @@
|
||||||
[^:]*: Assembler messages:
|
[^:]*: Assembler messages:
|
||||||
[^:]*:9: Error: Thumb encoding does not support an immediate here -- `msr APSR,#0xc0000004'
|
[^:]*:9: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
|
||||||
[^:]*:10: Error: Thumb encoding does not support an immediate here -- `msr APSR_g,#0xc0000004'
|
[^:]*:10: Error: Thumb encoding does not support an immediate here -- `msr APSR_g,#0xc0000004'
|
||||||
[^:]*:11: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
|
[^:]*:11: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
|
||||||
[^:]*:12: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvqg,#0xc0000004'
|
[^:]*:12: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvqg,#0xc0000004'
|
||||||
|
|
|
@ -5,7 +5,7 @@
|
||||||
.*: +file format .*arm.*
|
.*: +file format .*arm.*
|
||||||
|
|
||||||
Disassembly of section .text:
|
Disassembly of section .text:
|
||||||
00000000 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
|
00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
|
||||||
00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
|
00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
|
||||||
00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
|
00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
|
||||||
0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
|
0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
|
||||||
|
|
|
@ -6,7 +6,7 @@
|
||||||
|
|
||||||
@ Write to Special Register from Immediate
|
@ Write to Special Register from Immediate
|
||||||
@ Write to application status register
|
@ Write to application status register
|
||||||
msr APSR,#0xc0000004
|
msr APSR_nzcvq,#0xc0000004
|
||||||
msr APSR_g,#0xc0000004
|
msr APSR_g,#0xc0000004
|
||||||
msr APSR_nzcvq,#0xc0000004
|
msr APSR_nzcvq,#0xc0000004
|
||||||
msr APSR_nzcvqg,#0xc0000004
|
msr APSR_nzcvqg,#0xc0000004
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
[^:]*: Assembler messages:
|
[^:]*: Assembler messages:
|
||||||
[^:]*:9: Error: syntax error -- `msr APSR_g,r9'
|
[^:]*:8: writing to APSR without specifying a bitmask is deprecated
|
||||||
[^:]*:10: Error: syntax error -- `msr APSR_nzcvq,r9'
|
[^:]*:9: Error: selected processor does not support DSP extension -- `msr APSR_g,r9'
|
||||||
[^:]*:11: Error: syntax error -- `msr APSR_nzcvqg,r9'
|
[^:]*:11: Error: selected processor does not support DSP extension -- `msr APSR_nzcvqg,r9'
|
||||||
[^:]*:14: Error: selected processor does not support requested special purpose register -- `msr CPSR,r9'
|
[^:]*:14: Error: selected processor does not support requested special purpose register -- `msr CPSR,r9'
|
||||||
[^:]*:15: Error: selected processor does not support requested special purpose register -- `msr CPSR_s,r9'
|
[^:]*:15: Error: selected processor does not support requested special purpose register -- `msr CPSR_s,r9'
|
||||||
[^:]*:16: Error: selected processor does not support requested special purpose register -- `msr CPSR_f,r9'
|
[^:]*:16: Error: selected processor does not support requested special purpose register -- `msr CPSR_f,r9'
|
||||||
|
|
|
@ -2,12 +2,13 @@
|
||||||
# as: -march=armv7-a -mthumb
|
# as: -march=armv7-a -mthumb
|
||||||
# source: msr-reg.s
|
# source: msr-reg.s
|
||||||
# objdump: -dr --prefix-addresses --show-raw-insn
|
# objdump: -dr --prefix-addresses --show-raw-insn
|
||||||
|
# warning: writing to APSR without specifying a bitmask is deprecated
|
||||||
# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
|
# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
|
||||||
|
|
||||||
.*: +file format .*arm.*
|
.*: +file format .*arm.*
|
||||||
|
|
||||||
Disassembly of section .text:
|
Disassembly of section .text:
|
||||||
00000000 <[^>]*> f389 8900 msr CPSR_fc, r9
|
00000000 <[^>]*> f389 8800 msr CPSR_f, r9
|
||||||
00000004 <[^>]*> f389 8400 msr CPSR_s, r9
|
00000004 <[^>]*> f389 8400 msr CPSR_s, r9
|
||||||
00000008 <[^>]*> f389 8800 msr CPSR_f, r9
|
00000008 <[^>]*> f389 8800 msr CPSR_f, r9
|
||||||
0000000c <[^>]*> f389 8c00 msr CPSR_fs, r9
|
0000000c <[^>]*> f389 8c00 msr CPSR_fs, r9
|
||||||
|
|
|
@ -1,11 +1,12 @@
|
||||||
# name: MSR register operands
|
# name: MSR register operands
|
||||||
# as: -march=armv7-a
|
# as: -march=armv7-a
|
||||||
# objdump: -dr --prefix-addresses --show-raw-insn
|
# objdump: -dr --prefix-addresses --show-raw-insn
|
||||||
|
# warning: writing to APSR without specifying a bitmask is deprecated
|
||||||
|
|
||||||
.*: +file format .*arm.*
|
.*: +file format .*arm.*
|
||||||
|
|
||||||
Disassembly of section .text:
|
Disassembly of section .text:
|
||||||
00000000 <[^>]*> e129f009 msr CPSR_fc, r9
|
00000000 <[^>]*> e128f009 msr CPSR_f, r9
|
||||||
00000004 <[^>]*> e124f009 msr CPSR_s, r9
|
00000004 <[^>]*> e124f009 msr CPSR_s, r9
|
||||||
00000008 <[^>]*> e128f009 msr CPSR_f, r9
|
00000008 <[^>]*> e128f009 msr CPSR_f, r9
|
||||||
0000000c <[^>]*> e12cf009 msr CPSR_fs, r9
|
0000000c <[^>]*> e12cf009 msr CPSR_fs, r9
|
||||||
|
|
|
@ -5,7 +5,7 @@
|
||||||
.syntax unified
|
.syntax unified
|
||||||
|
|
||||||
@ Write to Special Register from register
|
@ Write to Special Register from register
|
||||||
msr APSR,r9
|
msr APSR,r9 @ deprecated usage.
|
||||||
msr APSR_g,r9
|
msr APSR_g,r9
|
||||||
msr APSR_nzcvq,r9
|
msr APSR_nzcvq,r9
|
||||||
msr APSR_nzcvqg,r9
|
msr APSR_nzcvqg,r9
|
||||||
|
|
|
@ -1,3 +1,8 @@
|
||||||
|
2011-04-11 Julian Brown <julian@codesourcery.com>
|
||||||
|
|
||||||
|
* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
|
||||||
|
(print_insn_thumb32): Add APSR bitmask support.
|
||||||
|
|
||||||
2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
|
2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
|
||||||
|
|
||||||
* arm-dis.c (print_insn): init vars moved into private_data structure.
|
* arm-dis.c (print_insn): init vars moved into private_data structure.
|
||||||
|
|
|
@ -3721,7 +3721,7 @@ psr_name (int regno)
|
||||||
case 9: return "PSP";
|
case 9: return "PSP";
|
||||||
case 16: return "PRIMASK";
|
case 16: return "PRIMASK";
|
||||||
case 17: return "BASEPRI";
|
case 17: return "BASEPRI";
|
||||||
case 18: return "BASEPRI_MASK";
|
case 18: return "BASEPRI_MAX";
|
||||||
case 19: return "FAULTMASK";
|
case 19: return "FAULTMASK";
|
||||||
case 20: return "CONTROL";
|
case 20: return "CONTROL";
|
||||||
default: return "<unknown>";
|
default: return "<unknown>";
|
||||||
|
@ -4191,6 +4191,15 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
|
||||||
else
|
else
|
||||||
func (stream, "(UNDEF: %lu)", sysm);
|
func (stream, "(UNDEF: %lu)", sysm);
|
||||||
}
|
}
|
||||||
|
else if ((given & 0xff) <= 3)
|
||||||
|
{
|
||||||
|
func (stream, "%s_", psr_name (given & 0xff));
|
||||||
|
|
||||||
|
if (given & 0x800)
|
||||||
|
func (stream, "nzcvq");
|
||||||
|
if (given & 0x400)
|
||||||
|
func (stream, "g");
|
||||||
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
func (stream, psr_name (given & 0xff));
|
func (stream, psr_name (given & 0xff));
|
||||||
|
|
Loading…
Reference in New Issue