Add new mnemonics for VLE multiple load instructions
opcodes/ * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw, e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for VLE multimple load/store instructions. Old e_ldm* variants are kept as aliases. Add missing e_lmvmcsrrw and e_stmvmcsrrw. gas/ * testsuite/gas/ppc/vle-mult-ld-st-insns.s: New file: Tests the support for the VLE multiple load/store instructions. * testsuite/gas/ppc/vle-mult-ld-st-insns.d: New file: Test driver. * testsuite/gas/ppc/ppc.exp: Run it.
This commit is contained in:
Alexander Fedotov
Alan Modra
parent
4b04bba2eb
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d2e6c9a368
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@ -1,3 +1,11 @@
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2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
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* testsuite/gas/ppc/vle-mult-ld-st-insns.s: New file: Tests the
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support for the VLE multiple load/store instructions.
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* testsuite/gas/ppc/vle-mult-ld-st-insns.d: New file: Test
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driver.
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* testsuite/gas/ppc/ppc.exp: Run it.
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2017-09-27 Nick Clifton <nickc@redhat.com>
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PR 22179
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@ -60,6 +60,7 @@ if { [istarget powerpc*-*-*] } then {
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run_dump_test "vle-simple-4"
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run_dump_test "vle-simple-5"
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run_dump_test "vle-simple-6"
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run_dump_test "vle-mult-ld-st-insns"
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#fail expected until get_powerpc_dialect() patch not applied
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setup_xfail "*-*-*"
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@ -0,0 +1,28 @@
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#as: -a32 -mvle -mregnames
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#objdump: -dr -Mvle
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#name: VLE Instructions for improving interrupt handler efficiency
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.*: +file format elf.*-powerpc.*
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Disassembly of section .text:
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00000000 <prolog>:
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0: 18 01 11 00 e_stmvgprw 0\(r1\)
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4: 18 22 11 04 e_stmvsprw 4\(r2\)
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8: 18 83 11 08 e_stmvsrrw 8\(r3\)
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c: 18 a4 11 0c e_stmvcsrrw 12\(r4\)
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10: 18 c5 11 10 e_stmvdsrrw 16\(r5\)
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14: 18 e6 11 14 e_stmvmcsrrw 20\(r6\)
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00000018 <epilog>:
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18: 18 07 10 18 e_lmvgprw 24\(r7\)
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1c: 18 28 10 1c e_lmvsprw 28\(r8\)
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20: 18 89 10 20 e_lmvsrrw 32\(r9\)
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24: 18 aa 10 24 e_lmvcsrrw 36\(r10\)
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28: 18 cb 10 28 e_lmvdsrrw 40\(r11\)
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2c: 18 ec 10 2c e_lmvmcsrrw 44\(r12\)
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00000030 <epilog_alt>:
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30: 18 0d 10 30 e_lmvgprw 48\(r13\)
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34: 18 2e 10 34 e_lmvsprw 52\(r14\)
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38: 18 8f 10 38 e_lmvsrrw 56\(r15\)
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3c: 18 b0 10 3c e_lmvcsrrw 60\(r16\)
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40: 18 d1 10 40 e_lmvdsrrw 64\(r17\)
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@ -0,0 +1,34 @@
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# VLE Instructions for Improving Interrupt Handler Efficiency (e200z760RM.pdf)
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# Original Engineering Bullet (EB696.pdf) contains two writings of load instructions
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# and has no ones for MCSRRs.
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# e_lmvgprw, e_stmvgprw - load/store multiple volatile GPRs (r0, r3:r12)
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# e_lmvsprw, e_stmvsprw - load/store multiple volatile SPRs (CR, LR, CTR, and XER)
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# e_lmvsrrw, e_stmvsrrw - load/store multiple volatile SRRs (SRR0, SRR1)
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# e_lmvcsrrw, e_stmvcsrrw - load/store multiple volatile CSRRs (CSRR0, CSRR1)
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# e_lmvdsrrw, e_stmvdsrrw - load/store multiple volatile DSRRs (DSRR0, DSRR1)
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# e_lmvmcsrrw, e_stmvmcsrrw - load/store multiple volatile MCSRRs (MCSRR0, MCSRR1)
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.text
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prolog:
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e_stmvgprw 0x00 (r1)
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e_stmvsprw 0x04 (r2)
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e_stmvsrrw 0x08 (r3)
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e_stmvcsrrw 0x0c (r4)
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e_stmvdsrrw 0x10 (r5)
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e_stmvmcsrrw 0x14 (r6)
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epilog:
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e_lmvgprw 0x18 (r7)
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e_lmvsprw 0x1c (r8)
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e_lmvsrrw 0x20 (r9)
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e_lmvcsrrw 0x24 (r10)
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e_lmvdsrrw 0x28 (r11)
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e_lmvmcsrrw 0x2c (r12)
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epilog_alt:
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e_ldmvgprw 0x30 (r13)
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e_ldmvsprw 0x34 (r14)
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e_ldmvsrrw 0x38 (r15)
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e_ldmvcsrrw 0x3c (r16)
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e_ldmvdsrrw 0x40 (r17)
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@ -1,3 +1,11 @@
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2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
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* ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
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e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
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VLE multimple load/store instructions. Old e_ldm* variants are
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kept as aliases.
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Add missing e_lmvmcsrrw and e_stmvmcsrrw.
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2017-09-27 Nick Clifton <nickc@redhat.com>
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PR 22179
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@ -8315,16 +8315,23 @@ const struct powerpc_opcode vle_opcodes[] = {
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{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
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{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
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{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
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{"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
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{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
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{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
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