* sparc-dis.c (opcodes_initialized): Move inside print_insn_sparc.
(current_arch_mask): New static global. (compute_arch_mask): New static function. (print_insn_sparc): Delete sparc_v9_p. New static local current_mach. Resort opcode table if current_mach changes. Generalize "insn not supported" test. (compare_opcodes): Prefer supported opcodes to nonsupported ones. Delete test for v9/!v9. * sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK. (v6notlet): Define. (brfc): Split into CBR and FBR for coprocessor/fp branches. (brfcx): Renamed to FBRX. (condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard coprocessor mnemonics are not supported on the sparclet). (condf): Renamed to CONDF. (SLCBCC2): Delete F_ALIAS flag.
This commit is contained in:
David Edelsohn
parent
d1f74cd2c3
commit
d302b5f240
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@ -1,3 +1,22 @@
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Wed Apr 3 10:40:45 1996 Doug Evans <dje@canuck.cygnus.com>
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* sparc-dis.c (opcodes_initialized): Move inside print_insn_sparc.
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(current_arch_mask): New static global.
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(compute_arch_mask): New static function.
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(print_insn_sparc): Delete sparc_v9_p. New static local
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current_mach. Resort opcode table if current_mach changes.
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Generalize "insn not supported" test.
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(compare_opcodes): Prefer supported opcodes to nonsupported ones.
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Delete test for v9/!v9.
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* sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK.
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(v6notlet): Define.
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(brfc): Split into CBR and FBR for coprocessor/fp branches.
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(brfcx): Renamed to FBRX.
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(condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard
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coprocessor mnemonics are not supported on the sparclet).
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(condf): Renamed to CONDF.
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(SLCBCC2): Delete F_ALIAS flag.
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Sat Mar 30 21:45:59 1996 Doug Evans <dje@canuck.cygnus.com>
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* sparc-opc.c (sparc_opcodes): rd must be 0 for
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@ -175,12 +175,14 @@ is_delayed_branch (insn)
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return 0;
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}
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/* Nonzero of opcode table has been initialized. */
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static int opcodes_initialized = 0;
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/* extern void qsort (); */
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static int compare_opcodes ();
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/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
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to compare_opcodes. */
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static unsigned int current_arch_mask;
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static int compute_arch_mask ();
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/* Print one instruction from MEMADDR on INFO->STREAM.
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We suffix the instruction with a comment that gives the absolute
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@ -199,13 +201,19 @@ print_insn_sparc (memaddr, info)
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unsigned long insn;
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register unsigned int i;
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register struct opcode_hash *op;
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int sparc_v9_p = bfd_mach_sparc_v9_p (info->mach);
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/* Nonzero of opcode table has been initialized. */
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static int opcodes_initialized = 0;
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/* bfd mach number of last call. */
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static unsigned long current_mach = 0;
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if (!opcodes_initialized)
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if (!opcodes_initialized
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|| info->mach != current_mach)
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{
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current_arch_mask = compute_arch_mask (info->mach);
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qsort ((char *) sparc_opcodes, sparc_num_opcodes,
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sizeof (sparc_opcodes[0]), compare_opcodes);
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build_hash_table (sparc_opcodes, opcode_hash_table, sparc_num_opcodes);
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current_mach = info->mach;
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opcodes_initialized = 1;
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}
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@ -230,16 +238,8 @@ print_insn_sparc (memaddr, info)
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{
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CONST struct sparc_opcode *opcode = op->opcode;
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/* ??? These architecture tests need to be more selective. */
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/* If the current architecture isn't sparc64, skip sparc64 insns. */
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if (!sparc_v9_p
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&& V9_ONLY_P (opcode))
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continue;
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/* If the current architecture is sparc64, skip sparc32 only insns. */
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if (sparc_v9_p
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&& ! V9_P (opcode))
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/* If the insn isn't supported by the current architecture, skip it. */
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if (! (opcode->architecture & current_arch_mask))
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continue;
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if ((opcode->match & insn) == opcode->match
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@ -267,6 +267,10 @@ print_insn_sparc (memaddr, info)
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&& strchr (opcode->args, 'r') != 0)
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/* Can't do simple format if source and dest are different. */
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continue;
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if (X_RS2 (insn) != X_RD (insn)
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&& strchr (opcode->args, 'O') != 0)
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/* Can't do simple format if source and dest are different. */
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continue;
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(*info->fprintf_func) (stream, opcode->name);
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@ -325,6 +329,7 @@ print_insn_sparc (memaddr, info)
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break;
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case '2':
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case 'O':
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reg (X_RS2 (insn));
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break;
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@ -691,6 +696,34 @@ print_insn_sparc (memaddr, info)
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return sizeof (buffer);
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}
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/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
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static int
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compute_arch_mask (unsigned long mach)
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{
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switch (mach)
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{
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case 0 :
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case bfd_mach_sparc :
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return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
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case bfd_mach_sparc_sparclet :
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return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
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case bfd_mach_sparc_sparclite :
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/* sparclites insns are recognized by default (because that's how
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they've always been treated, for better or worse). Kludge this by
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indicating generic v8 is also selected. */
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return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
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| SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
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case bfd_mach_sparc_v8plus :
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case bfd_mach_sparc_v9 :
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return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
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case bfd_mach_sparc_v8plusa :
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case bfd_mach_sparc_v9a :
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return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
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}
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abort ();
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}
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/* Compare opcodes A and B. */
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static int
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@ -703,6 +736,24 @@ compare_opcodes (a, b)
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unsigned long int lose0 = op0->lose, lose1 = op1->lose;
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register unsigned int i;
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/* If one (and only one) insn isn't supported by the current architecture,
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prefer the one that is. If neither are supported, but they're both for
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the same architecture, continue processing. Otherwise (both unsupported
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and for different architectures), prefer lower numbered arch's (fudged
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by comparing the bitmasks). */
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if (op0->architecture & current_arch_mask)
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{
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if (! (op1->architecture & current_arch_mask))
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return -1;
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}
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else
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{
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if (op1->architecture & current_arch_mask)
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return 1;
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else if (op0->architecture != op1->architecture)
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return op0->architecture - op1->architecture;
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}
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/* If a bit is set in both match and lose, there is something
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wrong with the opcode table. */
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if (match0 & lose0)
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@ -743,10 +794,6 @@ compare_opcodes (a, b)
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return x1 - x0;
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}
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/* Put non-sparc64 insns ahead of sparc64 ones. */
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if (V9_ONLY_P (op0) != V9_ONLY_P (op1))
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return V9_ONLY_P (op0) - V9_ONLY_P (op1);
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/* They are functionally equal. So as long as the opcode table is
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valid, we can put whichever one first we want, on aesthetic grounds. */
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@ -762,12 +809,14 @@ compare_opcodes (a, b)
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better have the same opcode. This is a sanity check on the table. */
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i = strcmp (op0->name, op1->name);
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if (i)
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{
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if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
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return i;
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return i;
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else
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fprintf (stderr,
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"Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
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op0->name, op1->name);
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fprintf (stderr,
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"Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
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op0->name, op1->name);
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}
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/* Fewer arguments are preferred. */
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{
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@ -29,18 +29,21 @@ Boston, MA 02111-1307, USA. */
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#include "opcode/sparc.h"
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/* Some defines to make life easy. */
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#define MASK_V6 (1 << SPARC_OPCODE_ARCH_V6)
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#define MASK_V7 (1 << SPARC_OPCODE_ARCH_V7)
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#define MASK_V8 (1 << SPARC_OPCODE_ARCH_V8)
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#define MASK_SPARCLET (1 << SPARC_OPCODE_ARCH_SPARCLET)
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#define MASK_SPARCLITE (1 << SPARC_OPCODE_ARCH_SPARCLITE)
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#define MASK_V9 (1 << SPARC_OPCODE_ARCH_V9)
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#define MASK_V9A (1 << SPARC_OPCODE_ARCH_V9A)
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#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
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#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
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#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
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#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
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#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
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#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
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#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
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/* Bit masks of architectures supporting the insn. */
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#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
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| MASK_SPARCLITE | MASK_V9 | MASK_V9A)
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/* v6 insns not supported on the sparclet */
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#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
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| MASK_SPARCLITE | MASK_V9 | MASK_V9A)
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#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
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| MASK_SPARCLITE | MASK_V9 | MASK_V9A)
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/* Although not all insns are implemented in hardware, sparclite is defined
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@ -59,7 +62,9 @@ Boston, MA 02111-1307, USA. */
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| MASK_SPARCLET | MASK_SPARCLITE)
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/* Table of opcode architectures.
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The order is defined in opcode/sparc.h. */
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The order is defined in opcode/sparc.h.
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The names must match the arguments to gas' -A<arch> option in tc-sparc.c.
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*/
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const struct sparc_opcode_arch sparc_opcode_archs[] = {
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{ "v6", MASK_V6 },
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{ "v7", MASK_V6 | MASK_V7 },
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@ -67,6 +72,7 @@ const struct sparc_opcode_arch sparc_opcode_archs[] = {
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{ "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
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{ "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
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/* ??? Don't some v8 priviledged insns conflict with v9? */
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/* ??? Will we want v8plus{,a} entries? */
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{ "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
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/* v9 with ultrasparc additions */
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{ "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
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@ -979,12 +985,12 @@ cond ("bcc", "tcc", CONDCC, F_CONDBR),
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cond ("bcs", "tcs", CONDCS, F_CONDBR),
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cond ("be", "te", CONDE, F_CONDBR),
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cond ("bg", "tg", CONDG, F_CONDBR),
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cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS),
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cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS),
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cond ("bge", "tge", CONDGE, F_CONDBR),
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cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
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cond ("bgu", "tgu", CONDGU, F_CONDBR),
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cond ("bl", "tl", CONDL, F_CONDBR),
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cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS),
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cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS),
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cond ("ble", "tle", CONDLE, F_CONDBR),
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cond ("bleu", "tleu", CONDLEU, F_CONDBR),
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cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */
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@ -1249,11 +1255,18 @@ cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
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#undef FM_QF /* v9 */
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#undef FM_SF /* v9 */
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#define brfc(opcode, mask, lose, flags) \
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/* Coprocessor branches. */
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#define CBR(opcode, mask, lose, flags, arch) \
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{ opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \
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{ opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch }
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/* Floating point branches. */
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#define FBR(opcode, mask, lose, flags) \
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{ opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, v6 }, \
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{ opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, v6 }
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#define brfcx(opcode, mask, lose, flags) /* v9 */ \
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/* V9 extended floating point branches. */
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#define FBRX(opcode, mask, lose, flags) /* v9 */ \
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{ opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED, v9 }, \
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{ opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED, v9 }, \
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{ opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED, v9 }, \
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@ -1279,43 +1292,51 @@ cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
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{ opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED, v9 }, \
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{ opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED, v9 }
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/* v9: We must put `brfcx' before `brfc', to ensure that we never match
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/* v9: We must put `FBRX' before `FBR', to ensure that we never match
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v9: something against an expression unless it is an expression. Otherwise,
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v9: we end up with undefined symbol tables entries, because they get added,
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v9: but are not deleted if the pattern fails to match. */
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#define condfc(fop, cop, mask, flags) \
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brfcx(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
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brfc(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
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brfc(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags)
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#define CONDFC(fop, cop, mask, flags) \
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FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
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FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
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CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
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#define condf(fop, mask, flags) \
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brfcx(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
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brfc(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
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#define CONDFCL(fop, cop, mask, flags) \
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FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
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FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
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CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
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condfc("fb", "cb", 0x8, 0),
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condfc("fba", "cba", 0x8, F_ALIAS),
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condfc("fbe", "cb0", 0x9, 0),
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condf("fbz", 0x9, F_ALIAS),
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condfc("fbg", "cb2", 0x6, 0),
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condfc("fbge", "cb02", 0xb, 0),
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condfc("fbl", "cb1", 0x4, 0),
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condfc("fble", "cb01", 0xd, 0),
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condfc("fblg", "cb12", 0x2, 0),
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condfc("fbn", "cbn", 0x0, 0),
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condfc("fbne", "cb123", 0x1, 0),
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condf("fbnz", 0x1, F_ALIAS),
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condfc("fbo", "cb012", 0xf, 0),
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condfc("fbu", "cb3", 0x7, 0),
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condfc("fbue", "cb03", 0xa, 0),
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condfc("fbug", "cb23", 0x5, 0),
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condfc("fbuge", "cb023", 0xc, 0),
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condfc("fbul", "cb13", 0x3, 0),
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condfc("fbule", "cb013", 0xe, 0),
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#define CONDF(fop, mask, flags) \
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FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
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FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
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#undef condfc
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#undef brfc
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#undef brfcx /* v9 */
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CONDFC ("fb", "cb", 0x8, 0),
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CONDFCL ("fba", "cba", 0x8, F_ALIAS),
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CONDFC ("fbe", "cb0", 0x9, 0),
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CONDF ("fbz", 0x9, F_ALIAS),
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CONDFC ("fbg", "cb2", 0x6, 0),
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CONDFC ("fbge", "cb02", 0xb, 0),
|
||||
CONDFC ("fbl", "cb1", 0x4, 0),
|
||||
CONDFC ("fble", "cb01", 0xd, 0),
|
||||
CONDFC ("fblg", "cb12", 0x2, 0),
|
||||
CONDFCL ("fbn", "cbn", 0x0, 0),
|
||||
CONDFC ("fbne", "cb123", 0x1, 0),
|
||||
CONDF ("fbnz", 0x1, F_ALIAS),
|
||||
CONDFC ("fbo", "cb012", 0xf, 0),
|
||||
CONDFC ("fbu", "cb3", 0x7, 0),
|
||||
CONDFC ("fbue", "cb03", 0xa, 0),
|
||||
CONDFC ("fbug", "cb23", 0x5, 0),
|
||||
CONDFC ("fbuge", "cb023", 0xc, 0),
|
||||
CONDFC ("fbul", "cb13", 0x3, 0),
|
||||
CONDFC ("fbule", "cb013", 0xe, 0),
|
||||
|
||||
#undef CONDFC
|
||||
#undef CONDFCL
|
||||
#undef CONDF
|
||||
#undef CBR
|
||||
#undef FBR
|
||||
#undef FBRX /* v9 */
|
||||
|
||||
{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
|
||||
{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
|
||||
|
|
@ -1516,14 +1537,14 @@ COMMUTEOP ("smuld", 0x0d, sparclet),
|
|||
{ "cpull", F3(2, 0x36, 0)|ASI(2), F3(~2, ~0x36, ~0)|ASI(~2)|RS1(~0)|RS2(~0), "d", 0, sparclet },
|
||||
|
||||
/* sparclet coprocessor branch insns */
|
||||
/* FIXME: We have to mark these as aliases until we can sort opcodes based
|
||||
on selected cpu. */
|
||||
#define SLCBCC2(opcode, mask, lose) \
|
||||
{ opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR|F_ALIAS, sparclet }, \
|
||||
{ opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR|F_ALIAS, sparclet }
|
||||
{ opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \
|
||||
{ opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
|
||||
#define SLCBCC(opcode, mask) \
|
||||
SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
|
||||
|
||||
/* cbn,cba can't be defined here because they're defined elsewhere and GAS
|
||||
requires all mnemonics of the same name to be consecutive. */
|
||||
/*SLCBCC("cbn", 0), - already defined */
|
||||
SLCBCC("cbe", 1),
|
||||
SLCBCC("cbf", 2),
|
||||
|
|
|
|||
Loading…
Reference in New Issue