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2006-07-15 H.J. Lu <hongjiu.lu@intel.com> 

* config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and
	CpuAmdFam10.
	(smallest_imm_type): Remove Cpu086.
	(i386_target_format): Likewise.

	* config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10.
	Update CpuXXX.
This commit is contained in:
H.J. Lu 2006-07-15 16:32:48 +00:00
parent 9691cba8cb
commit d32cad6576
3 changed files with 67 additions and 60 deletions
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10
gas/ChangeLog
View File

@ -1,3 +1,13 @@
2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and
CpuAmdFam10.
(smallest_imm_type): Remove Cpu086.
(i386_target_format): Likewise.
* config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10.
Update CpuXXX.
2006-07-13 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Michael Meissner <michael.meissner@amd.com>

64
gas/config/tc-i386.c
View File

@ -434,67 +434,67 @@ const relax_typeS md_relax_table[] =
static const arch_entry cpu_arch[] =
{
{"generic32", PROCESSOR_GENERIC32,
Cpu086|Cpu186|Cpu286|Cpu386},
Cpu186|Cpu286|Cpu386},
{"generic64", PROCESSOR_GENERIC64,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
|CpuMMX2|CpuSSE|CpuSSE2},
{"i8086", PROCESSOR_UNKNOWN,
Cpu086},
0},
{"i186", PROCESSOR_UNKNOWN,
Cpu086|Cpu186},
Cpu186},
{"i286", PROCESSOR_UNKNOWN,
Cpu086|Cpu186|Cpu286},
Cpu186|Cpu286},
{"i386", PROCESSOR_GENERIC32,
Cpu086|Cpu186|Cpu286|Cpu386},
Cpu186|Cpu286|Cpu386},
{"i486", PROCESSOR_I486,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486},
Cpu186|Cpu286|Cpu386|Cpu486},
{"i586", PROCESSOR_PENTIUM,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
{"i686", PROCESSOR_PENTIUMPRO,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
{"pentium", PROCESSOR_PENTIUM,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
{"pentiumpro",PROCESSOR_PENTIUMPRO,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
{"pentiumii", PROCESSOR_PENTIUMPRO,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
{"pentiumiii",PROCESSOR_PENTIUMPRO,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2
|CpuSSE},
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
{"pentium4", PROCESSOR_PENTIUM4,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
|CpuMMX2|CpuSSE|CpuSSE2},
{"prescott", PROCESSOR_NOCONA,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
{"nocona", PROCESSOR_NOCONA,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
{"yonah", PROCESSOR_YONAH,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
{"merom", PROCESSOR_MEROM,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuMNI},
{"k6", PROCESSOR_K6,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
{"k6_2", PROCESSOR_K6,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
{"athlon", PROCESSOR_ATHLON,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
{"sledgehammer", PROCESSOR_K8,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
{"opteron", PROCESSOR_K8,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
{"k8", PROCESSOR_K8,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
{"amdfam10", PROCESSOR_AMDFAM10,
Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
|CpuSledgehammer|CpuAmdFam10|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM},
Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
|CpuABM},
{".mmx", PROCESSOR_UNKNOWN,
CpuMMX},
{".sse", PROCESSOR_UNKNOWN,
@ -936,7 +936,7 @@ static int
smallest_imm_type (num)
offsetT num;
{
if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
{
/* This code is disabled on the 486 because all the Imm1 forms
in the opcode table are slower on the i486. They're the
@ -5942,11 +5942,11 @@ i386_target_format ()
{
set_code_flag (CODE_64BIT);
if (cpu_arch_isa_flags == 0)
cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
|CpuSSE|CpuSSE2;
if (cpu_arch_tune_flags == 0)
cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
|CpuSSE|CpuSSE2;
}
@ -5954,9 +5954,9 @@ i386_target_format ()
{
set_code_flag (CODE_32BIT);
if (cpu_arch_isa_flags == 0)
cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386;
cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
if (cpu_arch_tune_flags == 0)
cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386;
cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
}
else
as_fatal (_("Unknown architecture"));

53
gas/config/tc-i386.h
View File

@ -162,41 +162,38 @@ typedef struct
/* cpu feature flags */
unsigned int cpu_flags;
#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
#define Cpu186 0x2 /* i186 or better required */
#define Cpu286 0x4 /* i286 or better required */
#define Cpu386 0x8 /* i386 or better required */
#define Cpu486 0x10 /* i486 or better required */
#define Cpu586 0x20 /* i585 or better required */
#define Cpu686 0x40 /* i686 or better required */
#define CpuP4 0x80 /* Pentium4 or better required */
#define CpuK6 0x100 /* AMD K6 or better required*/
#define CpuAthlon 0x200 /* AMD Athlon or better required*/
#define CpuSledgehammer 0x400 /* Sledgehammer or better required */
#define CpuMMX 0x800 /* MMX support required */
#define CpuMMX2 0x1000 /* extended MMX support (with SSE or 3DNow!Ext) required */
#define CpuSSE 0x2000 /* Streaming SIMD extensions required */
#define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */
#define Cpu3dnow 0x8000 /* 3dnow! support required */
#define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */
#define CpuSSE3 0x20000 /* Streaming SIMD extensions 3 required */
#define Cpu186 0x1 /* i186 or better required */
#define Cpu286 0x2 /* i286 or better required */
#define Cpu386 0x4 /* i386 or better required */
#define Cpu486 0x8 /* i486 or better required */
#define Cpu586 0x10 /* i585 or better required */
#define Cpu686 0x20 /* i686 or better required */
#define CpuP4 0x40 /* Pentium4 or better required */
#define CpuK6 0x80 /* AMD K6 or better required*/
#define CpuSledgehammer 0x100 /* Sledgehammer or better required */
#define CpuMMX 0x200 /* MMX support required */
#define CpuMMX2 0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */
#define CpuSSE 0x800 /* Streaming SIMD extensions required */
#define CpuSSE2 0x1000 /* Streaming SIMD extensions 2 required */
#define Cpu3dnow 0x2000 /* 3dnow! support required */
#define Cpu3dnowA 0x4000 /* 3dnow!Extensions support required */
#define CpuSSE3 0x8000 /* Streaming SIMD extensions 3 required */
#define CpuPNI CpuSSE3 /* Prescott New Instructions required */
#define CpuPadLock 0x40000 /* VIA PadLock required */
#define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */
#define CpuVMX 0x100000 /* VMX Instructions required */
#define CpuMNI 0x200000 /* Merom New Instructions required */
#define CpuSSE4a 0x400000 /* SSE4a New Instuctions required */
#define CpuABM 0x800000 /* ABM New Instructions required */
#define CpuAmdFam10 0x1000000 /* AmdFam10 New instructions required */
#define CpuPadLock 0x10000 /* VIA PadLock required */
#define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */
#define CpuVMX 0x40000 /* VMX Instructions required */
#define CpuMNI 0x80000 /* Merom New Instructions required */
#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */
#define CpuABM 0x200000 /* ABM New Instructions required */
/* These flags are set by gas depending on the flag_code. */
#define Cpu64 0x4000000 /* 64bit support required */
#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
/* The default value for unknown CPUs - enable all features to avoid problems. */
#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|CpuP4|CpuSledgehammer|CpuAmdFam10|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME|CpuMNI|CpuABM|CpuSSE4a)
#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuMNI|CpuABM|CpuSSE4a)
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of