* h8300.h (UNOP3): Mark the register operand in this insn
as a source operand, not a destination operand. So the simulator can handle shal #2,er0 correctly.
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@ -1,3 +1,14 @@
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start-sanitize-h8s
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Tue Jul 2 13:20:19 1996 Jeffrey A Law (law@cygnus.com)
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* h8300.h (UNOP3): Mark the register operand in this insn
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as a source operand, not a destination operand.
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end-sanitize-h8s
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Fri Jun 21 13:52:17 1996 Richard Henderson <rth@tamu.edu>
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* alpha.h: New file.
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Thu Jun 20 15:02:57 1996 Ian Lance Taylor <ian@cygnus.com>
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Thu Jun 20 15:02:57 1996 Ian Lance Taylor <ian@cygnus.com>
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* rs6k.h: Remove obsolete file.
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* rs6k.h: Remove obsolete file.
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@ -208,9 +208,9 @@ struct h8_opcode
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{ O(code,SW), 0, 2, name, {OR16, E, 0}, {op1, op2, op3+1, OR16, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
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{ O(code,SW), 0, 2, name, {OR16, E, 0}, {op1, op2, op3+1, OR16, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
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{ O(code,SL), 0, 2, name, {OR32, E, 0}, {op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}, 0, 0, 0, 0} \
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{ O(code,SL), 0, 2, name, {OR32, E, 0}, {op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}, 0, 0, 0, 0} \
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/* start-sanitize-h8s */\
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/* start-sanitize-h8s */\
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,{ O(code,SB), 1, 2, name, {SHIFT_IMM, RD8, E}, {op1, op2, op3+4, RD8, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
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,{ O(code,SB), 1, 2, name, {SHIFT_IMM, RS8, E}, {op1, op2, op3+4, RS8, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
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{ O(code,SW), 0, 2, name, {SHIFT_IMM, RD16, E}, {op1, op2, op3+5, RD16, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
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{ O(code,SW), 0, 2, name, {SHIFT_IMM, RS16, E}, {op1, op2, op3+5, RS16, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
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{ O(code,SL), 0, 2, name, {SHIFT_IMM, RD32, E}, {op1, op2, op3+7, RD32|B30, E, 0, 0, 0, 0}, 0, 0, 0, 0} \
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{ O(code,SL), 0, 2, name, {SHIFT_IMM, RS32, E}, {op1, op2, op3+7, RS32|B30, E, 0, 0, 0, 0}, 0, 0, 0, 0} \
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/* end-sanitize-h8s */ \
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/* end-sanitize-h8s */ \
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