OpenE2K
/
binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

x86-64: Also optimize "clr reg64" 

"clr reg" is an alias of "xor reg, reg".  We can encode "clr reg64" as
"xor reg32, reg32".

gas/

	* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
	as "xor reg32, reg32".
	* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
	* testsuite/gas/i386/x86-64-optimize-1.d: Updated.

opcodes/

	* i386-opc.tbl: Add Optimize to clr.
	* i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu 2018-03-08 06:41:34 -08:00
parent 347a87745e
commit d3d50934a9
7 changed files with 30 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
as "xor reg32, reg32".
* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
* testsuite/gas/i386/x86-64-optimize-1.d: Updated.
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention -mold-gcc removal.

19
gas/config/tc-i386.c
View File

@ -3801,7 +3801,8 @@ optimize_encoding (void)
}
}
else if (flag_code == CODE_64BIT
&& ((i.reg_operands == 1
&& ((i.types[1].bitfield.qword
&& i.reg_operands == 1
&& i.imm_operands == 1
&& i.op[0].imms->X_op == O_constant
&& ((i.tm.base_opcode == 0xb0
@ -3816,12 +3817,16 @@ optimize_encoding (void)
|| ((i.tm.base_opcode == 0xf6
|| i.tm.base_opcode == 0xc6)
&& i.tm.extension_opcode == 0x0)))))
|| (i.reg_operands == 2
&& i.op[0].regs == i.op[1].regs
&& ((i.tm.base_opcode == 0x30
|| i.tm.base_opcode == 0x28)
&& i.tm.extension_opcode == None)))
&& i.types[1].bitfield.qword)
|| (i.types[0].bitfield.qword
&& ((i.reg_operands == 2
&& i.op[0].regs == i.op[1].regs
&& ((i.tm.base_opcode == 0x30
|| i.tm.base_opcode == 0x28)
&& i.tm.extension_opcode == None))
|| (i.reg_operands == 1
&& i.operands == 1
&& i.tm.base_opcode == 0x30
&& i.tm.extension_opcode == None)))))
{
/* Optimize: -O:
andq $imm31, %r64 -> andl $imm31, %r32

2
gas/testsuite/gas/i386/x86-64-optimize-1.d
View File

@ -50,4 +50,6 @@ Disassembly of section .text:
+[a-f0-9]+: b8 ff 03 00 00 mov \$0x3ff,%eax
+[a-f0-9]+: 48 b8 00 00 00 00 01 00 00 00 movabs \$0x100000000,%rax
+[a-f0-9]+: 48 b8 00 00 00 00 01 00 00 00 movabs \$0x100000000,%rax
+[a-f0-9]+: 31 c0 xor %eax,%eax
+[a-f0-9]+: 45 31 f6 xor %r14d,%r14d
#pass

2
gas/testsuite/gas/i386/x86-64-optimize-1.s
View File

@ -45,3 +45,5 @@ _start:
movq $1023,%rax
mov $0x100000000,%rax
movq $0x100000000,%rax
clrq %rax
clrq %r14

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add Optimize to clr.
* i386-tbl.h: Regenerated.
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove OldGcc.

2
opcodes/i386-opc.tbl
View File

@ -205,7 +205,7 @@ xor, 2, 0x34, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byt
xor, 2, 0x80, 0x6, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
// clr with 1 operand is really xor with 2 operands.
clr, 1, 0x30, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|RegKludge, { Reg8|Reg16|Reg32|Reg64 }
clr, 1, 0x30, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 }
adc, 2, 0x10, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
adc, 2, 0x83, 0x2, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }

2
opcodes/i386-tbl.h
View File

@ -2115,7 +2115,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } },
{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,