[ gas/ChangeLog ]

* config/tc-mips.c (macro_build): Add case 'k' to handle cache
	instruction.
	(macro): Add new case M_CACHE_AB.

	[ opcodes/ChangeLog ]
	* mips-opc.c: Add macro for cache instruction.

	[ include/opcode/ChangeLog ]
	* mips.h (enum): Add macro M_CACHE_AB.
This commit is contained in:
Thiemo Seufer 2006-05-05 15:41:23 +00:00
parent 77df29685b
commit d43b4baf07
6 changed files with 28 additions and 0 deletions

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@ -1,3 +1,10 @@
2006-05-05 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* config/tc-mips.c (macro_build): Add case 'k' to handle cache
instruction.
(macro): Add new case M_CACHE_AB.
2006-05-04 Kazu Hirata <kazu@codesourcery.com>
* config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.

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@ -3196,6 +3196,10 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
insn.insn_opcode |= va_arg (args, unsigned long);
continue;
case 'k':
insn.insn_opcode |= va_arg (args, unsigned long) << OP_SH_CACHE;
continue;
default:
internalError ();
}
@ -5820,6 +5824,9 @@ macro (struct mips_cl_insn *ip)
case M_SCD_AB:
s = "scd";
goto st;
case M_CACHE_AB:
s = "cache";
goto st;
case M_SDC1_AB:
if (mips_opts.arch == CPU_R4650)
{
@ -5857,6 +5864,8 @@ macro (struct mips_cl_insn *ip)
|| mask == M_L_DAB
|| mask == M_S_DAB)
fmt = "T,o(b)";
else if (mask == M_CACHE_AB)
fmt = "k,o(b)";
else if (coproc)
fmt = "E,o(b)";
else

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@ -1,3 +1,8 @@
2006-05-05 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips.h (enum): Add macro M_CACHE_AB.
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>

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@ -646,6 +646,7 @@ enum
M_BNE,
M_BNE_I,
M_BNEL_I,
M_CACHE_AB,
M_DABS,
M_DADD_I,
M_DADDU_I,

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@ -1,3 +1,8 @@
2006-05-05 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips-opc.c: Add macro for cache instruction.
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>

View File

@ -465,6 +465,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3},
{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3},
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },