[ARM] Support for ARMv8.1 Adv.SIMD extension
This commit is contained in:
Matthew Wahab
Jiong Wang
parent
ddfded2f7b
commit
d6b4b13ed2
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@ -259,6 +259,8 @@ static const arm_feature_set fpu_crypto_ext_armv8 =
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ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
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static const arm_feature_set crc_ext_armv8 =
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ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
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static const arm_feature_set fpu_neon_ext_v8_1 =
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ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA);
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static int mfloat_abi_opt = -1;
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/* Record user cpu selection for object attributes. */
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@ -12916,6 +12918,8 @@ struct neon_tab_entry
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X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
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X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
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X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
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X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
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X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
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X(vshl, 0x0000400, N_INV, 0x0800510), \
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X(vqshl, 0x0000410, N_INV, 0x0800710), \
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X(vand, 0x0000110, N_INV, 0x0800030), \
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@ -19815,6 +19819,11 @@ static const struct asm_opcode insns[] =
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NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
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NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
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NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
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/* ARM v8.1 extension. */
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nUF(vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
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nUF(vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
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nUF(vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
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nUF(vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
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/* Two address, int/float. Types S8 S16 S32 F32. */
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NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
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@ -24698,6 +24707,9 @@ static const struct arm_option_extension_value_table arm_extensions[] =
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| ARM_EXT_DIV),
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ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
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ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8,
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ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
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ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
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ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ANY),
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{ NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE }
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@ -24755,6 +24767,7 @@ static const struct arm_option_fpu_value_table arm_fpus[] =
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{"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
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{"crypto-neon-fp-armv8",
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FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
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{"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
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{NULL, ARM_ARCH_NONE}
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};
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@ -179,7 +179,9 @@ architectures),
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@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
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@code{virt} (Virtualization Extensions for v7-A architecture, implies
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@code{idiv}),
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@code{pan} (Priviliged Access Never Extensions for v8-A architecture)
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@code{pan} (Priviliged Access Never Extensions for v8-A architecture),
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@code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
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@code{simd})
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and
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@code{xscale}.
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@ -271,8 +273,9 @@ The following format options are recognized:
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@code{neon},
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@code{neon-vfpv4},
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@code{neon-fp-armv8},
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and
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@code{crypto-neon-fp-armv8}.
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and
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@code{neon-fp-armv8-1},
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In addition to determining which instructions are assembled, this option
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also affects the way in which the @code{.double} assembler directive behaves
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@ -85,6 +85,7 @@
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#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */
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#define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */
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#define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */
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#define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */
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/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
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defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
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@ -203,6 +204,11 @@
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#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
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ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
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#define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
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#define FPU_ARCH_NEON_VFP_ARMV8_1 \
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ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
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| FPU_VFP_ARMV8 \
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| FPU_NEON_EXT_RDMA)
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#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
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@ -1194,6 +1194,12 @@ static const struct opcode32 neon_opcodes[] =
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0xf2000a10, 0xfe800f10,
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"vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
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0xf3000b10, 0xff800f10,
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"vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
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0xf3000c10, 0xff800f10,
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"vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
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/* One register and an immediate value. */
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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@ -1447,6 +1453,19 @@ static const struct opcode32 neon_opcodes[] =
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0xf2800a40, 0xfe800f50,
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"vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
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0xf2800e40, 0xff800f50,
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"vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
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0xf2800f40, 0xff800f50,
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"vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
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0xf3800e40, 0xff800f50,
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"vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
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0xf3800f40, 0xff800f50,
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"vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
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},
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/* Element and structure load/store. */
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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