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[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction. 

ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
	architectural support for system register.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
	* gas/aarch64/sysreg-2.s: Add uses of dc instruction.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
	(aarch64_sys_ins_reg_supported_p): New.

Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
This commit is contained in:
Matthew Wahab 2015-12-10 16:38:44 +00:00
parent ea2deeec92
commit d6bf7ce6c2
9 changed files with 51 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
architectural support for system register.
2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation

4
gas/config/tc-aarch64.c
View File

@ -3687,6 +3687,10 @@ parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
if (!o)
return NULL;
if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
as_bad (_("selected processor does not support system register "
"name '%s'"), buf);
*str = q;
return o;
}

5
gas/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
* gas/aarch64/sysreg-2.s: Add uses of dc instruction.
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/uao-directive.d: New.

3
gas/testsuite/gas/aarch64/sysreg-2.d
View File

@ -27,3 +27,6 @@ Disassembly of section .text:
[0-9a-f]+: d518c125 msr disr_el1, x5
[0-9a-f]+: d538c125 mrs x5, disr_el1
[0-9a-f]+: d53cc125 mrs x5, vdisr_el2
[0-9a-f]+: d50b7a20 dc cvac, x0
[0-9a-f]+: d50b7b21 dc cvau, x1
[0-9a-f]+: d50b7c22 dc cvap, x2

6
gas/testsuite/gas/aarch64/sysreg-2.s
View File

@ -30,3 +30,9 @@
rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
/* DC CVAP. */
dc cvac, x0
dc cvau, x1
dc cvap, x2

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.

3
include/opcode/aarch64.h
View File

@ -676,6 +676,9 @@ typedef struct
} aarch64_sys_ins_reg;
extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
extern bfd_boolean
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
const aarch64_sys_ins_reg *);
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
(aarch64_sys_ins_reg_supported_p): New.
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt

16
opcodes/aarch64-opc.c
View File

@ -3264,6 +3264,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
{ "cvac", CPENS (3, C7, C10, 1), F_HASXT },
{ "csw", CPENS (0, C7, C10, 2), F_HASXT },
{ "cvau", CPENS (3, C7, C11, 1), F_HASXT },
{ "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
{ "civac", CPENS (3, C7, C14, 1), F_HASXT },
{ "cisw", CPENS (0, C7, C14, 2), F_HASXT },
{ 0, CPENS(0,0,0,0), 0 }
@ -3329,6 +3330,21 @@ aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
return (sys_ins_reg->flags & F_HASXT) != 0;
}
extern bfd_boolean
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
const aarch64_sys_ins_reg *reg)
{
if (!(reg->flags & F_ARCHEXT))
return TRUE;
/* DC CVAP. Values are from aarch64_sys_regs_dc. */
if (reg->value == CPENS (3, C7, C12, 1)
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
return TRUE;
}
#undef C0
#undef C1
#undef C2