[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support for the instruction to binutils, enabled when -march=armv8.2-a is selected. gas/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_sys_ins_reg): Add check of architectural support for system register. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Add tests for dc instruction. * gas/aarch64/sysreg-2.s: Add uses of dc instruction. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". (aarch64_sys_ins_reg_supported_p): New. Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
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@ -1,3 +1,8 @@
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
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architectural support for system register.
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2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com>
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2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com>
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* doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation
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* doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation
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@ -3687,6 +3687,10 @@ parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
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if (!o)
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if (!o)
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return NULL;
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return NULL;
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if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
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as_bad (_("selected processor does not support system register "
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"name '%s'"), buf);
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*str = q;
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*str = q;
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return o;
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return o;
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}
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}
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@ -1,3 +1,8 @@
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
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* gas/aarch64/sysreg-2.s: Add uses of dc instruction.
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* gas/aarch64/uao-directive.d: New.
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* gas/aarch64/uao-directive.d: New.
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@ -27,3 +27,6 @@ Disassembly of section .text:
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[0-9a-f]+: d518c125 msr disr_el1, x5
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[0-9a-f]+: d518c125 msr disr_el1, x5
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[0-9a-f]+: d538c125 mrs x5, disr_el1
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[0-9a-f]+: d538c125 mrs x5, disr_el1
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[0-9a-f]+: d53cc125 mrs x5, vdisr_el2
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[0-9a-f]+: d53cc125 mrs x5, vdisr_el2
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[0-9a-f]+: d50b7a20 dc cvac, x0
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[0-9a-f]+: d50b7b21 dc cvau, x1
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[0-9a-f]+: d50b7c22 dc cvap, x2
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@ -30,3 +30,9 @@
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rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
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/* DC CVAP. */
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dc cvac, x0
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dc cvau, x1
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dc cvap, x2
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@ -1,3 +1,7 @@
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
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* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
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@ -676,6 +676,9 @@ typedef struct
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} aarch64_sys_ins_reg;
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} aarch64_sys_ins_reg;
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extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
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extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
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extern bfd_boolean
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aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
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const aarch64_sys_ins_reg *);
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extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
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extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
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extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
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extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
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@ -1,3 +1,8 @@
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
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(aarch64_sys_ins_reg_supported_p): New.
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
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* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
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@ -3264,6 +3264,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
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{ "cvac", CPENS (3, C7, C10, 1), F_HASXT },
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{ "cvac", CPENS (3, C7, C10, 1), F_HASXT },
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{ "csw", CPENS (0, C7, C10, 2), F_HASXT },
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{ "csw", CPENS (0, C7, C10, 2), F_HASXT },
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{ "cvau", CPENS (3, C7, C11, 1), F_HASXT },
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{ "cvau", CPENS (3, C7, C11, 1), F_HASXT },
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{ "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
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{ "civac", CPENS (3, C7, C14, 1), F_HASXT },
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{ "civac", CPENS (3, C7, C14, 1), F_HASXT },
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{ "cisw", CPENS (0, C7, C14, 2), F_HASXT },
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{ "cisw", CPENS (0, C7, C14, 2), F_HASXT },
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{ 0, CPENS(0,0,0,0), 0 }
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{ 0, CPENS(0,0,0,0), 0 }
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@ -3329,6 +3330,21 @@ aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
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return (sys_ins_reg->flags & F_HASXT) != 0;
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return (sys_ins_reg->flags & F_HASXT) != 0;
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}
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}
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extern bfd_boolean
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aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
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const aarch64_sys_ins_reg *reg)
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{
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if (!(reg->flags & F_ARCHEXT))
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return TRUE;
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/* DC CVAP. Values are from aarch64_sys_regs_dc. */
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if (reg->value == CPENS (3, C7, C12, 1)
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&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
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return FALSE;
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return TRUE;
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}
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#undef C0
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#undef C0
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#undef C1
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#undef C1
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#undef C2
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#undef C2
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