Enable building the s12z target on Solaris hosts where REG_Y is defined in system header files.
* opcode/s12z.h: Undef REG_Y.
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@ -1,3 +1,7 @@
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2020-01-02 Christian Biesinger <cbiesinger@google.com>
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* opcode/s12z.h: Undef REG_Y.
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2020-01-01 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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@ -2,25 +2,30 @@
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#define S12Z_H
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/* This byte is used to prefix instructions in "page 2" of the opcode
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space */
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space. */
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#define PAGE2_PREBYTE (0x1b)
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struct reg
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{
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char *name; /* The canonical name of the register */
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int bytes; /* its size, in bytes */
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char *name; /* The canonical name of the register. */
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int bytes; /* its size, in bytes. */
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};
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/* How many registers do we have. Actually there are only 13,
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because CCL and CCH are the low and high bytes of CCW. But
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for assemnbly / disassembly purposes they are considered
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distinct registers. */
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distinct registers. */
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#define S12Z_N_REGISTERS 15
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extern const struct reg registers[S12Z_N_REGISTERS];
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enum {
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/* Solaris defines REG_Y in sys/regset.h; undef it here to avoid
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breaking compilation when this target is enabled. */
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#undef REG_Y
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enum
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{
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REG_D2 = 0,
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REG_D3,
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REG_D4,
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@ -38,7 +43,7 @@ enum {
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REG_CCW
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};
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/* Any of the registers d0, d1, ... d7 */
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/* Any of the registers d0, d1, ... d7. */
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#define REG_BIT_Dn \
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((0x1U << REG_D2) | \
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(0x1U << REG_D3) | \
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@ -49,23 +54,22 @@ enum {
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(0x1U << REG_D0) | \
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(0x1U << REG_D1))
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/* Any of the registers x, y or z */
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/* Any of the registers x, y or z. */
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#define REG_BIT_XYS \
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((0x1U << REG_X) | \
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(0x1U << REG_Y) | \
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(0x1U << REG_S))
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/* Any of the registers x, y, z or p */
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/* Any of the registers x, y, z or p. */
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#define REG_BIT_XYSP \
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((0x1U << REG_X) | \
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(0x1U << REG_Y) | \
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(0x1U << REG_S) | \
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(0x1U << REG_P))
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/* The x register or the y register */
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/* The x register or the y register. */
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#define REG_BIT_XY \
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((0x1U << REG_X) | \
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(0x1U << REG_Y))
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#endif
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