OpenE2K
/
binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

opcodes,gas: sparc: fix mnemonic of faligndatai 

opcodes/ChangeLog:

2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.

gas/ChangeLog:

2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai.
	* testsuite/gas/sparc/sparc5vis4.d: Likewise.
This commit is contained in:
Jose E. Marchesi 2016-05-09 04:09:53 -07:00
parent 6eb7d83039
commit d751b79ea6
5 changed files with 14 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai.
* testsuite/gas/sparc/sparc5vis4.d: Likewise.
2016-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (fpu_arch_vfp_v1): Mark with ATTRIBUTE_UNUSED.

2
gas/testsuite/gas/sparc/sparc5vis4.d
View File

@ -35,4 +35,4 @@ Disassembly of section .text:
64: 95 b1 aa c8 fpsubs8 %f6, %f8, %f10
68: 9d b2 aa ec fpsubus8 %f10, %f12, %f14
6c: a5 b3 aa 70 fpsubus16 %f14, %f16, %f18
70: bf b0 09 3f faligndatai %f0, %f62, %f4, %f62
70: bf b0 09 3f faligndata %f0, %f62, %f4, %f62

2
gas/testsuite/gas/sparc/sparc5vis4.s
View File

@ -28,4 +28,4 @@
fpsubs8 %f6, %f8, %f10
fpsubus8 %f10, %f12, %f14
fpsubus16 %f14, %f16, %f18
faligndatai %f0, %f62, %f4, %f62
faligndata %f0, %f62, %f4, %f62

4
opcodes/ChangeLog
View File

@ -1,3 +1,7 @@
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
* arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.

7
opcodes/sparc-opc.c
View File

@ -1834,7 +1834,8 @@ SLCBCC("cbnefr", 15),
{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, 0, v9a },
{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, 0, v9a },
{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, 0, v9a },
{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, 0, v9a }, /* faligndatag */
{ "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9b }, /* faligndatai */
{ "fzerod", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, 0, v9a },
{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, 0, v9a },
@ -2058,13 +2059,11 @@ SLCBCC("cbnefr", 15),
{ "mwait", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|RS1_G0|ASI(~0), "2", 0, 0, HWCAP2_MWAIT, v9b }, /* mwait r */
{ "mwait", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28)|RS1_G0, "i", 0, 0, HWCAP2_MWAIT, v9b }, /* mwait imm */
/* SPARC5 and VIS4.0 instructions. */
/* Other SPARC5 and VIS4.0 instructions. */
{ "subxc", F3(2, 0x36, 0)|OPF(0x41), F3(~2, ~0x36, ~0)|OPF(~0x41), "1,2,d", 0, 0, HWCAP2_SPARC5, v9b },
{ "subxccc", F3(2, 0x36, 0)|OPF(0x43), F3(~2, ~0x36, ~0)|OPF(~0x43), "1,2,d", 0, 0, HWCAP2_SPARC5, v9b },
{ "faligndatai", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9b },
{ "fpadd8", F3F(2, 0x36, 0x124), F3F(~2, ~0x36, ~0x124), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
{ "fpadds8", F3F(2, 0x36, 0x126), F3F(~2, ~0x36, ~0x126), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
{ "fpaddus8", F3F(2, 0x36, 0x127), F3F(~2, ~0x36, ~0x127), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },