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RISC-V: Make objdump disassembly work right for binary files.

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Without the ELF header to set info->endian, it ends up as BFD_UNKNOWN_ENDIAN
which gets printed as big-endian.  But RISC-V instructions are always little
endian, so we can set endian_code correctly, and then set display_endian from
that.  This is similar to how the aarch64 support works, but without the
support for constant pools, as we don't have that on RISC-V.

	opcodes/
	PR binutils/24739
	* riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
	Set info->display_endian to info->endian_code.
This commit is contained in:
Jim Wilson 2019-06-26 17:17:09 -07:00
parent 696d5b3801
commit d7560e2df5
2 changed files with 12 additions and 2 deletions
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6
opcodes/ChangeLog
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@ -1,3 +1,9 @@
2019-06-26 Jim Wilson <jimw@sifive.com>
PR binutils/24739
* riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
Set info->display_endian to info->endian_code.
2019-06-25 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG

6
opcodes/riscv-dis.c
View File

@ -395,9 +395,13 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
insnlen = riscv_insn_length (word);
/* RISC-V instructions are always little-endian. */
info->endian_code = BFD_ENDIAN_LITTLE;
info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
info->bytes_per_line = 8;
info->display_endian = info->endian;
/* We don't support constant pools, so this must be code. */
info->display_endian = info->endian_code;
info->insn_info_valid = 1;
info->branch_delay_insns = 0;
info->data_size = 0;