Check R_X86_64_32 overflow and allow R_X86_64_64 for x32.
bfd/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * archures.c (bfd_mach_i386_intel_syntax): New. (bfd_mach_i386_i8086): Updated. (bfd_mach_i386_i386): Likewise. (bfd_mach_x86_64): Likewise. (bfd_mach_x64_32): Likewise. (bfd_mach_i386_i386_intel_syntax): Likewise. (bfd_mach_x86_64_intel_syntax): Likewise. (bfd_mach_x64_32_intel_syntax): Likewise. (bfd_mach_l1om): Likewise. (bfd_mach_l1om_intel_syntax): Likewise. (bfd_mach_k1om): Likewise. (bfd_mach_k1om_intel_syntax): Likewise. * bfd-in2.h: Regenerated. * cpu-i386.c (bfd_i386_compatible): Check mach instead of bits_per_address. (bfd_x64_32_arch_intel_syntax): Set bits_per_address to 64. (bfd_x64_32_arch): Likewise. * elf64-x86-64.c: Include "libiberty.h". (x86_64_elf_howto_table): Append x32 R_X86_64_32. (elf_x86_64_rtype_to_howto): Support x32 R_X86_64_32. (elf_x86_64_reloc_type_lookup): Likewise. (elf_x86_64_reloc_name_lookup): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_check_relocs): Allow R_X86_64_64 relocations for x32. gas/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * config/tc-i386.c (handle_quad): Removed. (md_pseudo_table): Remove "quad". (tc_gen_reloc): Don't check BFD_RELOC_64 for disallow_64bit_reloc. (x86_dwarf2_addr_size): New. * config/tc-i386.h (x86_dwarf2_addr_size): New. (DWARF2_ADDR_SIZE): Likewise. gas/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * gas/i386/ilp32/ilp32.exp: Don't run inval. * gas/i386/ilp32/inval.l: Removed. * gas/i386/ilp32/inval.s: Likewise. * gas/i386/ilp32/quad.d: Expect R_X86_64_64 instead of R_X86_64_32. * gas/i386/ilp32/x86-64-pcrel.s: Add tests for movabs. * gas/i386/ilp32/x86-64-pcrel.d: Updated. ld/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * ld-x86-64/ilp32-6.d: New. * ld-x86-64/ilp32-6.s: Likewise. * ld-x86-64/ilp32-7.d: Likewise. * ld-x86-64/ilp32-7.s: Likewise. * ld-x86-64/ilp32-8.d: Likewise. * ld-x86-64/ilp32-8.s: Likewise. * ld-x86-64/ilp32-9.d: Likewise. * ld-x86-64/ilp32-9.s: Likewise. * ld-x86-64/x86-64.exp: Run ilp32-6, ilp32-7, ilp32-8 and ilp32-9. opcodes/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * i386-dis.c (print_insn): Optimize info->mach check.
This commit is contained in:
H.J. Lu
parent
c3f7b0e5a1
commit
d7921315ba
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@ -1,3 +1,34 @@
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2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/13048
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* archures.c (bfd_mach_i386_intel_syntax): New.
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(bfd_mach_i386_i8086): Updated.
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(bfd_mach_i386_i386): Likewise.
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(bfd_mach_x86_64): Likewise.
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(bfd_mach_x64_32): Likewise.
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(bfd_mach_i386_i386_intel_syntax): Likewise.
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(bfd_mach_x86_64_intel_syntax): Likewise.
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(bfd_mach_x64_32_intel_syntax): Likewise.
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(bfd_mach_l1om): Likewise.
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(bfd_mach_l1om_intel_syntax): Likewise.
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(bfd_mach_k1om): Likewise.
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(bfd_mach_k1om_intel_syntax): Likewise.
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* bfd-in2.h: Regenerated.
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* cpu-i386.c (bfd_i386_compatible): Check mach instead of
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bits_per_address.
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(bfd_x64_32_arch_intel_syntax): Set bits_per_address to 64.
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(bfd_x64_32_arch): Likewise.
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* elf64-x86-64.c: Include "libiberty.h".
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(x86_64_elf_howto_table): Append x32 R_X86_64_32.
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(elf_x86_64_rtype_to_howto): Support x32 R_X86_64_32.
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(elf_x86_64_reloc_type_lookup): Likewise.
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(elf_x86_64_reloc_name_lookup): Likewise.
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(elf_x86_64_relocate_section): Likewise.
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(elf_x86_64_check_relocs): Allow R_X86_64_64 relocations for x32.
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2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
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* elfxx-mips.c (check_br32): Fix return type.
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@ -183,19 +183,20 @@ DESCRIPTION
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.#define bfd_mach_mipsisa64r2 65
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.#define bfd_mach_mips_micromips 96
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. bfd_arch_i386, {* Intel 386 *}
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.#define bfd_mach_i386_i386 1
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.#define bfd_mach_i386_i8086 2
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.#define bfd_mach_i386_i386_intel_syntax 3
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.#define bfd_mach_x64_32 32
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.#define bfd_mach_x64_32_intel_syntax 33
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.#define bfd_mach_x86_64 64
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.#define bfd_mach_x86_64_intel_syntax 65
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.#define bfd_mach_i386_intel_syntax (1 << 0)
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.#define bfd_mach_i386_i8086 (1 << 1)
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.#define bfd_mach_i386_i386 (1 << 2)
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.#define bfd_mach_x86_64 (1 << 3)
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.#define bfd_mach_x64_32 (1 << 4)
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.#define bfd_mach_i386_i386_intel_syntax (bfd_mach_i386_i386 | bfd_mach_i386_intel_syntax)
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.#define bfd_mach_x86_64_intel_syntax (bfd_mach_x86_64 | bfd_mach_i386_intel_syntax)
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.#define bfd_mach_x64_32_intel_syntax (bfd_mach_x64_32 | bfd_mach_i386_intel_syntax)
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. bfd_arch_l1om, {* Intel L1OM *}
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.#define bfd_mach_l1om 66
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.#define bfd_mach_l1om_intel_syntax 67
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.#define bfd_mach_l1om (1 << 5)
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.#define bfd_mach_l1om_intel_syntax (bfd_mach_l1om | bfd_mach_i386_intel_syntax)
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. bfd_arch_k1om, {* Intel K1OM *}
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.#define bfd_mach_k1om 68
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.#define bfd_mach_k1om_intel_syntax 69
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.#define bfd_mach_k1om (1 << 6)
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.#define bfd_mach_k1om_intel_syntax (bfd_mach_k1om | bfd_mach_i386_intel_syntax)
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. bfd_arch_we32k, {* AT&T WE32xxx *}
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. bfd_arch_tahoe, {* CCI/Harris Tahoe *}
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. bfd_arch_i860, {* Intel 860 *}
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@ -1886,19 +1886,20 @@ enum bfd_architecture
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#define bfd_mach_mipsisa64r2 65
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#define bfd_mach_mips_micromips 96
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bfd_arch_i386, /* Intel 386 */
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#define bfd_mach_i386_i386 1
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#define bfd_mach_i386_i8086 2
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#define bfd_mach_i386_i386_intel_syntax 3
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#define bfd_mach_x64_32 32
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#define bfd_mach_x64_32_intel_syntax 33
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#define bfd_mach_x86_64 64
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#define bfd_mach_x86_64_intel_syntax 65
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#define bfd_mach_i386_intel_syntax (1 << 0)
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#define bfd_mach_i386_i8086 (1 << 1)
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#define bfd_mach_i386_i386 (1 << 2)
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#define bfd_mach_x86_64 (1 << 3)
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#define bfd_mach_x64_32 (1 << 4)
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#define bfd_mach_i386_i386_intel_syntax (bfd_mach_i386_i386 | bfd_mach_i386_intel_syntax)
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#define bfd_mach_x86_64_intel_syntax (bfd_mach_x86_64 | bfd_mach_i386_intel_syntax)
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#define bfd_mach_x64_32_intel_syntax (bfd_mach_x64_32 | bfd_mach_i386_intel_syntax)
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bfd_arch_l1om, /* Intel L1OM */
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#define bfd_mach_l1om 66
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#define bfd_mach_l1om_intel_syntax 67
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#define bfd_mach_l1om (1 << 5)
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#define bfd_mach_l1om_intel_syntax (bfd_mach_l1om | bfd_mach_i386_intel_syntax)
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bfd_arch_k1om, /* Intel K1OM */
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#define bfd_mach_k1om 68
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#define bfd_mach_k1om_intel_syntax 69
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#define bfd_mach_k1om (1 << 6)
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#define bfd_mach_k1om_intel_syntax (bfd_mach_k1om | bfd_mach_i386_intel_syntax)
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bfd_arch_we32k, /* AT&T WE32xxx */
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bfd_arch_tahoe, /* CCI/Harris Tahoe */
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bfd_arch_i860, /* Intel 860 */
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@ -31,7 +31,8 @@ bfd_i386_compatible (const bfd_arch_info_type *a,
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const bfd_arch_info_type *compat = bfd_default_compatible (a, b);
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/* Don't allow mixing x64_32 with x86_64. */
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if (compat && a->bits_per_address != b->bits_per_address)
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if (compat
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&& (a->mach & bfd_mach_x64_32) != (b->mach & bfd_mach_x64_32))
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compat = NULL;
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return compat;
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@ -40,7 +41,7 @@ bfd_i386_compatible (const bfd_arch_info_type *a,
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static const bfd_arch_info_type bfd_x64_32_arch_intel_syntax =
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{
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64, /* 64 bits in a word */
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32, /* 32 bits in an address */
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64, /* 64 bits in an address */
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8, /* 8 bits in a byte */
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bfd_arch_i386,
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bfd_mach_x64_32_intel_syntax,
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@ -104,7 +105,7 @@ static const bfd_arch_info_type i8086_arch =
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static const bfd_arch_info_type bfd_x64_32_arch =
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{
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64, /* 64 bits in a word */
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32, /* 32 bits in an address */
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64, /* 64 bits in an address */
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8, /* 8 bits in a byte */
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bfd_arch_i386,
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bfd_mach_x64_32,
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@ -30,6 +30,7 @@
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#include "objalloc.h"
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#include "hashtab.h"
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#include "dwarf2.h"
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#include "libiberty.h"
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#include "elf/x86-64.h"
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@ -178,7 +179,12 @@ static reloc_howto_type x86_64_elf_howto_table[] =
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/* GNU extension to record C++ vtable member usage. */
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HOWTO (R_X86_64_GNU_VTENTRY, 0, 4, 0, FALSE, 0, complain_overflow_dont,
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_bfd_elf_rel_vtable_reloc_fn, "R_X86_64_GNU_VTENTRY", FALSE, 0, 0,
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FALSE)
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FALSE),
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/* Use complain_overflow_bitfield on R_X86_64_32 for x32. */
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HOWTO(R_X86_64_32, 0, 2, 32, FALSE, 0, complain_overflow_bitfield,
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bfd_elf_generic_reloc, "R_X86_64_32", FALSE, 0xffffffff, 0xffffffff,
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FALSE)
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};
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#define IS_X86_64_PCREL_TYPE(TYPE) \
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@ -241,8 +247,15 @@ elf_x86_64_rtype_to_howto (bfd *abfd, unsigned r_type)
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{
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unsigned i;
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if (r_type < (unsigned int) R_X86_64_GNU_VTINHERIT
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|| r_type >= (unsigned int) R_X86_64_max)
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if (r_type == (unsigned int) R_X86_64_32)
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{
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if (ABI_64_P (abfd))
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i = r_type;
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else
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i = ARRAY_SIZE (x86_64_elf_howto_table) - 1;
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}
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else if (r_type < (unsigned int) R_X86_64_GNU_VTINHERIT
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|| r_type >= (unsigned int) R_X86_64_max)
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{
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if (r_type >= (unsigned int) R_X86_64_standard)
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{
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@ -276,15 +289,21 @@ elf_x86_64_reloc_type_lookup (bfd *abfd,
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}
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static reloc_howto_type *
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elf_x86_64_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
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elf_x86_64_reloc_name_lookup (bfd *abfd,
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const char *r_name)
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{
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unsigned int i;
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for (i = 0;
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i < (sizeof (x86_64_elf_howto_table)
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/ sizeof (x86_64_elf_howto_table[0]));
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i++)
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if (!ABI_64_P (abfd) && strcasecmp (r_name, "R_X86_64_32") == 0)
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{
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/* Get x32 R_X86_64_32. */
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reloc_howto_type *reloc
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= &x86_64_elf_howto_table[ARRAY_SIZE (x86_64_elf_howto_table) - 1];
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BFD_ASSERT (reloc->type == (unsigned int) R_X86_64_32);
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return reloc;
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}
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for (i = 0; i < ARRAY_SIZE (x86_64_elf_howto_table); i++)
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if (x86_64_elf_howto_table[i].name != NULL
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&& strcasecmp (x86_64_elf_howto_table[i].name, r_name) == 0)
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return &x86_64_elf_howto_table[i];
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@ -1396,14 +1415,6 @@ elf_x86_64_check_relocs (bfd *abfd, struct bfd_link_info *info,
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default:
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break;
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case R_X86_64_64:
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/* Allow R_X86_64_64 relocations in SEC_DEBUGGING sections
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when building shared libraries. */
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if (info->shared
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&& !info->executable
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&& (sec->flags & SEC_DEBUGGING) != 0)
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break;
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case R_X86_64_DTPOFF64:
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case R_X86_64_TPOFF64:
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case R_X86_64_PC64:
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@ -3022,7 +3033,12 @@ elf_x86_64_relocate_section (bfd *output_bfd,
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return FALSE;
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}
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howto = x86_64_elf_howto_table + r_type;
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if (r_type != (int) R_X86_64_32
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|| ABI_64_P (output_bfd))
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howto = x86_64_elf_howto_table + r_type;
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else
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howto = (x86_64_elf_howto_table
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+ ARRAY_SIZE (x86_64_elf_howto_table) - 1);
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r_symndx = htab->r_sym (rel->r_info);
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h = NULL;
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sym = NULL;
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@ -1,3 +1,14 @@
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2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/13048
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* config/tc-i386.c (handle_quad): Removed.
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(md_pseudo_table): Remove "quad".
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(tc_gen_reloc): Don't check BFD_RELOC_64 for disallow_64bit_reloc.
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(x86_dwarf2_addr_size): New.
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* config/tc-i386.h (x86_dwarf2_addr_size): New.
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(DWARF2_ADDR_SIZE): Likewise.
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2011-08-01 Nick Clifton <nickc@redhat.com>
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PR ld/12974
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@ -182,7 +182,6 @@ static void s_bss (int);
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#endif
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#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
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static void handle_large_common (int small ATTRIBUTE_UNUSED);
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static void handle_quad (int);
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#endif
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static const char *default_arch = DEFAULT_ARCH;
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@ -828,7 +827,6 @@ const pseudo_typeS md_pseudo_table[] =
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{"sse_check", set_sse_check, 0},
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#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
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{"largecomm", handle_large_common, 0},
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{"quad", handle_quad, 8},
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#else
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{"file", (void (*) (int)) dwarf2_directive_file, 0},
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{"loc", dwarf2_directive_loc, 0},
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@ -9059,7 +9057,6 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
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if (disallow_64bit_reloc)
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switch (code)
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{
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case BFD_RELOC_64:
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case BFD_RELOC_X86_64_DTPOFF64:
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case BFD_RELOC_X86_64_TPOFF64:
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case BFD_RELOC_64_PCREL:
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@ -9168,6 +9165,16 @@ tc_x86_frame_initial_instructions (void)
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cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
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}
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int
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x86_dwarf2_addr_size (void)
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{
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#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
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if (x86_elf_abi == X86_64_X32_ABI)
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return 4;
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#endif
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return bfd_arch_bits_per_address (stdoutput) / 8;
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}
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int
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i386_elf_section_type (const char *str, size_t len)
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{
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@ -9267,50 +9274,4 @@ handle_large_common (int small ATTRIBUTE_UNUSED)
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bss_section = saved_bss_section;
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}
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}
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static void
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handle_quad (int nbytes)
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{
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expressionS exp;
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if (x86_elf_abi != X86_64_X32_ABI)
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{
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cons (nbytes);
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return;
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}
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if (is_it_end_of_statement ())
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{
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demand_empty_rest_of_line ();
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return;
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}
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do
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{
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if (*input_line_pointer == '"')
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{
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as_bad (_("unexpected `\"' in expression"));
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ignore_rest_of_line ();
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return;
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}
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x86_cons (&exp, nbytes);
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/* Output 4 bytes if not constant. */
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if (exp.X_op != O_constant)
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nbytes = 4;
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emit_expr (&exp, (unsigned int) nbytes);
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/* Zero-extends to 8 bytes if not constant. */
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if (nbytes == 4)
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||||
{
|
||||
memset (&exp, '\0', sizeof (exp));
|
||||
exp.X_op = O_constant;
|
||||
emit_expr (&exp, nbytes);
|
||||
}
|
||||
nbytes = 8;
|
||||
}
|
||||
while (*input_line_pointer++ == ',');
|
||||
|
||||
input_line_pointer--; /* Put terminator back into stream. */
|
||||
|
||||
demand_empty_rest_of_line ();
|
||||
}
|
||||
#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
|
||||
|
|
|
|||
|
|
@ -279,6 +279,9 @@ extern unsigned int x86_dwarf2_return_column;
|
|||
extern int x86_cie_data_alignment;
|
||||
#define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
|
||||
|
||||
extern int x86_dwarf2_addr_size (void);
|
||||
#define DWARF2_ADDR_SIZE(bfd) x86_dwarf2_addr_size ()
|
||||
|
||||
#define tc_parse_to_dw2regnum tc_x86_parse_to_dw2regnum
|
||||
extern void tc_x86_parse_to_dw2regnum (expressionS *);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,17 @@
|
|||
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
PR ld/13048
|
||||
* gas/i386/ilp32/ilp32.exp: Don't run inval.
|
||||
|
||||
* gas/i386/ilp32/inval.l: Removed.
|
||||
* gas/i386/ilp32/inval.s: Likewise.
|
||||
|
||||
* gas/i386/ilp32/quad.d: Expect R_X86_64_64 instead of
|
||||
R_X86_64_32.
|
||||
|
||||
* gas/i386/ilp32/x86-64-pcrel.s: Add tests for movabs.
|
||||
* gas/i386/ilp32/x86-64-pcrel.d: Updated.
|
||||
|
||||
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
PR gas/13046
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check] &&
|
|||
}
|
||||
}
|
||||
|
||||
run_list_test "inval" "-al"
|
||||
run_list_test "reloc64" "--defsym _bad_=1"
|
||||
|
||||
set ASFLAGS "$old_ASFLAGS"
|
||||
|
|
|
|||
|
|
@ -1,23 +0,0 @@
|
|||
.*: Assembler messages:
|
||||
.*:3: Error: .*
|
||||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\.text
|
||||
[ ]*2[ ]+\# All the following should be illegal for x32
|
||||
[ ]*3[ ]+\?\?\?\? 48A10000 movabs xxx,%rax
|
||||
[ ]*3[ ]+00000000
|
||||
[ ]*3[ ]+0000
|
||||
[ ]*4[ ]+\?\?\?\? 48A10000 movabs foo,%rax
|
||||
[ ]*4[ ]+00000000
|
||||
[ ]*4[ ]+0000
|
||||
[ ]*5[ ]+\?\?\?\? 48A10000 movabsq xxx,%rax
|
||||
[ ]*5[ ]+00000000
|
||||
[ ]*5[ ]+0000
|
||||
[ ]*6[ ]+\?\?\?\? 48A10000 movabsq foo,%rax
|
||||
\*\*\*\* Error:cannot represent relocation type BFD_RELOC_[ ]*64[ ]+in x32 mode
|
||||
[ ]*6[ ]+00000000
|
||||
[ ]*6[ ]+0000
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
.text
|
||||
# All the following should be illegal for x32
|
||||
movabs xxx,%rax
|
||||
movabs foo,%rax
|
||||
movabsq xxx,%rax
|
||||
movabsq foo,%rax
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
#objdump: -sr
|
||||
#name: xquad
|
||||
#name: x86-64 (ILP32) quad
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
RELOCATION RECORDS FOR \[.data\]:
|
||||
OFFSET +TYPE +VALUE
|
||||
0+ R_X86_64_32 +foo
|
||||
0+10 R_X86_64_32 +bar
|
||||
0+20 R_X86_64_32 +foo
|
||||
0+30 R_X86_64_32 +bar
|
||||
0+ R_X86_64_64 +foo
|
||||
0+10 R_X86_64_64 +bar
|
||||
0+20 R_X86_64_64 +foo
|
||||
0+30 R_X86_64_64 +bar
|
||||
|
||||
|
||||
Contents of section .data:
|
||||
|
|
|
|||
|
|
@ -5,13 +5,15 @@
|
|||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+000 <_start>:
|
||||
[ ]*[0-9a-f]+:[ ]+b0 00[ ]+movb?[ ]+\$(0x)?0,%al[ ]*[0-9a-f]+:[ ]+R_X86_64_PC8[ ]+xtrn\+(0x)?1
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 00 00[ ]+movw?[ ]+\$(0x)?0,%ax[ ]*[0-9a-f]+:[ ]+R_X86_64_PC16[ ]+xtrn\+(0x)?2
|
||||
[ ]*[0-9a-f]+:[ ]+b8( 00){4}[ ]+movl?[ ]+\$(0x)?0,%eax[ ]*[0-9a-f]+:[ ]+R_X86_64_PC32[ ]+xtrn\+(0x)?1
|
||||
[ ]*[0-9a-f]+:[ ]+48 c7 c0( 00){4}[ ]+movq?[ ]+\$(0x)?0,%rax[ ]*[0-9a-f]+:[ ]+R_X86_64_PC32[ ]+xtrn\+(0x)?3
|
||||
[ ]*[0-9a-f]+:[ ]+b0 00[ ]+movb?[ ]+\$(0x)?0,%al[ ]*[0-9a-f]+:[ ]+R_X86_64_8[ ]+xtrn
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 00 00[ ]+movw?[ ]+\$(0x)?0,%ax[ ]*[0-9a-f]+:[ ]+R_X86_64_16[ ]+xtrn
|
||||
[ ]*[0-9a-f]+:[ ]+b8( 00){4}[ ]+movl?[ ]+\$(0x)?0,%eax[ ]*[0-9a-f]+:[ ]+R_X86_64_32[ ]+xtrn
|
||||
[ ]*[0-9a-f]+:[ ]+48 c7 c0( 00){4}[ ]+movq?[ ]+\$(0x)?0,%rax[ ]*[0-9a-f]+:[ ]+R_X86_64_32S[ ]+xtrn
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al 1: R_X86_64_PC8 xtrn\+0x1
|
||||
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax 4: R_X86_64_PC16 xtrn\+0x2
|
||||
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 7: R_X86_64_PC32 xtrn\+0x1
|
||||
[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax e: R_X86_64_PC32 xtrn\+0x3
|
||||
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al 13: R_X86_64_8 xtrn
|
||||
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax 16: R_X86_64_16 xtrn
|
||||
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 19: R_X86_64_32 xtrn
|
||||
[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax 20: R_X86_64_32S xtrn
|
||||
[ ]*[a-f0-9]+: 48 b8 00 00 00 00 00 00 00 00 movabs \$0x0,%rax 26: R_X86_64_64 xtrn
|
||||
[ ]*[a-f0-9]+: 48 a1 00 00 00 00 00 00 00 00 movabs 0x0,%rax 30: R_X86_64_64 xtrn
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -9,3 +9,5 @@ _start:
|
|||
movw $xtrn, %ax
|
||||
movl $xtrn, %eax
|
||||
movq $xtrn, %rax
|
||||
movabs $xtrn, %rax
|
||||
movabsq xtrn, %rax
|
||||
|
|
|
|||
|
|
@ -1,3 +1,17 @@
|
|||
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
PR ld/13048
|
||||
* ld-x86-64/ilp32-6.d: New.
|
||||
* ld-x86-64/ilp32-6.s: Likewise.
|
||||
* ld-x86-64/ilp32-7.d: Likewise.
|
||||
* ld-x86-64/ilp32-7.s: Likewise.
|
||||
* ld-x86-64/ilp32-8.d: Likewise.
|
||||
* ld-x86-64/ilp32-8.s: Likewise.
|
||||
* ld-x86-64/ilp32-9.d: Likewise.
|
||||
* ld-x86-64/ilp32-9.s: Likewise.
|
||||
|
||||
* ld-x86-64/x86-64.exp: Run ilp32-6, ilp32-7, ilp32-8 and ilp32-9.
|
||||
|
||||
2011-07-27 Roland McGrath <mcgrathr@google.com>
|
||||
|
||||
* ld-i386/vxworks1-lib.rd: Swap order of sections expected in output.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
#as: --x32
|
||||
#ld: -m elf32_x86_64 -Ttext-segment 0xe0000000
|
||||
#error: .*relocation truncated to fit: R_X86_64_32S.*
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
.globl _start
|
||||
_start:
|
||||
mov $_start,%rax
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#as: --x32
|
||||
#ld: -m elf32_x86_64 -Ttext-segment 0xe0000000
|
||||
#error: .*relocation truncated to fit: R_X86_64_32S.*
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
.globl _start
|
||||
_start:
|
||||
mov _start,%rax
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
#as: --x32
|
||||
#ld: -m elf32_x86_64 -Ttext-segment 0xe0000000
|
||||
#objdump: -dw
|
||||
|
||||
.*: +file format elf32-x86-64
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
e0000054 <_start>:
|
||||
[ ]*[a-f0-9]+: 48 b8 54 00 00 e0 00 00 00 00 movabs \$0xe0000054,%rax
|
||||
[ ]*[a-f0-9]+: 48 a1 54 00 00 e0 00 00 00 00 movabs 0xe0000054,%rax
|
||||
#pass
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
.text
|
||||
.globl _start
|
||||
_start:
|
||||
movabs $_start,%rax
|
||||
movabs _start,%rax
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#as: --x32
|
||||
#ld: -m elf32_x86_64 -Ttext-segment 0xe0000000
|
||||
#objdump: -s -j .text
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Contents of section .text:
|
||||
e0000054 540000e0 00000000 T.......
|
||||
#pass
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
.text
|
||||
.globl _start
|
||||
_start:
|
||||
.quad _start
|
||||
|
|
@ -203,6 +203,10 @@ run_dump_test "ilp32-2"
|
|||
run_dump_test "ilp32-3"
|
||||
run_dump_test "ilp32-4"
|
||||
run_dump_test "ilp32-5"
|
||||
run_dump_test "ilp32-6"
|
||||
run_dump_test "ilp32-7"
|
||||
run_dump_test "ilp32-8"
|
||||
run_dump_test "ilp32-9"
|
||||
run_dump_test "ia32-1"
|
||||
run_dump_test "ia32-2"
|
||||
run_dump_test "ia32-3"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
PR ld/13048
|
||||
* i386-dis.c (print_insn): Optimize info->mach check.
|
||||
|
||||
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
PR gas/13046
|
||||
|
|
|
|||
|
|
@ -11161,40 +11161,19 @@ print_insn (bfd_vma pc, disassemble_info *info)
|
|||
int prefix_length;
|
||||
int default_prefixes;
|
||||
|
||||
if (info->mach == bfd_mach_x86_64_intel_syntax
|
||||
|| info->mach == bfd_mach_x86_64
|
||||
|| info->mach == bfd_mach_x64_32_intel_syntax
|
||||
|| info->mach == bfd_mach_x64_32
|
||||
|| info->mach == bfd_mach_l1om
|
||||
|| info->mach == bfd_mach_l1om_intel_syntax
|
||||
|| info->mach == bfd_mach_k1om
|
||||
|| info->mach == bfd_mach_k1om_intel_syntax)
|
||||
address_mode = mode_64bit;
|
||||
else
|
||||
priv.orig_sizeflag = AFLAG | DFLAG;
|
||||
if ((info->mach & bfd_mach_i386_i386) != 0)
|
||||
address_mode = mode_32bit;
|
||||
else if (info->mach == bfd_mach_i386_i8086)
|
||||
{
|
||||
address_mode = mode_16bit;
|
||||
priv.orig_sizeflag = 0;
|
||||
}
|
||||
else
|
||||
address_mode = mode_64bit;
|
||||
|
||||
if (intel_syntax == (char) -1)
|
||||
intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
|
||||
|| info->mach == bfd_mach_x86_64_intel_syntax
|
||||
|| info->mach == bfd_mach_x64_32_intel_syntax
|
||||
|| info->mach == bfd_mach_l1om_intel_syntax
|
||||
|| info->mach == bfd_mach_k1om_intel_syntax);
|
||||
|
||||
if (info->mach == bfd_mach_i386_i386
|
||||
|| info->mach == bfd_mach_x86_64
|
||||
|| info->mach == bfd_mach_x64_32
|
||||
|| info->mach == bfd_mach_l1om
|
||||
|| info->mach == bfd_mach_k1om
|
||||
|| info->mach == bfd_mach_i386_i386_intel_syntax
|
||||
|| info->mach == bfd_mach_x86_64_intel_syntax
|
||||
|| info->mach == bfd_mach_x64_32_intel_syntax
|
||||
|| info->mach == bfd_mach_l1om_intel_syntax
|
||||
|| info->mach == bfd_mach_k1om_intel_syntax)
|
||||
priv.orig_sizeflag = AFLAG | DFLAG;
|
||||
else if (info->mach == bfd_mach_i386_i8086)
|
||||
priv.orig_sizeflag = 0;
|
||||
else
|
||||
abort ();
|
||||
intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
|
||||
|
||||
for (p = info->disassembler_options; p != NULL; )
|
||||
{
|
||||
|
|
@ -11299,8 +11278,7 @@ print_insn (bfd_vma pc, disassemble_info *info)
|
|||
/* The output looks better if we put 7 bytes on a line, since that
|
||||
puts most long word instructions on a single line. Use 8 bytes
|
||||
for Intel L1OM. */
|
||||
if (info->mach == bfd_mach_l1om
|
||||
|| info->mach == bfd_mach_l1om_intel_syntax)
|
||||
if ((info->mach & bfd_mach_l1om) != 0)
|
||||
info->bytes_per_line = 8;
|
||||
else
|
||||
info->bytes_per_line = 7;
|
||||
|
|
|
|||
Loading…
Reference in New Issue