MIPS16: Reassign 0' and 4' operand codes
Replace `0' and `4' operand codes with `.' and `F' respectively to free up the `0'-`4' consecutive range. No functional change. gas/ * config/tc-mips.c (mips16_macro_build): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_macro): Likewise. include/ * opcode/mips.h: Replace `0' and `4' operand codes with `.' and `F' respectively. opcodes/ * mips16-opc.c (decode_mips16_operand): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_opcodes): Likewise.
This commit is contained in:
Maciej W. Rozycki
parent
0674ee5dad
commit
d8722d7641
@ -1,3 +1,9 @@
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2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
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* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
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operand codes with `.' and `F' respectively.
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(mips16_macro): Likewise.
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2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
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* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
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@ -8758,15 +8758,15 @@ mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
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case ')':
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break;
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case '0':
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case '.':
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case 'S':
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case 'P':
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case 'R':
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break;
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case '<':
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case '4':
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case '5':
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case 'F':
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case 'H':
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case 'W':
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case 'D':
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@ -13531,7 +13531,7 @@ mips16_macro (struct mips_cl_insn *ip)
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s = "mfhi";
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do_div3:
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start_noreorder ();
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macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
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macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]);
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expr1.X_add_number = 2;
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macro_build (&expr1, "bnez", "x,p", op[2]);
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macro_build (NULL, "break", "6", 7);
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@ -13561,7 +13561,7 @@ mips16_macro (struct mips_cl_insn *ip)
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s2 = "mfhi";
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do_divu3:
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start_noreorder ();
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macro_build (NULL, s, "0,x,y", op[1], op[2]);
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macro_build (NULL, s, ".,x,y", op[1], op[2]);
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expr1.X_add_number = 2;
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macro_build (&expr1, "bnez", "x,p", op[2]);
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macro_build (NULL, "break", "6", 7);
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@ -13583,7 +13583,7 @@ mips16_macro (struct mips_cl_insn *ip)
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case M_SUBU_I:
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do_subu:
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imm_expr.X_add_number = -imm_expr.X_add_number;
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macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
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macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]);
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break;
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case M_SUBU_I_2:
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@ -1,3 +1,8 @@
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2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
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* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
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`F' respectively.
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2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
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* opcode/mips.h (INSN2_SHORT_ONLY): New macro.
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@ -1803,7 +1803,7 @@ extern int bfd_mips_num_opcodes;
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"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
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"v" 3 bit same register as source and destination (MIPS16OP_*_RX)
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"w" 3 bit same register as source and destination (MIPS16OP_*_RY)
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"0" zero register ($0)
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"." zero register ($0)
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"S" stack pointer ($sp or $29)
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"P" program counter
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"R" return address register ($ra or $31)
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@ -1823,8 +1823,8 @@ extern int bfd_mips_num_opcodes;
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"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
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"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
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"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
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"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
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"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
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"F" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
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"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
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"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
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"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
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@ -1844,9 +1844,9 @@ extern int bfd_mips_num_opcodes;
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"M" 7 bit register list for restore instruction (18 bit extended)
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Characters used so far, for quick reference when adding more:
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" 456 8 0"
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"[]<"
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"ABCDE HI KLM P RS UVWXYZ"
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" 56 8 "
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".[]<"
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"ABCDEF HI KLM P RS UVWXYZ"
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"a e ijklm pq vwxyz"
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*/
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@ -1,3 +1,9 @@
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2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
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* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
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operand codes with `.' and `F' respectively.
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(mips16_opcodes): Likewise.
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2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
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@ -49,7 +49,8 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
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{
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switch (type)
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{
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case '0': MAPPED_REG (0, 0, GP, reg_0_map);
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case '.': MAPPED_REG (0, 0, GP, reg_0_map);
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case '6': UINT (6, 5);
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case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
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@ -80,7 +81,6 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
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case '[': UINT (6, 0);
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case ']': UINT (6, 0);
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case '4': SINT (15, 0);
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case '5': SINT (16, 0);
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case '8': SINT (16, 0);
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@ -89,6 +89,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
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case 'C': SINT (16, 0);
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case 'D': SINT (16, 0);
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case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
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case 'F': SINT (15, 0);
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case 'H': SINT (16, 0);
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case 'K': SINT (16, 0);
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case 'U': UINT (16, 0);
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@ -107,7 +108,6 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
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case '[': INT_ADJ (3, 2, 8, 0, FALSE);
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case ']': INT_ADJ (3, 8, 8, 0, FALSE);
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case '4': SINT (4, 0);
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case '5': UINT (5, 0);
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case '8': UINT (8, 0);
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@ -116,6 +116,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
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case 'C': INT_ADJ (8, 0, 255, 3, FALSE); /* (0 .. 255) << 3 */
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case 'D': INT_ADJ (5, 0, 31, 3, FALSE); /* (0 .. 31) << 3 */
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case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE);
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case 'F': SINT (4, 0);
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case 'H': INT_ADJ (5, 0, 31, 1, FALSE); /* (0 .. 31) << 1 */
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case 'K': INT_ADJ (8, 0, 127, 3, FALSE); /* (-128 .. 127) << 3 */
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case 'U': UINT (8, 0);
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@ -184,14 +185,14 @@ const struct mips_opcode mips16_opcodes[] =
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{"nop", "", 0x6500, 0xffff, 0, SH|RD_16, I1, 0, 0 }, /* move $0,$Z */
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{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
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{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
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{"addiu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
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{"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
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{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
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{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
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{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
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{"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
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{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
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{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
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{"addu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
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{"addu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
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{"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
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{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
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{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
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@ -228,33 +229,33 @@ const struct mips_opcode mips16_opcodes[] =
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{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
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{"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
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{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
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{"daddiu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
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{"daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
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{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
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{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
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{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
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{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
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{"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
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{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
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{"daddu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
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{"daddu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
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{"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
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{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
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{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
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{"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
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{"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
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{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
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{"ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
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{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 },
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{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
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{"ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
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{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 },
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{"div", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
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{"div", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
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{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
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{"divu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
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{"divu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
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{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
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{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
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{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
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{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
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{"drem", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
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{"drem", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
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{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 },
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{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
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{"dremu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
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{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 },
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{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
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{"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 },
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@ -315,9 +316,9 @@ const struct mips_opcode mips16_opcodes[] =
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{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
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{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
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{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
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{"rem", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
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{"rem", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
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{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
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{"remu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
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{"remu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
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{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
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{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
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{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
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