Thu Dec 10 18:46:25 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30/div0s.cgs: New testcase. * sim/fr30/div0u.cgs: New testcase. * sim/fr30/div1.cgs: New testcase. * sim/fr30/div2.cgs: New testcase. * sim/fr30/div3.cgs: New testcase. * sim/fr30/div4s.cgs: New testcase. * sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros.
This commit is contained in:
Dave Brolley
parent
767d2de5d7
commit
d8d144a0ab
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@ -1,3 +1,13 @@
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Thu Dec 10 18:46:25 1998 Dave Brolley <brolley@cygnus.com>
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* sim/fr30/div0s.cgs: New testcase.
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* sim/fr30/div0u.cgs: New testcase.
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* sim/fr30/div1.cgs: New testcase.
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* sim/fr30/div2.cgs: New testcase.
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* sim/fr30/div3.cgs: New testcase.
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* sim/fr30/div4s.cgs: New testcase.
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* sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros.
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Tue Dec 8 13:16:53 1998 Dave Brolley <brolley@cygnus.com>
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* sim/fr30/testutils.inc (set_s_user): Correct Mask.
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@ -0,0 +1,64 @@
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# fr30 testcase for div0s $Ri
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global div0s
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div0s:
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; Test div0s $Rj,$Ri
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; example from the manual - negative dividend
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mvi_h_gr 0x0fffffff,r2
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mvi_h_dr 0x00000000,mdh
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mvi_h_dr 0xfffffff0,mdl
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set_dbits 0x0 ; Set opposite of expected
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set_cc 0x0f ; Condition codes should not change
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div0s r2
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test_cc 1 1 1 1
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test_h_gr 0x0fffffff,r2
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test_h_dr 0xffffffff,mdh
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test_h_dr 0xfffffff0,mdl
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test_dbits 0x3
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; negative divisor
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mvi_h_gr 0xffffffff,r2
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mvi_h_dr 0xffffffff,mdh
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mvi_h_dr 0x7fffffff,mdl
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set_dbits 0x1 ; Set opposite of expected
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set_cc 0x0f ; Condition codes should not change
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div0s r2
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test_cc 1 1 1 1
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test_h_gr 0xffffffff,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x7fffffff,mdl
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test_dbits 0x2
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; Both sign bits 0
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mvi_h_gr 0x0fffffff,r2
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mvi_h_dr 0xffffffff,mdh
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mvi_h_dr 0x7ffffff0,mdl
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set_dbits 0x3 ; Set opposite of expected
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set_cc 0x0f ; Condition codes should not change
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div0s r2
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test_cc 1 1 1 1
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test_h_gr 0x0fffffff,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x7ffffff0,mdl
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test_dbits 0x0
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; Both sign bits 1
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mvi_h_gr 0xffffffff,r2
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mvi_h_dr 0x00000000,mdh
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mvi_h_dr 0xffffffff,mdl
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set_dbits 0x2 ; Set opposite of expected
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set_cc 0x0f ; Condition codes should not change
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div0s r2
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test_cc 1 1 1 1
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test_h_gr 0xffffffff,r2
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test_h_dr 0xffffffff,mdh
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test_h_dr 0xffffffff,mdl
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test_dbits 0x1
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pass
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@ -0,0 +1,25 @@
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# fr30 testcase for div0u $Ri
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global div0u
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div0u:
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; Test div0u $Rj,$Ri
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; operand register has no effect
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mvi_h_gr 0xdeadbeef,r2
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0x0ffffff0,mdl
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set_dbits 0x3 ; Set opposite of expected
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set_cc 0x0f ; Condition codes should not change
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div0u r2
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test_cc 1 1 1 1
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test_h_gr 0xdeadbeef,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x0ffffff0,mdl
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test_dbits 0x0
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pass
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@ -0,0 +1,113 @@
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# fr30 testcase for div1 $Ri
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global div1
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div1:
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; Test div1 $Ri
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; example from the manual -- all status bits 0
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mvi_h_gr 0x00ffffff,r2
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mvi_h_dr 0x00ffffff,mdh
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mvi_h_dr 0x00000000,mdl
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set_dbits 0x0
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set_cc 0x00
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div1 r2
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test_cc 0 0 0 0
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test_dbits 0x0
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x00ffffff,mdh ; misprinted in manual?
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test_h_dr 0x00000001,mdl
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; D0 == 1
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set_dbits 0x1
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set_cc 0x00
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div1 r2
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test_cc 0 0 0 0
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test_dbits 0x1
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x01fffffe,mdh
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test_h_dr 0x00000002,mdl
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; D1 == 1
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set_dbits 0x2
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set_cc 0x00
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div1 r2
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test_cc 0 0 0 0
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test_dbits 0x2
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x03fffffc,mdh
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test_h_dr 0x00000004,mdl
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; D0 == 1, D1 == 1
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set_dbits 0x3
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set_cc 0x00
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div1 r2
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test_cc 0 0 0 0
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test_dbits 0x3
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x08fffff7,mdh
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test_h_dr 0x00000009,mdl
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; C == 1
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mvi_h_gr 0x11ffffef,r2
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set_dbits 0x0
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set_cc 0x00
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div1 r2
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test_cc 0 0 0 1
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test_dbits 0x0
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test_h_gr 0x11ffffef,r2
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test_h_dr 0x11ffffee,mdh
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test_h_dr 0x00000012,mdl
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; D0 == 1, C == 1
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mvi_h_gr 0x23ffffdd,r2
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set_dbits 0x1
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set_cc 0x00
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div1 r2
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test_cc 0 0 0 1
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test_dbits 0x1
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test_h_gr 0x23ffffdd,r2
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test_h_dr 0xffffffff,mdh
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test_h_dr 0x00000025,mdl
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; D1 == 1, C == 1
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mvi_h_gr 0x00000003,r2
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set_dbits 0x2
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set_cc 0x00
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div1 r2
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test_cc 0 0 0 1
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test_dbits 0x2
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test_h_gr 0x00000003,r2
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test_h_dr 0x00000001,mdh
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test_h_dr 0x0000004b,mdl
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; D0 == 1, D1 == 1, C == 1
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mvi_h_gr 0xfffffffe,r2
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set_dbits 0x3
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set_cc 0x00
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div1 r2
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test_cc 0 0 0 1
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test_dbits 0x3
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test_h_gr 0xfffffffe,r2
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test_h_dr 0x00000002,mdh
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test_h_dr 0x00000096,mdl
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; remainder is zero
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mvi_h_gr 0x00000004,r2
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set_dbits 0x0
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set_cc 0x00
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div1 r2
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test_cc 0 1 0 0
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test_dbits 0x0
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test_h_gr 0x00000004,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x0000012d,mdl
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pass
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@ -0,0 +1,120 @@
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# fr30 testcase for div2 $Ri
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global div2
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div2:
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; Test div2 $Ri
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; example from the manual -- all status bits 0
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mvi_h_gr 0x00ffffff,r2
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mvi_h_dr 0x00ffffff,mdh
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mvi_h_dr 0x0000000f,mdl
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set_dbits 0x0
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set_cc 0x00
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div2 r2
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test_cc 0 1 0 0
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test_dbits 0x0
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x0000000f,mdl
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; D0 == 1
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mvi_h_dr 0x00ffffff,mdh
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set_dbits 0x1
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set_cc 0x00
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div2 r2
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test_cc 0 1 0 0
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test_dbits 0x1
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x0000000f,mdl
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; D1 == 1
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mvi_h_dr 0x00ffffff,mdh
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set_dbits 0x2
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set_cc 0x00
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div2 r2
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test_cc 0 0 0 0
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test_dbits 0x2
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x00ffffff,mdh
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test_h_dr 0x0000000f,mdl
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; D0 == 1, D1 == 1
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set_dbits 0x3
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set_cc 0x00
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div2 r2
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test_cc 0 0 0 0
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test_dbits 0x3
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x00ffffff,mdh
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test_h_dr 0x0000000f,mdl
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; C == 1
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mvi_h_dr 0x11ffffee,mdh
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mvi_h_gr 0x11ffffef,r2
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set_dbits 0x0
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set_cc 0x00
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div2 r2
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test_cc 0 0 0 1
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test_dbits 0x0
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test_h_gr 0x11ffffef,r2
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test_h_dr 0x11ffffee,mdh
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test_h_dr 0x0000000f,mdl
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; D0 == 1, C == 1
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mvi_h_dr 0x23ffffdc,mdh
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mvi_h_gr 0x23ffffdd,r2
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set_dbits 0x1
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set_cc 0x00
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div2 r2
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test_cc 0 0 0 1
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test_dbits 0x1
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test_h_gr 0x23ffffdd,r2
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test_h_dr 0x23ffffdc,mdh
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test_h_dr 0x0000000f,mdl
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; D1 == 1, C == 1
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mvi_h_dr 0xfffffffd,mdh
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mvi_h_gr 0x00000004,r2
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set_dbits 0x2
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set_cc 0x00
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div2 r2
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test_cc 0 0 0 1
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test_dbits 0x2
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test_h_gr 0x00000004,r2
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test_h_dr 0xfffffffd,mdh
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test_h_dr 0x0000000f,mdl
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; D0 == 1, D1 == 1, C == 1
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mvi_h_dr 0x00000002,mdh
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mvi_h_gr 0xffffffff,r2
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set_dbits 0x3
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set_cc 0x00
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div2 r2
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test_cc 0 0 0 1
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test_dbits 0x3
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test_h_gr 0xffffffff,r2
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test_h_dr 0x00000002,mdh
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test_h_dr 0x0000000f,mdl
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; remainder is zero
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mvi_h_dr 0x00000004,mdh
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mvi_h_gr 0x00000004,r2
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set_dbits 0x0
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set_cc 0x00
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div2 r2
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test_cc 0 1 0 0
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test_dbits 0x0
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test_h_gr 0x00000004,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x0000000f,mdl
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pass
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@ -0,0 +1,34 @@
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# fr30 testcase for div3
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global div3
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div3:
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; Test div3
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; example from the manual
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mvi_h_gr 0x00ffffff,r2
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mvi_h_dr 0x00000000,mdh
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mvi_h_dr 0x0000000f,mdl
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set_dbits 0x0
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set_cc 0x04
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div3
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test_cc 0 1 0 0
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test_dbits 0x0
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x00000010,mdl
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set_dbits 0x0
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set_cc 0x00
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div3
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test_cc 0 0 0 0
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test_dbits 0x0
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x00000010,mdl
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pass
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@ -0,0 +1,34 @@
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# fr30 testcase for div4s
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global div4s
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div4s:
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; Test div4s
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; example from the manual
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mvi_h_gr 0x00ffffff,r2
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mvi_h_dr 0x00000000,mdh
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mvi_h_dr 0x0000000f,mdl
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set_dbits 0x3
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set_cc 0x0f
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div4s
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test_cc 1 1 1 1
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test_dbits 0x3
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0xfffffff1,mdl
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set_dbits 0x0
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set_cc 0x00
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div4s
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test_cc 0 0 0 0
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test_dbits 0x0
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test_h_gr 0x00ffffff,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0xfffffff1,mdl
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pass
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@ -45,6 +45,12 @@ _start:
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ldi32 \val,\reg
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.endm
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; Load an immediate value into a dedicated register
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.macro mvi_h_dr val reg
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ldi32 \val,r0
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mov r0,\reg
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.endm
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; Load a general register into another general register
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.macro mvr_h_gr src targ
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mov \src,\targ
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fail
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test_cc\@:
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.endm
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; Set the division bits
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.macro set_dbits val
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mvr_h_gr ps,r5
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mvi_h_gr 0xfffff8ff,r4
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and r4,r5
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mvi_h_gr \val,r0
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mvi_h_gr 3,r4
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and r4,r0
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lsl 9,r0
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or r0,r5
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mvr_h_gr r5,ps
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.endm
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; Test the division bits
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.macro test_dbits val
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mvr_h_gr ps,r0
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lsr 9,r0
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mvi_h_gr 3,r4
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and r4,r0
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test_h_gr \val,r0
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.endm
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