From d98bb281e84ba33e1e19f67319f01e19c9c9c8e3 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Fri, 10 Aug 2001 16:22:08 +0000 Subject: [PATCH] * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32 argument. * mips-opc.c (G6): Undefine. (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro as the first "move" alternative. --- opcodes/ChangeLog | 8 ++++++++ opcodes/mips-dis.c | 2 +- opcodes/mips-opc.c | 4 +--- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d9dc0acd63..2a12444fa6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2001-08-10 Richard Sandiford + + * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32 + argument. + * mips-opc.c (G6): Undefine. + (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro + as the first "move" alternative. + 2001-08-10 Andreas Jaeger * configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 97f263d4df..eb18ff876b 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -469,7 +469,7 @@ print_insn_mips (memaddr, word, info) { register const char *d; - if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor, 0)) + if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor)) continue; (*info->fprintf_func) (info->stream, "%s", op->name); diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 3028b99e0f..ba4038bb8c 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -96,8 +96,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define G3 (I4 \ ) -#define G6 INSN_GP32 - /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either for arguments must apear in the correct order in this table for the @@ -121,7 +119,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */ {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ {"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 }, -{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1|G6 },/* or */ +{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 }, {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */ {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */ {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */