* interp.c (mips16_entry): Add support for floating point cases.
(SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
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@ -1,3 +1,16 @@
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Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
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* interp.c (mips16_entry): Add support for floating point cases.
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(SignalException): Pass floating point cases to mips16_entry.
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(ValueFPR): Don't restrict fmt_single and fmt_word to even
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registers.
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(StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
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or fmt_word.
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(COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
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and then set the state to fmt_uninterpreted.
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(COP_SW): Temporarily set the state to fmt_word while calling
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ValueFPR.
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Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
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* gencode.c (build_instruction): The high order may be set in the
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@ -1624,7 +1624,14 @@ sim_monitor(reason)
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uword64 paddr;
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int cca;
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if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
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V0 = callback->write(callback,(int)A0,(const char *)((int)paddr),(int)A2);
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{
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if (A0 == 1)
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V0 = callback->write_stdout(callback,(const char *)((int)paddr),
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(int)A2);
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else
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V0 = callback->write(callback,(int)A0,(const char *)((int)paddr),
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(int)A2);
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}
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else
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sim_error("Attempt to pass pointer that does not reference simulated memory");
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}
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@ -1895,11 +1902,11 @@ mips16_entry (insn)
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sregs = (insn & 0x0c0) >> 6;
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rreg = (insn & 0x020) >> 5;
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/* These should be checked by the caller. */
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if (aregs == 5 || aregs == 6 || sregs == 3)
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/* This should be checked by the caller. */
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if (sregs == 3)
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abort ();
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if (aregs != 7)
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if (aregs < 5)
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{
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int i;
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t_reg tsp;
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@ -1947,6 +1954,19 @@ mips16_entry (insn)
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SP += 32;
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if (aregs == 5)
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{
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FGR[0] = WORD64LO (GPR[4]);
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fpr_state[0] = fmt_uninterpreted;
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}
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else if (aregs == 6)
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{
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FGR[0] = WORD64LO (GPR[5]);
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FGR[1] = WORD64LO (GPR[4]);
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fpr_state[0] = fmt_uninterpreted;
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fpr_state[1] = fmt_uninterpreted;
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}
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PC = RA;
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}
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}
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@ -2704,8 +2724,6 @@ SignalException (int exception,...)
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simulate a handler for them. */
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else if ((IPC & 1) != 0
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&& (instruction & 0xf81f) == 0xe809
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&& (instruction & 0x700) != 0x500
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&& (instruction & 0x700) != 0x600
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&& (instruction & 0x0c0) != 0x0c0) {
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mips16_entry (instruction);
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break;
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@ -3000,7 +3018,7 @@ ValueFPR(fpr,fmt)
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err = -1;
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break;
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}
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} else if ((fpr & 1) == 0) { /* even registers only */
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} else {
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switch (fmt) {
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case fmt_single:
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case fmt_word:
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@ -3010,7 +3028,11 @@ ValueFPR(fpr,fmt)
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case fmt_uninterpreted:
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case fmt_double:
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case fmt_long:
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value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
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if ((fpr & 1) == 0) { /* even registers only */
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value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
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} else {
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SignalException (ReservedInstruction, 0);
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}
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break;
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default :
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@ -3061,23 +3083,27 @@ StoreFPR(fpr,fmt,value)
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err = -1;
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break;
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}
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} else if ((fpr & 1) == 0) { /* even register number only */
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} else {
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switch (fmt) {
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case fmt_single :
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case fmt_word :
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FGR[fpr+1] = 0xDEADC0DE;
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FGR[fpr] = (value & 0xFFFFFFFF);
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fpr_state[fpr + 1] = fmt;
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fpr_state[fpr] = fmt;
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break;
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case fmt_uninterpreted:
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case fmt_double :
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case fmt_long :
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FGR[fpr+1] = (value >> 32);
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FGR[fpr] = (value & 0xFFFFFFFF);
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fpr_state[fpr + 1] = fmt;
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fpr_state[fpr] = fmt;
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if ((fpr & 1) == 0) { /* even register number only */
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FGR[fpr+1] = (value >> 32);
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FGR[fpr] = (value & 0xFFFFFFFF);
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fpr_state[fpr + 1] = fmt;
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fpr_state[fpr] = fmt;
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} else {
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fpr_state[fpr] = fmt_unknown;
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fpr_state[fpr + 1] = fmt_unknown;
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SignalException (ReservedInstruction, 0);
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}
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break;
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default :
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@ -3754,7 +3780,8 @@ COP_LW(coproc_num,coproc_reg,memword)
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#ifdef DEBUG
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printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%08X%08X\n",memword,WORD64HI(memword),WORD64LO(memword));
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#endif
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StoreFPR(coproc_reg,fmt_uninterpreted,(uword64)memword);
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StoreFPR(coproc_reg,fmt_word,(uword64)memword);
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fpr_state[coproc_reg] = fmt_uninterpreted;
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break;
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#endif /* HASFPU */
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@ -3795,11 +3822,16 @@ COP_SW(coproc_num,coproc_reg)
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int coproc_num, coproc_reg;
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{
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unsigned int value = 0;
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FP_formats hold;
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switch (coproc_num) {
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#if defined(HASFPU)
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case 1:
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#if 1
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hold = fpr_state[coproc_reg];
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fpr_state[coproc_reg] = fmt_word;
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value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
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fpr_state[coproc_reg] = hold;
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#else
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#if 1
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value = (unsigned int)ValueFPR(coproc_reg,fpr_state[coproc_reg]);
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